From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org, Chet Douglas <chet.r.douglas@intel.com>
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: [RFC PATCH v2 28/28] cxl: Program decoders for regions
Date: Fri, 22 Oct 2021 11:37:09 -0700 [thread overview]
Message-ID: <20211022183709.1199701-29-ben.widawsky@intel.com> (raw)
In-Reply-To: <20211022183709.1199701-1-ben.widawsky@intel.com>
Do the HDM decoder programming for all endpoints and host bridges in a
region. Switches are currently unimplemented.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
drivers/cxl/cxl.h | 3 +
drivers/cxl/port.c | 196 +++++++++++++++++++++++++++++++++++++++++++
drivers/cxl/region.c | 33 +++++++-
3 files changed, 231 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 79d22992fddf..f2ee26ac2398 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -52,6 +52,7 @@
#define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4)
#define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9)
#define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10)
+#define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11)
#define CXL_HDM_DECODER0_CTRL_TYPE BIT(12)
#define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24)
#define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28)
@@ -337,6 +338,8 @@ struct cxl_dport *cxl_find_dport_by_dev(struct cxl_port *port,
struct device *dev);
struct cxl_decoder *cxl_pop_decoder(struct cxl_port *port);
void cxl_push_decoder(struct cxl_decoder *cxld);
+int cxl_commit_decoder(struct cxl_decoder *cxld);
+void cxl_disable_decoder(struct cxl_decoder *cxld);
struct cxl_decoder *to_cxl_decoder(struct device *dev);
bool is_root_decoder(struct device *dev);
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 5d35ccf2407f..67143c7f59bb 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -99,6 +99,202 @@ struct cxl_port_data {
} caps;
};
+#define COMMIT_TIMEOUT_MS 10
+static int wait_for_commit(struct cxl_decoder *cxld)
+{
+ struct cxl_port *port = to_cxl_port(cxld->dev.parent);
+ const unsigned long start = jiffies;
+ struct cxl_port_data *cpd;
+ void __iomem *hdm_decoder;
+ unsigned long end = start;
+ u32 ctrl;
+
+ cpd = dev_get_drvdata(&port->dev);
+ hdm_decoder = cpd->regs.hdm_decoder;
+
+ do {
+ end = jiffies;
+ ctrl = readl(hdm_decoder +
+ CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id));
+ if (FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl))
+ break;
+
+ if (time_after(end, start + COMMIT_TIMEOUT_MS)) {
+ dev_err(&cxld->dev, "HDM decoder commit timeout %x\n", ctrl);
+ return -ETIMEDOUT;
+ }
+ if ((ctrl & CXL_HDM_DECODER0_CTRL_COMMIT_ERROR) != 0) {
+ dev_err(&cxld->dev, "HDM decoder commit error %x\n", ctrl);
+ return -ENXIO;
+ }
+ } while (!!FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl));
+
+ return 0;
+}
+
+/**
+ * cxl_commit_decoder() - Program a configured cxl_decoder
+ * @cxld: The preconfigured cxl decoder.
+ *
+ * A cxl decoder that is to be committed should have been earmarked as enabled.
+ * This mechanism acts as a soft reservation on the decoder.
+ *
+ * Returns 0 if commit was successful, negative error code otherwise.
+ */
+int cxl_commit_decoder(struct cxl_decoder *cxld)
+{
+ u32 ctrl, tl_lo, tl_hi, base_lo, base_hi, size_lo, size_hi;
+ struct cxl_port *port = to_cxl_port(cxld->dev.parent);
+ struct cxl_port_data *cpd;
+ void __iomem *hdm_decoder;
+ int rc;
+
+ /*
+ * Decoder flags are entirely software controlled and therefore this
+ * case is purely a driver bug.
+ */
+ if (dev_WARN_ONCE(&port->dev, (cxld->flags & CXL_DECODER_F_EN) == 0,
+ "Invalid %s enable state\n", dev_name(&cxld->dev)))
+ return -ENXIO;
+
+ cpd = dev_get_drvdata(&port->dev);
+ hdm_decoder = cpd->regs.hdm_decoder;
+ ctrl = readl(hdm_decoder + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id));
+
+ /*
+ * A decoder that's currently active cannot be changed without the
+ * system being quiesced. While the driver should prevent against this,
+ * for a variety of reasons the hardware might not be in sync with the
+ * hardware and so, do not splat on error.
+ */
+ size_hi = readl(hdm_decoder +
+ CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(cxld->id));
+ size_lo =
+ readl(hdm_decoder + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(cxld->id));
+ if (FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl) &&
+ (size_lo + size_hi)) {
+ dev_err(&port->dev, "Tried to change an active decoder (%s)\n",
+ dev_name(&cxld->dev));
+ return -EBUSY;
+ }
+
+ u32p_replace_bits(&ctrl, 8 - ilog2(cxld->interleave_granularity),
+ CXL_HDM_DECODER0_CTRL_IG_MASK);
+ u32p_replace_bits(&ctrl, ilog2(cxld->interleave_ways),
+ CXL_HDM_DECODER0_CTRL_IW_MASK);
+ u32p_replace_bits(&ctrl, 1, CXL_HDM_DECODER0_CTRL_COMMIT);
+
+ /* TODO: set based on type */
+ u32p_replace_bits(&ctrl, 1, CXL_HDM_DECODER0_CTRL_TYPE);
+
+ base_lo = FIELD_PREP(GENMASK(31, 28),
+ (u32)(cxld->res.start & 0xffffffff));
+ base_hi = FIELD_PREP(~0, (u32)(cxld->res.start >> 32));
+
+ size_lo = (u32)(resource_size(&cxld->res)) & GENMASK(31, 28);
+ size_hi = (u32)((resource_size(&cxld->res) >> 32));
+
+ if (cxld->nr_targets > 0) {
+ tl_lo |= FIELD_PREP(GENMASK(7, 0), cxld->target[0]->port_id);
+ if (cxld->interleave_ways > 1)
+ tl_lo |= FIELD_PREP(GENMASK(15, 8),
+ cxld->target[1]->port_id);
+ if (cxld->interleave_ways > 2)
+ tl_lo |= FIELD_PREP(GENMASK(23, 16),
+ cxld->target[2]->port_id);
+ if (cxld->interleave_ways > 3)
+ tl_lo |= FIELD_PREP(GENMASK(31, 24),
+ cxld->target[3]->port_id);
+ if (cxld->interleave_ways > 4)
+ tl_hi |= FIELD_PREP(GENMASK(7, 0),
+ cxld->target[4]->port_id);
+ if (cxld->interleave_ways > 5)
+ tl_hi |= FIELD_PREP(GENMASK(15, 8),
+ cxld->target[5]->port_id);
+ if (cxld->interleave_ways > 6)
+ tl_hi |= FIELD_PREP(GENMASK(23, 16),
+ cxld->target[6]->port_id);
+ if (cxld->interleave_ways > 7)
+ tl_hi |= FIELD_PREP(GENMASK(31, 24),
+ cxld->target[7]->port_id);
+
+ writel(tl_hi, hdm_decoder + CXL_HDM_DECODER0_TL_HIGH(cxld->id));
+ writel(tl_lo, hdm_decoder + CXL_HDM_DECODER0_TL_LOW(cxld->id));
+ }
+
+ writel(size_hi,
+ hdm_decoder + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(cxld->id));
+ writel(size_lo,
+ hdm_decoder + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(cxld->id));
+ writel(base_hi,
+ hdm_decoder + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(cxld->id));
+ writel(base_lo,
+ hdm_decoder + CXL_HDM_DECODER0_BASE_LOW_OFFSET(cxld->id));
+ writel(ctrl, hdm_decoder + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id));
+
+ rc = wait_for_commit(cxld);
+ if (rc)
+ return rc;
+
+#define DPORT_TL_STR "%d %d %d %d %d %d %d %d"
+#define DPORT(i) \
+ (cxld->nr_targets && cxld->interleave_ways > (i)) ? \
+ cxld->target[(i)]->port_id : \
+ -1
+#define DPORT_TL \
+ DPORT(0), DPORT(1), DPORT(2), DPORT(3), DPORT(4), DPORT(5), DPORT(6), \
+ DPORT(7)
+
+ dev_dbg(&port->dev,
+ "%s\n\tBase %pa\n\tSize %llu\n\tIG %u\n\tIW %u\n\tTargetList: " DPORT_TL_STR,
+ dev_name(&cxld->dev), &cxld->res.start,
+ resource_size(&cxld->res), cxld->interleave_granularity,
+ cxld->interleave_ways, DPORT_TL);
+#undef DPORT_TL
+#undef DPORT
+#undef DPORT_TL_STR
+ return 0;
+}
+EXPORT_SYMBOL_GPL(cxl_commit_decoder);
+
+/**
+ * cxl_disable_decoder() - Disables a decoder
+ * @cxld: The active cxl decoder.
+ *
+ * CXL decoders (as of 2.0 spec) have no way to deactivate them other than to
+ * set the size of the HDM to 0. This function will clear all registers, and if
+ * the decoder is active, commit the 0'd out registers.
+ */
+void cxl_disable_decoder(struct cxl_decoder *cxld)
+{
+ struct cxl_port *port = to_cxl_port(cxld->dev.parent);
+ struct cxl_port_data *cpd;
+ void __iomem *hdm_decoder;
+ u32 ctrl;
+
+ cpd = dev_get_drvdata(&port->dev);
+ hdm_decoder = cpd->regs.hdm_decoder;
+ ctrl = readl(hdm_decoder + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id));
+
+ if (dev_WARN_ONCE(&port->dev, (cxld->flags & CXL_DECODER_F_EN) == 0,
+ "Invalid decoder enable state\n"))
+ return;
+
+ /* There's no way to "uncommit" a committed decoder, only 0 size it */
+ writel(0, hdm_decoder + CXL_HDM_DECODER0_TL_HIGH(cxld->id));
+ writel(0, hdm_decoder + CXL_HDM_DECODER0_TL_LOW(cxld->id));
+ writel(0, hdm_decoder + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(cxld->id));
+ writel(0, hdm_decoder + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(cxld->id));
+ writel(0, hdm_decoder + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(cxld->id));
+ writel(0, hdm_decoder + CXL_HDM_DECODER0_BASE_LOW_OFFSET(cxld->id));
+
+ /* If the device isn't actually active, just zero out all the fields */
+ if (FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl))
+ writel(CXL_HDM_DECODER0_CTRL_COMMIT,
+ hdm_decoder + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id));
+}
+EXPORT_SYMBOL_GPL(cxl_disable_decoder);
+
static inline int cxl_hdm_decoder_ig(u32 ctrl)
{
int val = FIELD_GET(CXL_HDM_DECODER0_CTRL_IG_MASK, ctrl);
diff --git a/drivers/cxl/region.c b/drivers/cxl/region.c
index f4d190ede3ee..05e7ca3d0900 100644
--- a/drivers/cxl/region.c
+++ b/drivers/cxl/region.c
@@ -526,7 +526,38 @@ static int gather_hdm_decoders(const struct cxl_region *region, struct decoder_p
static int bind_region(const struct cxl_region *region)
{
- /* TODO: */
+ const struct decoder_programming *p = ®ion->state;
+ int i, rc;
+
+ for (i = 0; i < p->hb_count; i++) {
+ struct cxl_decoder *cxld = p->hbs[i].cxld;
+ int j;
+
+ cxld->res = (struct resource)DEFINE_RES_MEM(region->res->start,
+ region->size);
+ cxld->interleave_granularity = region->ig;
+ cxld->interleave_ways = p->hbs[i].rp_count;
+ for (j = 0; j < p->hbs[i].rp_count; j++)
+ cxld->target[j] = p->hbs[i].rp_target_list[j];
+
+ rc = cxl_commit_decoder(cxld);
+ if (rc)
+ return rc;
+ }
+
+ for (i = 0; i < region_ways(region); i++) {
+ struct cxl_decoder *cxld = p->ep_cxld[i];
+
+ cxld->res = (struct resource)DEFINE_RES_MEM(region->res->start,
+ region->size);
+ cxld->interleave_granularity = region->ig;
+ cxld->interleave_ways = region_ways(region);
+
+ rc = cxl_commit_decoder(cxld);
+ if (rc)
+ return rc;
+ }
+
return 0;
}
--
2.33.1
prev parent reply other threads:[~2021-10-22 18:37 UTC|newest]
Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-22 18:36 [RFC PATCH v2 00/28] CXL Region Creation / HDM decoder programming Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 01/28] cxl: Rename CXL_MEM to CXL_PCI Ben Widawsky
2021-10-29 20:15 ` Dan Williams
2021-10-29 21:20 ` Ben Widawsky
2021-10-29 21:39 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 02/28] cxl: Move register block enumeration to core Ben Widawsky
2021-10-29 20:23 ` Dan Williams
2021-10-29 21:23 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 03/28] cxl/acpi: Map component registers for Root Ports Ben Widawsky
2021-10-29 20:28 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 04/28] cxl: Add helper for new drivers Ben Widawsky
2021-10-29 20:30 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 05/28] cxl/core: Convert decoder range to resource Ben Widawsky
2021-10-29 20:50 ` Dan Williams
2021-10-29 21:26 ` Ben Widawsky
2021-10-29 22:22 ` Dan Williams
2021-10-29 22:37 ` Ben Widawsky
2021-11-01 14:33 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 06/28] cxl: Introduce endpoint decoders Ben Widawsky
2021-10-29 21:00 ` Dan Williams
2021-10-29 22:02 ` Ben Widawsky
2021-10-29 22:25 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 07/28] cxl/core: Move target population locking to caller Ben Widawsky
2021-10-29 23:03 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 08/28] cxl/port: Introduce a port driver Ben Widawsky
2021-10-30 1:37 ` Dan Williams
2021-10-31 17:53 ` Dan Williams
2021-10-31 18:10 ` Dan Williams
2021-11-01 17:36 ` Ben Widawsky
2021-11-01 17:53 ` Ben Widawsky
2021-11-01 17:54 ` Ben Widawsky
2021-11-02 3:31 ` Dan Williams
2021-11-02 16:27 ` Ben Widawsky
2021-11-02 17:21 ` Dan Williams
2021-11-02 16:58 ` Ben Widawsky
2021-11-04 19:10 ` Dan Williams
2021-11-04 19:49 ` Ben Widawsky
2021-11-04 20:04 ` Dan Williams
2021-11-04 21:25 ` Ben Widawsky
2021-11-04 16:37 ` Ben Widawsky
2021-11-04 19:17 ` Dan Williams
2021-11-04 19:46 ` Ben Widawsky
2021-11-04 20:00 ` Dan Williams
2021-11-04 21:26 ` Ben Widawsky
2021-11-03 15:18 ` Jonathan Cameron
2021-10-22 18:36 ` [RFC PATCH v2 09/28] cxl/acpi: Map single port host bridge component registers Ben Widawsky
2021-10-31 18:03 ` Dan Williams
2021-11-01 17:07 ` Ben Widawsky
2021-11-02 2:15 ` Dan Williams
2021-11-02 16:31 ` Ben Widawsky
2021-11-02 17:46 ` Dan Williams
2021-11-02 17:57 ` Ben Widawsky
2021-11-02 18:10 ` Dan Williams
2021-11-02 18:27 ` Ben Widawsky
2021-11-02 18:49 ` Dan Williams
2021-11-02 21:15 ` Ben Widawsky
2021-11-02 21:34 ` Dan Williams
2021-11-02 21:47 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 10/28] cxl/core: Store global list of root ports Ben Widawsky
2021-10-31 18:32 ` Dan Williams
2021-11-01 18:43 ` Ben Widawsky
2021-11-02 2:04 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 11/28] cxl/acpi: Rescan bus at probe completion Ben Widawsky
2021-10-31 19:25 ` Dan Williams
2021-11-01 18:56 ` Ben Widawsky
2021-11-01 21:45 ` Ben Widawsky
2021-11-02 1:56 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 12/28] cxl/core: Store component register base for memdevs Ben Widawsky
2021-10-31 20:13 ` Dan Williams
2021-11-01 21:50 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 13/28] cxl: Flesh out register names Ben Widawsky
2021-10-31 20:18 ` Dan Williams
2021-11-01 22:00 ` Ben Widawsky
2021-11-02 1:53 ` Dan Williams
2021-11-03 15:53 ` Jonathan Cameron
2021-11-03 16:03 ` Ben Widawsky
2021-11-03 16:42 ` Jonathan Cameron
2021-11-03 17:05 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 14/28] cxl: Hide devm host for ports Ben Widawsky
2021-10-31 21:14 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 15/28] cxl/core: Introduce API to scan switch ports Ben Widawsky
2021-11-01 5:39 ` Dan Williams
2021-11-01 22:56 ` Ben Widawsky
2021-11-02 1:45 ` Dan Williams
2021-11-02 16:39 ` Ben Widawsky
2021-11-02 20:00 ` Dan Williams
2021-11-16 16:50 ` Ben Widawsky
2021-11-16 17:51 ` Dan Williams
2021-11-16 18:02 ` Ben Widawsky
2021-11-03 16:08 ` Jonathan Cameron
2021-11-10 17:49 ` Ben Widawsky
2021-11-10 18:10 ` Jonathan Cameron
2021-11-10 21:03 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 16/28] cxl: Introduce cxl_mem driver Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 17/28] cxl: Disable switch hierarchies for now Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 18/28] cxl/region: Add region creation ABI Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 19/28] cxl/region: Introduce concept of region configuration Ben Widawsky
2021-12-15 17:47 ` Jonathan Cameron
2021-10-22 18:37 ` [RFC PATCH v2 20/28] cxl/region: Introduce a cxl_region driver Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 21/28] cxl/acpi: Handle address space allocation Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 22/28] cxl/region: Address " Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 23/28] cxl/region: Implement XHB verification Ben Widawsky
2022-01-06 16:55 ` Jonathan Cameron
2022-01-06 16:58 ` Ben Widawsky
2022-01-06 17:33 ` Jonathan Cameron
2022-01-06 18:10 ` Jonathan Cameron
2022-01-06 18:34 ` Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 24/28] cxl/region: HB port config verification Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 25/28] cxl/region: Record host bridge target list Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 26/28] cxl/mem: Store the endpoint's uport Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 27/28] cxl/region: Gather HDM decoder resources Ben Widawsky
2021-10-22 18:37 ` Ben Widawsky [this message]
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