From: Ben Widawsky <ben.widawsky@intel.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org,
Chet Douglas <chet.r.douglas@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [RFC PATCH v2 05/28] cxl/core: Convert decoder range to resource
Date: Fri, 29 Oct 2021 14:26:54 -0700 [thread overview]
Message-ID: <20211029212654.cnge45a3tj3abj4s@intel.com> (raw)
In-Reply-To: <CAPcyv4iiR_HT_9ExRvgLixWnQg8y-id1zpmRYurFSfw3OiVaYQ@mail.gmail.com>
On 21-10-29 13:50:29, Dan Williams wrote:
> On Fri, Oct 22, 2021 at 11:37 AM Ben Widawsky <ben.widawsky@intel.com> wrote:
> >
> > Regions will use the resource API in order to help manage allocated
> > space. As regions are children of the decoder, it makes sense that the
> > parent host the main resource to be suballocated by the region.
> >
> > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> > ---
> > drivers/cxl/acpi.c | 12 ++++--------
> > drivers/cxl/core/bus.c | 4 ++--
> > drivers/cxl/cxl.h | 4 ++--
> > 3 files changed, 8 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> > index 7d13e7f0aefc..b972abc9f6ef 100644
> > --- a/drivers/cxl/acpi.c
> > +++ b/drivers/cxl/acpi.c
> > @@ -126,10 +126,9 @@ static void cxl_add_cfmws_decoders(struct device *dev,
> >
> > cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
> > cxld->target_type = CXL_DECODER_EXPANDER;
> > - cxld->range = (struct range) {
> > - .start = cfmws->base_hpa,
> > - .end = cfmws->base_hpa + cfmws->window_size - 1,
> > - };
> > + cxld->res = (struct resource)DEFINE_RES_MEM_NAMED(cfmws->base_hpa,
> > + cfmws->window_size,
> > + "cfmws");
>
> I think this should just be DEFINE_RES_MEM(), and then set the name of
> it inside cxl_decoder_add() to the dev_name() of the decoder device.
> That way a dump of the resource tree hierarchy makes sense compared to
> the device hierarchy with actual device names not a series of
> repeating "cfmws" entries.
>
> > cxld->interleave_ways = CFMWS_INTERLEAVE_WAYS(cfmws);
> > cxld->interleave_granularity =
> > CFMWS_INTERLEAVE_GRANULARITY(cfmws);
> > @@ -339,10 +338,7 @@ static int add_host_bridge_uport(struct device *match, void *arg)
> > cxld->interleave_ways = 1;
> > cxld->interleave_granularity = PAGE_SIZE;
> > cxld->target_type = CXL_DECODER_EXPANDER;
> > - cxld->range = (struct range) {
> > - .start = 0,
> > - .end = -1,
> > - };
> > + cxld->res = (struct resource)DEFINE_RES_MEM(0, 0);
> >
> > device_lock(&port->dev);
> > dport = list_first_entry(&port->dports, typeof(*dport), list);
> > diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
> > index ebd061d03950..454d4d846eb2 100644
> > --- a/drivers/cxl/core/bus.c
> > +++ b/drivers/cxl/core/bus.c
> > @@ -47,7 +47,7 @@ static ssize_t start_show(struct device *dev, struct device_attribute *attr,
> > {
> > struct cxl_decoder *cxld = to_cxl_decoder(dev);
> >
> > - return sysfs_emit(buf, "%#llx\n", cxld->range.start);
> > + return sysfs_emit(buf, "%#llx\n", cxld->res.start);
> > }
> > static DEVICE_ATTR_RO(start);
> >
> > @@ -56,7 +56,7 @@ static ssize_t size_show(struct device *dev, struct device_attribute *attr,
> > {
> > struct cxl_decoder *cxld = to_cxl_decoder(dev);
> >
> > - return sysfs_emit(buf, "%#llx\n", range_len(&cxld->range));
> > + return sysfs_emit(buf, "%#llx\n", resource_size(&cxld->res));
>
> It's not clear to me that anything other than root decoders will host
> a resource tree, every decoder downstream of the root would reference
> a subset of the root decoder range. Something like:
>
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 5e2e93451928..00bf742396e0 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -200,7 +200,8 @@ enum cxl_decoder_type {
> * struct cxl_decoder - CXL address range decode configuration
> * @dev: this decoder's device
> * @id: kernel device name id
> - * @range: address range considered by this decoder
> + * @res: platform address range hosted by a root decoder
> + * @range: address range programmed in the (non-root) decoder
> * @interleave_ways: number of cxl_dports in this decode
> * @interleave_granularity: data stride per dport
> * @target_type: accelerator vs expander (type2 vs type3) selector
> @@ -211,7 +212,10 @@ enum cxl_decoder_type {
> struct cxl_decoder {
> struct device dev;
> int id;
> - struct range range;
> + union {
> + struct resource res;
> + struct range range;
> + };
> int interleave_ways;
> int interleave_granularity;
> enum cxl_decoder_type target_type;
>
> ...because regions will __request_region(&cxld->res, ...) from the
> root decoder, and all the intervening decoders in that stack will be
> updated to make that mapping happen.
>
> Note, this is just how I had it roughly mapped out in my head, I defer
> making it a hard recommendation until I get deeper into this set to
> see if we diverge.
>
You're correct.
I had changed this already for my v3. I ended up with this:
+ union {
+ struct resource cfmws_res;
+ struct resource *decoder_res;
+ };
Not sure if you prefer one way or another.
> > }
> > static DEVICE_ATTR_RO(size);
> >
> > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> > index 4483e1a39fc3..7f2e2bdc7883 100644
> > --- a/drivers/cxl/cxl.h
> > +++ b/drivers/cxl/cxl.h
> > @@ -195,7 +195,7 @@ enum cxl_decoder_type {
> > * struct cxl_decoder - CXL address range decode configuration
> > * @dev: this decoder's device
> > * @id: kernel device name id
> > - * @range: address range considered by this decoder
> > + * @res: address space resources considered by this decoder
> > * @interleave_ways: number of cxl_dports in this decode
> > * @interleave_granularity: data stride per dport
> > * @target_type: accelerator vs expander (type2 vs type3) selector
> > @@ -206,7 +206,7 @@ enum cxl_decoder_type {
> > struct cxl_decoder {
> > struct device dev;
> > int id;
> > - struct range range;
> > + struct resource res;
> > int interleave_ways;
> > int interleave_granularity;
> > enum cxl_decoder_type target_type;
> > --
> > 2.33.1
> >
next prev parent reply other threads:[~2021-10-29 21:26 UTC|newest]
Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-22 18:36 [RFC PATCH v2 00/28] CXL Region Creation / HDM decoder programming Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 01/28] cxl: Rename CXL_MEM to CXL_PCI Ben Widawsky
2021-10-29 20:15 ` Dan Williams
2021-10-29 21:20 ` Ben Widawsky
2021-10-29 21:39 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 02/28] cxl: Move register block enumeration to core Ben Widawsky
2021-10-29 20:23 ` Dan Williams
2021-10-29 21:23 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 03/28] cxl/acpi: Map component registers for Root Ports Ben Widawsky
2021-10-29 20:28 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 04/28] cxl: Add helper for new drivers Ben Widawsky
2021-10-29 20:30 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 05/28] cxl/core: Convert decoder range to resource Ben Widawsky
2021-10-29 20:50 ` Dan Williams
2021-10-29 21:26 ` Ben Widawsky [this message]
2021-10-29 22:22 ` Dan Williams
2021-10-29 22:37 ` Ben Widawsky
2021-11-01 14:33 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 06/28] cxl: Introduce endpoint decoders Ben Widawsky
2021-10-29 21:00 ` Dan Williams
2021-10-29 22:02 ` Ben Widawsky
2021-10-29 22:25 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 07/28] cxl/core: Move target population locking to caller Ben Widawsky
2021-10-29 23:03 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 08/28] cxl/port: Introduce a port driver Ben Widawsky
2021-10-30 1:37 ` Dan Williams
2021-10-31 17:53 ` Dan Williams
2021-10-31 18:10 ` Dan Williams
2021-11-01 17:36 ` Ben Widawsky
2021-11-01 17:53 ` Ben Widawsky
2021-11-01 17:54 ` Ben Widawsky
2021-11-02 3:31 ` Dan Williams
2021-11-02 16:27 ` Ben Widawsky
2021-11-02 17:21 ` Dan Williams
2021-11-02 16:58 ` Ben Widawsky
2021-11-04 19:10 ` Dan Williams
2021-11-04 19:49 ` Ben Widawsky
2021-11-04 20:04 ` Dan Williams
2021-11-04 21:25 ` Ben Widawsky
2021-11-04 16:37 ` Ben Widawsky
2021-11-04 19:17 ` Dan Williams
2021-11-04 19:46 ` Ben Widawsky
2021-11-04 20:00 ` Dan Williams
2021-11-04 21:26 ` Ben Widawsky
2021-11-03 15:18 ` Jonathan Cameron
2021-10-22 18:36 ` [RFC PATCH v2 09/28] cxl/acpi: Map single port host bridge component registers Ben Widawsky
2021-10-31 18:03 ` Dan Williams
2021-11-01 17:07 ` Ben Widawsky
2021-11-02 2:15 ` Dan Williams
2021-11-02 16:31 ` Ben Widawsky
2021-11-02 17:46 ` Dan Williams
2021-11-02 17:57 ` Ben Widawsky
2021-11-02 18:10 ` Dan Williams
2021-11-02 18:27 ` Ben Widawsky
2021-11-02 18:49 ` Dan Williams
2021-11-02 21:15 ` Ben Widawsky
2021-11-02 21:34 ` Dan Williams
2021-11-02 21:47 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 10/28] cxl/core: Store global list of root ports Ben Widawsky
2021-10-31 18:32 ` Dan Williams
2021-11-01 18:43 ` Ben Widawsky
2021-11-02 2:04 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 11/28] cxl/acpi: Rescan bus at probe completion Ben Widawsky
2021-10-31 19:25 ` Dan Williams
2021-11-01 18:56 ` Ben Widawsky
2021-11-01 21:45 ` Ben Widawsky
2021-11-02 1:56 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 12/28] cxl/core: Store component register base for memdevs Ben Widawsky
2021-10-31 20:13 ` Dan Williams
2021-11-01 21:50 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 13/28] cxl: Flesh out register names Ben Widawsky
2021-10-31 20:18 ` Dan Williams
2021-11-01 22:00 ` Ben Widawsky
2021-11-02 1:53 ` Dan Williams
2021-11-03 15:53 ` Jonathan Cameron
2021-11-03 16:03 ` Ben Widawsky
2021-11-03 16:42 ` Jonathan Cameron
2021-11-03 17:05 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 14/28] cxl: Hide devm host for ports Ben Widawsky
2021-10-31 21:14 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 15/28] cxl/core: Introduce API to scan switch ports Ben Widawsky
2021-11-01 5:39 ` Dan Williams
2021-11-01 22:56 ` Ben Widawsky
2021-11-02 1:45 ` Dan Williams
2021-11-02 16:39 ` Ben Widawsky
2021-11-02 20:00 ` Dan Williams
2021-11-16 16:50 ` Ben Widawsky
2021-11-16 17:51 ` Dan Williams
2021-11-16 18:02 ` Ben Widawsky
2021-11-03 16:08 ` Jonathan Cameron
2021-11-10 17:49 ` Ben Widawsky
2021-11-10 18:10 ` Jonathan Cameron
2021-11-10 21:03 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 16/28] cxl: Introduce cxl_mem driver Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 17/28] cxl: Disable switch hierarchies for now Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 18/28] cxl/region: Add region creation ABI Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 19/28] cxl/region: Introduce concept of region configuration Ben Widawsky
2021-12-15 17:47 ` Jonathan Cameron
2021-10-22 18:37 ` [RFC PATCH v2 20/28] cxl/region: Introduce a cxl_region driver Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 21/28] cxl/acpi: Handle address space allocation Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 22/28] cxl/region: Address " Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 23/28] cxl/region: Implement XHB verification Ben Widawsky
2022-01-06 16:55 ` Jonathan Cameron
2022-01-06 16:58 ` Ben Widawsky
2022-01-06 17:33 ` Jonathan Cameron
2022-01-06 18:10 ` Jonathan Cameron
2022-01-06 18:34 ` Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 24/28] cxl/region: HB port config verification Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 25/28] cxl/region: Record host bridge target list Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 26/28] cxl/mem: Store the endpoint's uport Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 27/28] cxl/region: Gather HDM decoder resources Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 28/28] cxl: Program decoders for regions Ben Widawsky
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