From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, Ben Widawsky <bwidawsk@kernel.org>,
<hch@lst.de>, <nvdimm@lists.linux.dev>,
<linux-pci@vger.kernel.org>
Subject: Re: [PATCH v2 06/28] cxl/hdm: Enumerate allocated DPA
Date: Wed, 20 Jul 2022 17:40:31 +0100 [thread overview]
Message-ID: <20220720174031.00006f78@Huawei.com> (raw)
In-Reply-To: <165784327682.1758207.7914919426043855876.stgit@dwillia2-xfh.jf.intel.com>
On Thu, 14 Jul 2022 17:01:16 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> In preparation for provisioning CXL regions, add accounting for the DPA
> space consumed by existing regions / decoders. Recall, a CXL region is a
> memory range comprised from one or more endpoint devices contributing a
> mapping of their DPA into HPA space through a decoder.
>
> Record the DPA ranges covered by committed decoders at initial probe of
> endpoint ports relative to a per-device resource tree of the DPA type
> (pmem or volatile-ram).
>
> The cxl_dpa_rwsem semaphore is introduced to globally synchronize DPA
> state across all endpoints and their decoders at once. The vast majority
> of DPA operations are reads as region creation is expected to be as rare
> as disk partitioning and volume creation. The device_lock() for this
> synchronization is specifically avoided for concern of entangling with
> sysfs attribute removal.
>
> Co-developed-by: Ben Widawsky <bwidawsk@kernel.org>
> Signed-off-by: Ben Widawsky <bwidawsk@kernel.org>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
One trivial ordering question inline. I'm not that bothered whether you
do anything about it though as it's all very local.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/hdm.c | 143 ++++++++++++++++++++++++++++++++++++++++++++----
> drivers/cxl/cxl.h | 2 +
> drivers/cxl/cxlmem.h | 13 ++++
> 3 files changed, 147 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 650363d5272f..d4c17325001b 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -153,10 +153,105 @@ void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds)
> }
> EXPORT_SYMBOL_NS_GPL(cxl_dpa_debug, CXL);
>
> +/*
> + * Must be called in a context that synchronizes against this decoder's
> + * port ->remove() callback (like an endpoint decoder sysfs attribute)
> + */
> +static void __cxl_dpa_release(struct cxl_endpoint_decoder *cxled)
> +{
> + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> + struct resource *res = cxled->dpa_res;
> +
> + lockdep_assert_held_write(&cxl_dpa_rwsem);
> +
> + if (cxled->skip)
> + __release_region(&cxlds->dpa_res, res->start - cxled->skip,
> + cxled->skip);
> + cxled->skip = 0;
> + __release_region(&cxlds->dpa_res, res->start, resource_size(res));
Minor but I think the ordering in here is unnecessarily not the opposite
of what is going on in __cxl_dpa_reserve() Should be releasing the
actual rs first, then releasing the skip.
> + cxled->dpa_res = NULL;
> +}
> +
> +static void cxl_dpa_release(void *cxled)
> +{
> + down_write(&cxl_dpa_rwsem);
> + __cxl_dpa_release(cxled);
> + up_write(&cxl_dpa_rwsem);
> +}
> +
> +static int __cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
> + resource_size_t base, resource_size_t len,
> + resource_size_t skipped)
> +{
> + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> + struct cxl_port *port = cxled_to_port(cxled);
> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> + struct device *dev = &port->dev;
> + struct resource *res;
> +
> + lockdep_assert_held_write(&cxl_dpa_rwsem);
> +
> + if (!len)
> + return 0;
> +
> + if (cxled->dpa_res) {
> + dev_dbg(dev, "decoder%d.%d: existing allocation %pr assigned\n",
> + port->id, cxled->cxld.id, cxled->dpa_res);
> + return -EBUSY;
> + }
> +
> + if (skipped) {
> + res = __request_region(&cxlds->dpa_res, base - skipped, skipped,
> + dev_name(&cxled->cxld.dev), 0);
> + if (!res) {
> + dev_dbg(dev,
> + "decoder%d.%d: failed to reserve skipped space\n",
> + port->id, cxled->cxld.id);
> + return -EBUSY;
> + }
> + }
> + res = __request_region(&cxlds->dpa_res, base, len,
> + dev_name(&cxled->cxld.dev), 0);
> + if (!res) {
> + dev_dbg(dev, "decoder%d.%d: failed to reserve allocation\n",
> + port->id, cxled->cxld.id);
> + if (skipped)
> + __release_region(&cxlds->dpa_res, base - skipped,
> + skipped);
> + return -EBUSY;
> + }
> + cxled->dpa_res = res;
> + cxled->skip = skipped;
> +
> + return 0;
> +}
> +
...
next prev parent reply other threads:[~2022-07-20 16:40 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-15 0:00 [PATCH v2 00/28] CXL PMEM Region Provisioning Dan Williams
2022-07-15 0:00 ` [PATCH v2 01/28] Documentation/cxl: Use a double line break between entries Dan Williams
2022-07-20 13:26 ` Jonathan Cameron
2022-07-15 0:00 ` [PATCH v2 02/28] cxl/core: Define a 'struct cxl_switch_decoder' Dan Williams
2022-07-20 15:39 ` Jonathan Cameron
2022-07-15 0:00 ` [PATCH v2 03/28] cxl/acpi: Track CXL resources in iomem_resource Dan Williams
2022-07-15 5:23 ` Greg Kroah-Hartman
2022-07-20 16:03 ` Jonathan Cameron
2022-07-15 0:01 ` [PATCH v2 04/28] cxl/core: Define a 'struct cxl_root_decoder' Dan Williams
2022-07-20 16:07 ` Jonathan Cameron
2022-07-15 0:01 ` [PATCH v2 05/28] cxl/core: Define a 'struct cxl_endpoint_decoder' Dan Williams
2022-07-20 16:11 ` Jonathan Cameron
2022-07-15 0:01 ` [PATCH v2 06/28] cxl/hdm: Enumerate allocated DPA Dan Williams
2022-07-20 16:40 ` Jonathan Cameron [this message]
2022-07-21 15:29 ` Dan Williams
2022-07-15 0:01 ` [PATCH v2 07/28] cxl/hdm: Add 'mode' attribute to decoder objects Dan Williams
2022-07-15 0:01 ` [PATCH v2 08/28] cxl/hdm: Track next decoder to allocate Dan Williams
2022-07-20 16:45 ` Jonathan Cameron
2022-07-15 0:01 ` [PATCH v2 09/28] cxl/hdm: Add support for allocating DPA to an endpoint decoder Dan Williams
2022-07-20 16:51 ` Jonathan Cameron
2022-07-15 0:01 ` [PATCH v2 10/28] cxl/port: Record dport in endpoint references Dan Williams
2022-07-20 16:53 ` Jonathan Cameron
2022-07-15 0:01 ` [PATCH v2 11/28] cxl/port: Record parent dport when adding ports Dan Williams
2022-07-15 0:01 ` [PATCH v2 12/28] cxl/port: Move 'cxl_ep' references to an xarray per port Dan Williams
2022-07-15 0:01 ` [PATCH v2 13/28] cxl/port: Move dport tracking to an xarray Dan Williams
2022-07-20 16:56 ` Jonathan Cameron
2022-07-15 0:02 ` [PATCH v2 14/28] cxl/hdm: Add sysfs attributes for interleave ways + granularity Dan Williams
2022-07-20 16:58 ` Jonathan Cameron
2022-07-15 0:02 ` [PATCH v2 15/28] cxl/mem: Enumerate port targets before adding endpoints Dan Williams
2022-07-15 0:02 ` [PATCH v2 16/28] resource: Introduce alloc_free_mem_region() Dan Williams
2022-07-20 17:00 ` Jonathan Cameron
2022-07-21 16:10 ` Dan Williams
2022-09-06 13:25 ` Rogerio Alves
2022-07-15 0:02 ` [PATCH v2 17/28] cxl/region: Add region creation support Dan Williams
2022-07-20 17:16 ` Jonathan Cameron
2022-07-15 0:02 ` [PATCH v2 18/28] cxl/region: Add a 'uuid' attribute Dan Williams
2022-07-20 17:18 ` Jonathan Cameron
2022-07-15 0:02 ` [PATCH v2 19/28] cxl/region: Add interleave geometry attributes Dan Williams
2022-07-15 0:02 ` [PATCH v2 20/28] cxl/region: Allocate HPA capacity to regions Dan Williams
2022-07-20 17:20 ` Jonathan Cameron
2022-07-15 0:02 ` [PATCH v2 21/28] cxl/region: Enable the assignment of endpoint decoders " Dan Williams
2022-07-20 17:26 ` Jonathan Cameron
2022-07-20 19:05 ` Dan Williams
2022-07-15 0:02 ` [PATCH v2 22/28] cxl/acpi: Add a host-bridge index lookup mechanism Dan Williams
2022-07-15 0:02 ` [PATCH v2 23/28] cxl/region: Attach endpoint decoders Dan Williams
2022-07-20 17:29 ` Jonathan Cameron
2022-07-15 0:02 ` [PATCH v2 24/28] cxl/region: Program target lists Dan Williams
2022-07-20 17:41 ` Jonathan Cameron
2022-07-21 16:56 ` Dan Williams
2022-07-15 0:03 ` [PATCH v2 25/28] cxl/hdm: Commit decoder state to hardware Dan Williams
2022-07-20 17:44 ` Jonathan Cameron
2022-07-15 0:03 ` [PATCH v2 26/28] cxl/region: Add region driver boiler plate Dan Williams
2022-07-15 0:03 ` [PATCH v2 27/28] cxl/pmem: Fix offline_nvdimm_bus() to offline by bridge Dan Williams
2022-07-20 17:46 ` Jonathan Cameron
2022-07-15 0:03 ` [PATCH v2 28/28] cxl/region: Introduce cxl_pmem_region objects Dan Williams
2022-07-20 18:05 ` Jonathan Cameron
2022-07-20 18:12 ` [PATCH v2 00/28] CXL PMEM Region Provisioning Jonathan Cameron
2022-07-21 18:34 ` Dan Williams
2022-07-21 14:59 ` Jonathan Cameron
2022-07-21 16:29 ` Dan Williams
2022-07-21 17:22 ` Jonathan Cameron
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