From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <ira.weiny@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
"Ben Widawsky" <bwidawsk@kernel.org>, <linux-cxl@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>
Subject: Re: [PATCH V3 2/2] cxl/doe: Request exclusive DOE access
Date: Tue, 27 Sep 2022 14:58:36 +0100 [thread overview]
Message-ID: <20220927145836.0000572e@huawei.com> (raw)
In-Reply-To: <20220926215711.2893286-3-ira.weiny@intel.com>
On Mon, 26 Sep 2022 14:57:11 -0700
ira.weiny@intel.com wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> The PCIE Data Object Exchange (DOE) mailbox is a protocol run over
> configuration cycles. It assumes one initiator at a time. While the
> kernel has control of the mailbox user space writes could interfere with
> the kernel access.
>
> Mark DOE mailbox config space exclusive when iterated by the CXL driver.
>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
I wonder a bit on whether the failure should be fatal given that something
very odd would be required for it to fail.
I'm not that bothered though.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ---
> Changes from V2:
> Jonathan:
> s/PCI_DOE_CAP_SIZE/PCI_DOE_CAP_SIZEOF
> Set PCI_DOE_CAP_SIZEOF directly
> ---
> drivers/cxl/pci.c | 5 +++++
> include/uapi/linux/pci_regs.h | 1 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index faeb5d9d7a7a..621a0522b554 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -418,6 +418,11 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds)
> continue;
> }
>
> + if (!pci_request_config_region_exclusive(pdev, off,
> + PCI_DOE_CAP_SIZEOF,
> + dev_name(dev)))
> + pci_err(pdev, "Failed to exclude DOE registers\n");
> +
> if (xa_insert(&cxlds->doe_mbs, off, doe_mb, GFP_KERNEL)) {
> dev_err(dev, "xa_insert failed to insert MB @ %x\n",
> off);
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 57b8e2ffb1dd..82a03ea954af 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -1119,6 +1119,7 @@
> #define PCI_DOE_STATUS_DATA_OBJECT_READY 0x80000000 /* Data Object Ready */
> #define PCI_DOE_WRITE 0x10 /* DOE Write Data Mailbox Register */
> #define PCI_DOE_READ 0x14 /* DOE Read Data Mailbox Register */
> +#define PCI_DOE_CAP_SIZEOF 0x18 /* Size of DOE register block */
>
> /* DOE Data Object - note not actually registers */
> #define PCI_DOE_DATA_OBJECT_HEADER_1_VID 0x0000ffff
next prev parent reply other threads:[~2022-09-27 13:59 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-26 21:57 [PATCH V3 0/2] CXL: Taint user access to DOE mailbox config space ira.weiny
2022-09-26 21:57 ` [PATCH V3 1/2] PCI: Allow drivers to request exclusive config regions ira.weiny
2022-09-27 7:27 ` Greg Kroah-Hartman
2022-09-27 18:51 ` Bjorn Helgaas
2022-09-26 21:57 ` [PATCH V3 2/2] cxl/doe: Request exclusive DOE access ira.weiny
2022-09-27 13:58 ` Jonathan Cameron [this message]
2022-10-21 23:29 ` [PATCH V3 0/2] CXL: Taint user access to DOE mailbox config space Dan Williams
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