Re: [RFC PATCH v2 2/4] cxl/pci: Find and register CXL PMU devices

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Thu, 1 Sep 2022 15:36:23 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> On 8/24/2022 3:36 AM, Jonathan Cameron wrote:
> > CXL PMU devices can be found from entries in the Register
> > Locator DVSEC.
> >
> > In order to register the minimum number of IRQ vectors necessary
> > to support all CPMUs found, separate the registration into two
> > steps.  First find the devices, and query the IRQs used and then
> > register the devices. Between these two steps, request the
> > IRQ vectors necessary and enable bus master support.
> >
> > Future IRQ users for CXL type 3 devices (e.g. DOEs) will need to
> > follow a similar pattern the number of vectors necessary is known
> > before any parts of the driver stack rely on their availability.
> >
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> >


> > +static int cxl_alloc_irq_vectors(struct cxl_dev_state *cxlds, int vectors)
> > +{
> > +	struct device *dev = cxlds->dev;
> > +	struct pci_dev *pdev = to_pci_dev(dev);
> > +	int rc;
> > +
> > +	rc = pci_alloc_irq_vectors(pdev, vectors, vectors,
> > +				   PCI_IRQ_MSI | PCI_IRQ_MSIX);
> > +	if (rc < 0)
> > +		return rc;
> > +	if (rc != vectors) {  
> 
> I don't think you'll hit here since you passed in vectors for min and 
> max. You'll get -ENOSPC and return from the earlier check.
> 
> https://elixir.bootlin.com/linux/v6.0-rc3/source/drivers/pci/msi/msi.c#L1005
> 
> DJ
> 

Good point.  This also applies to the version of the same function in
Davidlohr's patch set, so I've cut and paste your comment to there.

Jonathan