From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Liang Kan <kan.liang@linux.intel.com>,
<linux-cxl@vger.kernel.org>, <peterz@infradead.org>,
<mingo@redhat.com>, <acme@kernel.org>, <mark.rutland@arm.com>,
<will@kernel.org>, <linuxarm@huawei.com>,
<linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Davidlohr Bueso <dave@stgolabs.net>,
Dave Jiang <dave.jiang@intel.com>
Subject: Re: [PATCH v4 3/5] cxl/pci: Find and register CXL PMU devices
Date: Wed, 5 Apr 2023 11:48:05 +0100 [thread overview]
Message-ID: <20230405114805.000014ef@Huawei.com> (raw)
In-Reply-To: <642c77ad5f0d_21a8294fe@dwillia2-xfh.jf.intel.com.notmuch>
On Tue, 4 Apr 2023 12:17:01 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> Jonathan Cameron wrote:
> > CXL PMU devices can be found from entries in the Register
> > Locator DVSEC.
> >
> > In order to register the minimum number of IRQ vectors necessary
> > to support all CPMUs found, separate the registration into two
> > steps. First find the devices, and query the IRQs used and then
> > register the devices. Between these two steps, request the
> > IRQ vectors necessary and enable bus master support.
>
> It's not clear why this patch is talking about irq vectors and bus
> mastering when there is no irq query/setup logic in this patch?
>
> > Future IRQ users for CXL type 3 devices (e.g. DOEs) will need to
> > follow a similar pattern the number of vectors necessary is known
> > before any parts of the driver stack rely on their availability.
>
> With the new pci_msix_alloc_irq_at() it's not clear that this 2 step
> approach is required, right?
Stale description. Will drop all that garbage.
>
> > Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
> > v4:
> > - No change.
> > ---
> > drivers/cxl/core/Makefile | 1 +
> > drivers/cxl/core/core.h | 1 +
> > drivers/cxl/core/cpmu.c | 72 +++++++++++++++++++++++++++++++++++++++
>
> A quibble with the naming, I prefer:
>
> drivers/cxl/core/pmu.c
>
> ...since "cxl" is in the directory path. Also, usages of cpmu
> already have a cxl in their symbol names, so just s/cpmu/pmu/ throught.
> The usage of CPMU_ for register macros would seem be more clear, or at
> least more consistent, as CXL_PMU_ like the other register offset
> definitions in cxlpci.h.
Makes sense. I'll leave the register defs as
CPMU_XXX to keep them compact but use the pmu naming for pretty much everything else.
>
> > drivers/cxl/core/port.c | 2 ++
> > drivers/cxl/core/regs.c | 16 +++++++++
> > drivers/cxl/cpmu.h | 56 ++++++++++++++++++++++++++++++
>
> drivers/cxl/pmu.h
>
> > drivers/cxl/cxl.h | 14 ++++++++
> > drivers/cxl/cxlpci.h | 1 +
> > drivers/cxl/pci.c | 25 +++++++++++++-
> > 9 files changed, 187 insertions(+), 1 deletion(-)
>
> Other than those minor issues above, this looks good to me, with those
> fixed up.
>
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Thanks,
next prev parent reply other threads:[~2023-04-05 10:48 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 16:45 [PATCH v4 0/5] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
2023-03-30 16:45 ` [PATCH v4 1/5] cxl: Add function to count regblocks of a given type Jonathan Cameron
2023-04-04 3:59 ` Dan Williams
2023-03-30 16:45 ` [PATCH v4 2/5] perf: Allow a PMU to have a parent Jonathan Cameron
2023-04-04 4:03 ` Dan Williams
2023-03-30 16:45 ` [PATCH v4 3/5] cxl/pci: Find and register CXL PMU devices Jonathan Cameron
2023-04-04 19:17 ` Dan Williams
2023-04-05 10:48 ` Jonathan Cameron [this message]
2023-03-30 16:45 ` [PATCH v4 4/5] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
2023-04-03 17:32 ` Liang, Kan
2023-04-04 16:48 ` Jonathan Cameron
2023-04-04 21:53 ` Dan Williams
2023-04-05 16:08 ` Jonathan Cameron
2023-04-05 19:26 ` Dan Williams
2023-03-30 16:45 ` [PATCH v4 5/5] docs: perf: Minimal introduction the the CXL PMU device and driver Jonathan Cameron
2023-04-03 17:45 ` Liang, Kan
2023-04-04 16:55 ` Jonathan Cameron
2023-04-04 22:24 ` Dan Williams
2023-04-06 16:33 ` Jonathan Cameron
2023-04-04 3:55 ` [PATCH v4 0/5] CXL 3.0 Performance Monitoring Unit support Dan Williams
2023-04-11 13:21 ` Jonathan Cameron
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