* [ACPICA PATCH] Add CXL 3.0 structures (CXIMS & RDPAS) to the CEDT table
@ 2022-09-16 23:21 alison.schofield
2022-09-16 23:35 ` Dan Williams
0 siblings, 1 reply; 2+ messages in thread
From: alison.schofield @ 2022-09-16 23:21 UTC (permalink / raw)
To: Robert Moore, Dan Williams, Ira Weiny, Vishal Verma,
Ben Widawsky, Dave Jiang
Cc: Alison Schofield, linux-cxl
From: Alison Schofield <alison.schofield@intel.com>
Prologue: The CXIMS addition to ACPICA was reverted, so, while I was
at it, decided to collect both CEDT changes in one patch for ACPICA.
Please review here, or on ACPICA github:
https://github.com/acpica/acpica/pull/795
Thanks,
Alison
The CXL 3.0 Specification[1] adds two new structures to
the CXL Early Discovery Table (CEDT). The CEDT may include
zero or more entries of these types:
CXIMS: CXL XOR Interleave Math Structure
Enables the host to find a targets position in an
Interleave Target List when XOR Math is used.
RDPAS: RCEC Downstream Post Association Structure
Enables the host to locate the Downstream Port(s)
that report errors to a given Root Complex Event
Collector (RCEC).
[1]https://www.computeexpresslink.org/spec-landing
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
---
source/include/actbl1.h | 34 +++++++++++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/source/include/actbl1.h b/source/include/actbl1.h
index 3de78b0d8f01..6041e8f4c289 100644
--- a/source/include/actbl1.h
+++ b/source/include/actbl1.h
@@ -525,7 +525,9 @@ enum AcpiCedtType
{
ACPI_CEDT_TYPE_CHBS = 0,
ACPI_CEDT_TYPE_CFMWS = 1,
- ACPI_CEDT_TYPE_RESERVED = 2,
+ ACPI_CEDT_TYPE_CXIMS = 2,
+ ACPI_CEDT_TYPE_RDPAS = 3,
+ ACPI_CEDT_TYPE_RESERVED = 4,
};
/* Values for version field above */
@@ -583,6 +585,7 @@ typedef struct acpi_cedt_cfmws_target_element
/* Values for Interleave Arithmetic field above */
#define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0)
+#define ACPI_CEDT_CFMWS_ARITHMETIC_XOR (1)
/* Values for Restrictions field above */
@@ -592,6 +595,35 @@ typedef struct acpi_cedt_cfmws_target_element
#define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3)
#define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4)
+/* 2: CXL XOR Interleave Math Structure */
+
+struct acpi_cedt_cxims {
+ ACPI_CEDT_HEADER Header;
+ UINT16 Reserved1;
+ UINT8 Hbig;
+ UINT8 NrXormaps;
+ UINT64 XormapList[];
+};
+
+/* 3: CXL RCEC Downstream Port Association Structure */
+
+struct acpi_cedt_rdpas {
+ ACPI_CEDT_HEADER Header;
+ UINT8 Reserved1;
+ UINT16 Length;
+ UINT16 Segment;
+ UINT16 Bdf;
+ UINT8 Protocol;
+ UINT64 Address;
+};
+
+/* Masks for bdf field above */
+#define ACPI_CEDT_RDPAS_BUS_MASK 0xff00
+#define ACPI_CEDT_RDPAS_DEVICE_MASK 0x00f8
+#define ACPI_CEDT_RDPAS_FUNCTION_MASK 0x0007
+
+#define ACPI_CEDT_RDPAS_PROTOCOL_IO (0)
+#define ACPI_CEDT_RDPAS_PROTOCOL_CACHEMEM (1)
/*******************************************************************************
*
--
2.31.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* RE: [ACPICA PATCH] Add CXL 3.0 structures (CXIMS & RDPAS) to the CEDT table
2022-09-16 23:21 [ACPICA PATCH] Add CXL 3.0 structures (CXIMS & RDPAS) to the CEDT table alison.schofield
@ 2022-09-16 23:35 ` Dan Williams
0 siblings, 0 replies; 2+ messages in thread
From: Dan Williams @ 2022-09-16 23:35 UTC (permalink / raw)
To: alison.schofield, Robert Moore, Dan Williams, Ira Weiny,
Vishal Verma, Ben Widawsky, Dave Jiang
Cc: Alison Schofield, linux-cxl
alison.schofield@ wrote:
> From: Alison Schofield <alison.schofield@intel.com>
>
> Prologue: The CXIMS addition to ACPICA was reverted, so, while I was
> at it, decided to collect both CEDT changes in one patch for ACPICA.
> Please review here, or on ACPICA github:
> https://github.com/acpica/acpica/pull/795
> Thanks,
> Alison
>
>
> The CXL 3.0 Specification[1] adds two new structures to
> the CXL Early Discovery Table (CEDT). The CEDT may include
> zero or more entries of these types:
>
> CXIMS: CXL XOR Interleave Math Structure
> Enables the host to find a targets position in an
> Interleave Target List when XOR Math is used.
>
> RDPAS: RCEC Downstream Post Association Structure
> Enables the host to locate the Downstream Port(s)
> that report errors to a given Root Complex Event
> Collector (RCEC).
>
> [1]https://www.computeexpresslink.org/spec-landing
>
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> ---
> source/include/actbl1.h | 34 +++++++++++++++++++++++++++++++++-
> 1 file changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/source/include/actbl1.h b/source/include/actbl1.h
> index 3de78b0d8f01..6041e8f4c289 100644
> --- a/source/include/actbl1.h
> +++ b/source/include/actbl1.h
> @@ -525,7 +525,9 @@ enum AcpiCedtType
> {
> ACPI_CEDT_TYPE_CHBS = 0,
> ACPI_CEDT_TYPE_CFMWS = 1,
> - ACPI_CEDT_TYPE_RESERVED = 2,
> + ACPI_CEDT_TYPE_CXIMS = 2,
> + ACPI_CEDT_TYPE_RDPAS = 3,
> + ACPI_CEDT_TYPE_RESERVED = 4,
> };
>
> /* Values for version field above */
> @@ -583,6 +585,7 @@ typedef struct acpi_cedt_cfmws_target_element
> /* Values for Interleave Arithmetic field above */
>
> #define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0)
> +#define ACPI_CEDT_CFMWS_ARITHMETIC_XOR (1)
>
> /* Values for Restrictions field above */
>
> @@ -592,6 +595,35 @@ typedef struct acpi_cedt_cfmws_target_element
> #define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3)
> #define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4)
>
> +/* 2: CXL XOR Interleave Math Structure */
> +
> +struct acpi_cedt_cxims {
> + ACPI_CEDT_HEADER Header;
> + UINT16 Reserved1;
> + UINT8 Hbig;
> + UINT8 NrXormaps;
> + UINT64 XormapList[];
This might be the source of the build trouble. I thought ACPICA builds
in constrained environments with simple compilers that do not support
variable-length arrays.
For example:
typedef struct acpi_table_slit
{
ACPI_TABLE_HEADER Header; /* Common ACPI table header */
UINT64 LocalityCount;
UINT8 Entry[1]; /* Real size = localities^2 */
} ACPI_TABLE_SLIT;
https://github.com/acpica/acpica/blob/master/source/include/actbl3.h#L234
However, if this is the breakage then I don't understand why:
typedef struct acpi_cedt_cfmws
{
ACPI_CEDT_HEADER Header;
UINT32 Reserved1;
UINT64 BaseHpa;
UINT64 WindowSize;
UINT8 InterleaveWays;
UINT8 InterleaveArithmetic;
UINT16 Reserved2;
UINT32 Granularity;
UINT16 Restrictions;
UINT16 QtgId;
UINT32 InterleaveTargets[];
} ACPI_CEDT_CFMWS;
https://github.com/acpica/acpica/blob/master/source/include/actbl1.h#L561
Gets by without complaint?
Otherwise that's all I can see as the reason why the first attempt
reported build issues.
Bob, is there a place where someone can reproduce the ACPICA build
environment to check these issues themselves going forward?
^ permalink raw reply [flat|nested] 2+ messages in thread
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