Re: [PATCH] cxl: Add post reset warning if the reset is detected as Secondary Bus Reset (SBR)

[Dan Williams <dan.j.williams@intel.com>]

Bjorn Helgaas wrote:
> [+cc Alex, reset expert]
> 
> On Mon, Feb 19, 2024 at 02:20:06PM +0000, Jonathan Cameron wrote:
> > On Thu, 15 Feb 2024 16:23:07 -0700
> > Dave Jiang <dave.jiang@intel.com> wrote:
> > 
> > > SBR is equivalent to a device been hot removed and inserted again. Doing a
> > > SBR on a CXL type 3 device is problematic if the exported device memory is
> > > part of system memory that cannot be offlined. The event is equivalent to
> > > violently ripping out that range of memory from the kernel. While the
> > > hardware requires the "Unmask SBR" bit set in the Port Control Extensions
> > > register and the kernel currently does not unmask it, user can unmask
> > > this bit via setpci or similar tool.
> 
> IIUC, this refers to CXL r3.1, sec 8.1.5.2, which says the default
> "Unmask SBR" value is 0, and that when it is 0, the SBR bit in Bridge
> Control has no effect unless the Port is operating in PCIe or RCD
> mode.
> 
> So I guess the scenario is a CXL Port leading to a CXL type 3 device,
> and if the Port has the default "Unmask SBR" of 0, an attempt to reset
> the type 3 device via SBR would have no effect.  But if a user or some
> future kernel *sets* "Unmask SBR", the type 3 device could see a hot
> reset.
> 
> It sounds kind of problematic that when "Unmask SBR" is 0, an attempt
> to reset downstream devices using SBR would fail but the caller of
> pci_reset_function() would think it succeeded.
> 
> > > The driver does not have a way to detect whether a reset coming from the
> > > PCI subsystem is a Function Level Reset (FLR) or SBR. The only way to
> > > detect is to note if there are active decoders before the reset and check
> > > if the range register memory active bit remains set after reset.
> > > 
> > > A helper function to check is added to detect if the range register memory
> > > active bit is set. A locked helper for cxl_num_decoders_committed() is also
> > > added to allow pci code to call the cxl_num_decoders_committed() while
> > > holding the cxl_region_rwsem.
> > > 
> > > Add a err_handler->reset_prepare() to detect whether there are active
> > > decoders.  Add a err_handler->reset_done() to check if there was active
> > > memory before the reset and it is no longer active after the reset. A
> > > warning is emitted in the case of active memory has been offlined.
> > > 
> > > Suggested-by: Dan Williams <dan.j.williams@intel.com>
> > > Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> > 
> > This feels like we are papering over a hole in the PCI core.
> > Is there no way of detecting Secondary Bus Reset (SBR) and
> > communicate that down to the device?
> > +CC Bjorn. 
> > Most of the logic would be needed in driver anyway though as
> > we don't want to bother warning on SBR if there was no memory mapped.
> > 
> > Bjorn, would you prefer this FLR vs SBR being detected by state
> > change in driver, or a modification to the PCI core so that it
> > provides this info to the drivers?
> 
> I guess this is about pci_reset_function() and similar paths, which
> call .reset_prepare() in pci_dev_save_and_disable() before the reset
> and call .reset_done() afterwards, and the question is whether we
> should pass a new parameter to .reset_done() to tell the driver what
> type of reset was done?
> 
> That seems *possible*, but kind of a hassle because there are several
> different reset methods (six in pci_reset_fn_methods[] plus
> device-specific things in pci_dev_reset_methods[] and a few more in
> various hotplug_slot_ops structs), and I guess we'd have to plumb them
> all to return some indication of what kind of reset they used.
> 
> But even before we get that far, if pci_reset_function() just does
> nothing on these devices because SBRs are masked by default, that
> sounds like it needs to be fixed first.

True, if the administrator asked for SBR the kernel should work to honor
that regardless of any quirks like CXL SBR masking that might be in
effect.

Is that effectively a new reset_method? In other words, teach the kernel
to toggle "Unmask SBR" on demand, but only if the selected reset_method
is "cxl_bus". That at least allows us a place to hook some documentation
around why this is a potentially system-catastrophic event.

Otherwise CXL SBR masking is in effect modeled as just another way to
indicate a PCI_DEV_FLAGS_NO_BUS_RESET quirk.