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Tsirkin" , Igor Mammedov , linux-cxl@vger.kernel.org, Ben Widawsky , Peter Maydell , linuxarm@huawei.com, Shameerali Kolothum Thodi , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Saransh Gupta1 , Shreyas Shah , Chris Browy , Samarth Saxena , Dan Williams Subject: Re: [PATCH v6 18/43] qtests/cxl: Add initial root port and CXL type3 tests Date: Tue, 01 Mar 2022 18:11:25 +0000 In-reply-to: <20220211120747.3074-19-Jonathan.Cameron@huawei.com> Message-ID: <87h78hlewu.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Jonathan Cameron writes: > At this stage we can boot configurations with host bridges, > root ports and type 3 memory devices, so add appropriate > tests. > > Signed-off-by: Jonathan Cameron > --- > tests/qtest/cxl-test.c | 126 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 126 insertions(+) > > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c > index 1006c8ae4e..1436de40e2 100644 > --- a/tests/qtest/cxl-test.c > +++ b/tests/qtest/cxl-test.c > @@ -8,6 +8,47 @@ > #include "qemu/osdep.h" > #include "libqtest-single.h" >=20=20 > +#define QEMU_PXB_CMD "-machine q35,cxl=3Don " \ > + "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D5= 2 " > + > +#define QEMU_2PXB_CMD "-machine q35,cxl=3Don " \ > + "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D= 52 " \ > + "-device pxb-cxl,id=3Dcxl.1,bus=3Dpcie.0,bus_nr=3D= 53 " > + > +#define QEMU_RP "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D= 0 " > + > +/* Dual ports on first pxb */ > +#define QEMU_2RP "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot= =3D0 " \ > + "-device cxl-rp,id=3Drp1,bus=3Dcxl.0,chassis=3D0,slot= =3D1 " > + > +/* Dual ports on each of the pxb instances */ > +#define QEMU_4RP "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot= =3D0 " \ > + "-device cxl-rp,id=3Drp1,bus=3Dcxl.0,chassis=3D0,slot= =3D1 " \ > + "-device cxl-rp,id=3Drp2,bus=3Dcxl.1,chassis=3D0,slot= =3D2 " \ > + "-device cxl-rp,id=3Drp3,bus=3Dcxl.1,chassis=3D0,slot= =3D3 " > + > +#define QEMU_T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%= s,size=3D256M " \ > + "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,id=3Dcxl= -pmem0,size=3D256M " > + > +#define QEMU_2T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D= %s,size=3D256M " \ > + "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,id=3Dcx= l-pmem0,size=3D256M " \ > + "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D= %s,size=3D256M " \ > + "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,id=3Dcx= l-pmem1,size=3D256M " > + > +#define QEMU_4T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D= %s,size=3D256M " \ > + "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,id=3Dcx= l-pmem0,size=3D256M " \ > + "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D= %s,size=3D256M " \ > + "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,id=3Dcx= l-pmem1,size=3D256M " \ > + "-object memory-backend-file,id=3Dcxl-mem2,mem-path=3D= %s,size=3D256M " \ > + "-device cxl-type3,bus=3Drp2,memdev=3Dcxl-mem2,id=3Dcx= l-pmem2,size=3D256M " \ > + "-object memory-backend-file,id=3Dcxl-mem3,mem-path=3D= %s,size=3D256M " \ > + "-device cxl-type3,bus=3Drp3,memdev=3Dcxl-mem3,id=3Dcx= l-pmem3,size=3D256M " > + > +static void cxl_basic_hb(void) > +{ > + qtest_start("-machine q35,cxl=3Don"); > + qtest_end(); > +} >=20=20 > static void cxl_basic_pxb(void) > { > @@ -15,9 +56,94 @@ static void cxl_basic_pxb(void) > qtest_end(); > } >=20=20 > +static void cxl_pxb_with_window(void) > +{ > + qtest_start(QEMU_PXB_CMD); > + qtest_end(); > +} > + > +static void cxl_2pxb_with_window(void) > +{ > + qtest_start(QEMU_2PXB_CMD); > + qtest_end(); > +} > + > +static void cxl_root_port(void) > +{ > + qtest_start(QEMU_PXB_CMD QEMU_RP); > + qtest_end(); > +} > + > +static void cxl_2root_port(void) > +{ > + qtest_start(QEMU_PXB_CMD QEMU_2RP); > + qtest_end(); > +} > + > +static void cxl_t3d(void) > +{ > + GString *cmdline; > + char template[] =3D "/tmp/cxl-test-XXXXXX"; > + const char *tmpfs; > + > + tmpfs =3D mkdtemp(template); > + > + cmdline =3D g_string_new(NULL); > + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D, tmpfs); > + > + qtest_start(cmdline->str); > + qtest_end(); > + > + g_string_free(cmdline, TRUE); For future reference you could do: g_autoptr(GString) cmdline =3D g_string_new(NULL); and drop the free ;-) > +} > + > +static void cxl_1pxb_2rp_2t3d(void) > +{ > + GString *cmdline; > + char template[] =3D "/tmp/cxl-test-XXXXXX"; > + const char *tmpfs; > + > + tmpfs =3D mkdtemp(template); > + > + cmdline =3D g_string_new(NULL); > + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_2RP QEMU_2T3D, tmpfs, tmp= fs); > + > + qtest_start(cmdline->str); > + qtest_end(); > + > + g_string_free(cmdline, TRUE); > +} > + > +static void cxl_2pxb_4rp_4t3d(void) > +{ > + GString *cmdline; > + char template[] =3D "/tmp/cxl-test-XXXXXX"; > + const char *tmpfs; > + > + tmpfs =3D mkdtemp(template); > + > + cmdline =3D g_string_new(NULL); > + g_string_printf(cmdline, QEMU_2PXB_CMD QEMU_4RP QEMU_4T3D, > + tmpfs, tmpfs, tmpfs, tmpfs); > + > + qtest_start(cmdline->str); > + qtest_end(); > + > + g_string_free(cmdline, TRUE); > +} > + > int main(int argc, char **argv) > { > g_test_init(&argc, &argv, NULL); > + > + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > + qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); > + qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); > + qtest_add_func("/pci/cxl/rp", cxl_root_port); > + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > + qtest_add_func("/pci/cxl/type3_device", cxl_t3d); > + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp= _4t3d); > return g_test_run(); > } Otherwise: Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e