messages from 2021-04-07 22:28:35 to 2021-05-26 17:44:26 UTC [more...]
[PATCH] cxl: Rename mem to pci
2021-05-26 17:44 UTC (5+ messages)
` [PATCH v2] "
` [PATCH v3] "
[PATCH v2 0/5] Map register blocks individually
2021-05-25 14:28 UTC (11+ messages)
` [PATCH v2 1/5] cxl/mem: Introduce cxl_decode_register_block()
` [PATCH v2 2/5] cxl/mem: Reserve all device regions at once
` [PATCH v2 3/5] cxl/mem: Map registers based on capabilities
` [PATCH v2 4/5] cxl/mem: Reserve individual register block regions
` [PATCH v2 5/5] cxl: Add HDM decoder capbilities
[PATCH v4 0/5] PCI Data Object Exchange support + CXL CDAT
2021-05-25 10:26 UTC (7+ messages)
` [PATCH v4 1/5] PCI: Add vendor ID for the PCI SIG
` [PATCH v4 2/5] PCI/DOE: Add Data Object Exchange support
` [PATCH v4 3/5] cxl/mem: Add CDAT table reading from DOE
` [PATCH v4 4/5] DONOTMERGE: PCI/DOE: Add per DOE chrdev for ioctl based access
` [PATCH v4 5/5] DONOTMERGE: PCI/DOE: Add userspace example program to tools/pci
[PATCH 0/7] Enumerate HDM Decoder registers
2021-05-20 21:29 UTC (22+ messages)
` [PATCH 1/7] cxl/mem: Use dev instead of pdev->dev
` [PATCH 2/7] cxl/mem: Split creation from mapping in probe
` [PATCH 3/7] cxl/mem: Move register locator logic into reg setup
` [PATCH 4/7] cxl/mem: Get rid of @cxlm.base
` [PATCH v2 "
` [PATCH 5/7] cxl/mem: Move device register setup
` [PATCH 6/7] cxl/mem: Create a helper to setup device regs
` [PATCH 7/7] cxl: Add HDM decoder capbilities
[PATCH] cxl/mem: Demarcate vendor specific capability IDs
2021-05-20 20:55 UTC (2+ messages)
[PATCH] cxl/docs: Fix "Title underline too short" warning
2021-05-20 19:54 UTC (2+ messages)
[PATCH] cxl/pci.c: Add a 'label_storage_size' attribute to the memdev
2021-05-20 19:50 UTC (2+ messages)
[PATCH 0/4] Map register blocks individually
2021-05-20 19:44 UTC (10+ messages)
` [PATCH 1/4] cxl/mem: Fully decode device capability header
` [PATCH 2/4] cxl/mem: Reserve all device regions at once
` [PATCH 3/4] cxl/mem: Introduce cxl_decode_register_block()
` [PATCH 4/4] cxl/mem: Map registers based on capabilities
CXL Vendor Specific Capabilities
2021-05-20 11:55 UTC (3+ messages)
[RFC PATCH v3 0/4] PCI Data Object Exchange support + CXL CDAT
2021-05-20 8:22 UTC (31+ messages)
` [RFC PATCH v3 1/4] PCI: Add vendor ID for the PCI SIG
` [RFC PATCH v3 2/4] PCI/doe: Add Data Object Exchange support
` [RFC PATCH v3 3/4] cxl/mem: Add CDAT table reading from DOE
` [RFC PATCH v3 4/4] cxl/mem: Add a debug parser for CDAT commands
[PATCH 1/3] cxl/mem: Fix register block offset calculation
2021-05-19 20:01 UTC (11+ messages)
` [PATCH 2/3] cxl/mem: Print unknown capability IDs as hex
` [PATCH 3/3] cxl/mem: Demarcate vendor specific capability IDs
` [PATCH v2] cxl/mem: Fix register block offset calculation
Access to CXL memory
2021-05-18 1:57 UTC (2+ messages)
[RFC PATCH] Documentation/arm64: describe the kernel's expectations of 'memory'
2021-05-17 12:25 UTC (4+ messages)
[PATCH v4 0/8] CXL Port Enumeration and Plans for v5.14
2021-05-14 22:54 UTC (13+ messages)
` [PATCH v4 1/8] cxl/mem: Move some definitions to mem.h
` [PATCH v4 2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices
` [PATCH v4 3/8] cxl/core: Rename bus.c to core.c
` [PATCH v4 4/8] cxl/core: Refactor CXL register lookup for bridge reuse
` [PATCH v4 5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root
` [PATCH v5 "
` [PATCH v4 6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS
` [PATCH v4 7/8] cxl/port: Introduce cxl_port objects
` [PATCH v5 "
` [PATCH v4 8/8] cxl/acpi: Add module parameters to stand in for ACPI tables
[PATCH v3 0/8] CXL Port Enumeration and Plans for v5.14
2021-05-12 6:36 UTC (22+ messages)
` [PATCH 1/8] cxl/mem: Move some definitions to mem.h
` [PATCH 2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices
` [PATCH 3/8] cxl/core: Rename bus.c to core.c
` [PATCH 4/8] cxl/core: Refactor CXL register lookup for bridge reuse
` [PATCH 5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root
` [PATCH 6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS
` [PATCH 7/8] cxl/port: Introduce cxl_port objects
` [PATCH 8/8] cxl/acpi: Add module parameters to stand in for ACPI tables
Personal
2021-05-10 14:06 UTC
CXL HDM alignment
2021-05-07 1:43 UTC
Get back To Me
2021-05-01 9:22 UTC
CXL mailbox background command
2021-04-30 1:42 UTC (5+ messages)
CXL mailbox background command
2021-04-29 1:24 UTC
[PATCH v5 cxl2.0-v3-doe 2/6] include/hw/pci: headers for PCIe DOE
2021-04-28 13:47 UTC (4+ messages)
` [PATCH v5 cxl2.0-v3-doe 3/6] hw/pci: PCIe Data Object Exchange implementation
` [PATCH v5 cxl2.0-v3-doe 4/6] cxl/compliance: CXL Compliance "
` [PATCH v5 cxl2.0-v3-doe 5/6] cxl/cdat: CXL CDAT "
[ACPI Code First ECN v2]: Generic Port, performace data for hotplug memory
2021-04-20 17:30 UTC (9+ messages)
[GIT PULL] cxl fixes for v5.12-rc8 / final
2021-04-17 17:02 UTC (2+ messages)
[PATCH] cxl/mem: Fix memory device capacity probing
2021-04-17 0:54 UTC (2+ messages)
CXL Trees for linux-next
2021-04-16 2:42 UTC (5+ messages)
[PATCH v2 0/8] CXL Port Enumeration
2021-04-15 20:53 UTC (15+ messages)
` [PATCH v2 1/8] cxl/mem: Move some definitions to mem.h
` [PATCH v2 2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices
` [PATCH v2 4/8] cxl/core: Refactor CXL register lookup for bridge reuse
` [PATCH v2 5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root
[PATCH v2 7/8] cxl/port: Introduce cxl_port objects
2021-04-15 5:21 UTC (6+ messages)
[RFC PATCH v2 0/4] PCI Data Object Exchange support + CXL CDAT
2021-04-14 18:50 UTC (11+ messages)
` [RFC PATCH v2 1/4] PCI: Add vendor define ID for the PCI SIG
` [RFC PATCH v2 2/4] PCI/doe: Initial support PCI Data Object Exchange
` [RFC PATCH v2 3/4] cxl/mem: Add CDAT table reading from DOE
` [RFC PATCH v2 4/4] cxl/mem: Add a debug parser for CDAT commands
[PATCH] cxl/mem: Clarify UAPI documentation
2021-04-14 12:37 UTC (2+ messages)
[PATCH] cxl/mem: Add media provisioning required commands
2021-04-14 12:36 UTC (2+ messages)
[PATCH v4 cxl-2.0-doe 1/3] PCIe Data Object Exchange implementation
2021-04-09 15:27 UTC (3+ messages)
` [PATCH v4 cxl-2.0-doe 2/3] CXL "
` [PATCH v4 cxl-2.0-doe 3/3] PCIe standard header for DOE
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