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 messages from 2021-11-20 00:03:11 to 2021-12-10 19:38:53 UTC [more...]

[PATCH v5 21/21] cxl/core: Split decoder setup into alloc + add
 2021-12-10 19:38 UTC  (3+ messages)
` [PATCH v6 "

[ndctl PATCH v5 00/16] Initial CXL support
 2021-12-09 21:23 UTC  (7+ messages)
` [ndctl PATCH v5 02/16] cxl: add a cxl utility and libcxl library
    ` [ndctl PATCH v6] "
        ` [ndctl PATCH v7] "

[PATCH 00/23] Add drivers for CXL ports and mem devices
 2021-12-07  4:48 UTC  (127+ messages)
` [PATCH 01/23] cxl: Rename CXL_MEM to CXL_PCI
` [PATCH 02/23] cxl: Flesh out register names
` [PATCH 03/23] cxl/pci: Extract device status check
` [PATCH 04/23] cxl/pci: Implement Interface Ready Timeout
` [PATCH 05/23] cxl/pci: Don't poll doorbell for mailbox access
` [PATCH 06/23] cxl/pci: Don't check media status for mbox access
` [PATCH 07/23] cxl/pci: Add new DVSEC definitions
` [PATCH 08/23] cxl/acpi: Map component registers for Root Ports
` [PATCH 09/23] cxl: Introduce module_cxl_driver
` [PATCH 10/23] cxl/core: Convert decoder range to resource
` [PATCH 11/23] cxl/core: Document and tighten up decoder APIs
` [PATCH 12/23] cxl: Introduce endpoint decoders
` [PATCH 13/23] cxl/core: Move target population locking to caller
` [PATCH 14/23] cxl: Introduce topology host registration
` [PATCH 15/23] cxl/core: Store global list of root ports
` [PATCH 16/23] cxl/pci: Cache device DVSEC offset
` [PATCH 17/23] cxl: Cache and pass DVSEC ranges
` [PATCH 18/23] cxl/pci: Implement wait for media active
` [PATCH 19/23] cxl/pci: Store component register base in cxlds
` [PATCH 20/23] cxl/port: Introduce a port driver
` [PATCH 21/23] cxl: Unify port enumeration for decoders
` [PATCH 22/23] cxl/mem: Introduce cxl_mem driver
` [PATCH 23/23] cxl/mem: Disable switch hierarchies for now

[PATCH 0/2] cxl/mailbox: Replace racy error checking with timeouts
 2021-12-06 17:33 UTC  (10+ messages)
` [PATCH 1/2] cxl/pci: Implement Interface Ready Timeout
` [PATCH 2/2] cxl/pci: Defer mailbox status checks to command timeouts

[PATCH 2/5] PCI/DOE: Add Data Object Exchange Aux Driver
 2021-12-06 12:27 UTC  (6+ messages)

[PATCH v2 00/14] Add drivers for CXL ports and mem devices
 2021-12-06 10:51 UTC  (21+ messages)
` [PATCH v2 01/14] cxl/core: Add, document, and tighten up decoder APIs
` [PATCH v2 02/14] cxl: Introduce endpoint decoders
` [PATCH v2 03/14] cxl/core: Move target population locking to caller
` [PATCH v2 04/14] cxl: Introduce topology host registration
` [PATCH v2 05/14] cxl/core: Store global list of root ports
` [PATCH v2 06/14] cxl/pci: Cache device DVSEC offset
` [PATCH v2 07/14] cxl: Cache and pass DVSEC ranges
` [PATCH v2 08/14] cxl/pci: Implement wait for media active
` [PATCH v2 09/14] cxl/pci: Store component register base in cxlds
` [PATCH v2 10/14] cxl: Make passthrough decoder init implicit
` [PATCH v2 11/14] cxl/port: Introduce a port driver
` [PATCH v2 12/14] cxl: Unify port enumeration for decoders
` [PATCH v2 13/14] cxl/port: Cleanup adding passthrough decoders
` [PATCH v2 14/14] cxl/mem: Introduce cxl_mem driver

[PATCH 0/9] CXL port prep work
 2021-12-04  5:13 UTC  (22+ messages)
` [PATCH 1/9] cxl: Rename CXL_MEM to CXL_PCI
` [PATCH 2/9] cxl: Flesh out register names
` [PATCH 3/9] cxl/pci: Extract device status check
` [PATCH 4/9] cxl/pci: Implement Interface Ready Timeout
    ` [PATCH v2 "
` [PATCH 5/9] cxl/pci: Don't poll doorbell for mailbox access
` [PATCH 6/9] cxl/pci: Add new DVSEC definitions
` [PATCH 7/9] cxl/acpi: Map component registers for Root Ports
` [PATCH 8/9] cxl: Introduce module_cxl_driver
` [PATCH 9/9] cxl/core: Convert decoder range to resource

[RFC PATCH v3 00/31] CXL 2.0 Support
 2021-12-02 10:32 UTC  (3+ messages)
` [RFC PATCH v3 14/31] acpi/pci: Consolidate host bridge setup

Follow-up on the CXL discussion at OFTC
 2021-12-01 10:29 UTC  (17+ messages)

[RFT PATCH] x86/pat: Fix set_mce_nospec() for pmem
 2021-11-30 23:00 UTC  (2+ messages)

[PATCH 3/5] cxl/pci: Add DOE Auxiliary Devices
 2021-11-30  6:42 UTC  (6+ messages)

[PATCH 17/23] cxl: Cache and pass DVSEC ranges
 2021-11-29  9:39 UTC 


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