messages from 2022-01-25 13:56:11 to 2022-02-01 15:17:31 UTC [more...]
[PATCH v3 00/40] CXL.mem Topology Discovery and Hotplug Support
2022-02-01 15:17 UTC (87+ messages)
` [PATCH v3 02/40] cxl/pci: Implement Interface Ready Timeout
` [PATCH v4 "
` [PATCH v3 03/40] cxl/pci: Defer mailbox status checks to command timeouts
` [PATCH v3 08/40] cxl/core/port: Rename bus.c to port.c
` [PATCH v3 09/40] cxl/decoder: Hide physical address information from non-root
` [PATCH v3 11/40] cxl/core/port: Clarify decoder creation
` [PATCH v4 "
` [PATCH v3 12/40] cxl/core: Fix cxl_probe_component_regs() error message
` [PATCH v3 13/40] cxl/core/port: Make passthrough decoder init implicit
` [PATCH v3 14/40] cxl/core: Track port depth
` [PATCH v3 15/40] cxl: Prove CXL locking
` [PATCH v4 "
` [PATCH v3 17/40] cxl/port: Introduce cxl_port_to_pci_bus()
` [PATCH v4 "
` [PATCH v3 19/40] cxl/port: Up-level cxl_add_dport() locking requirements to the caller
` [PATCH v4 "
` [PATCH v3 20/40] cxl/pci: Rename pci.h to cxlpci.h
` [PATCH v3 21/40] cxl/core: Generalize dport enumeration in the core
` [PATCH v4 "
` [PATCH v3 22/40] cxl/core/hdm: Add CXL standard decoder enumeration to "
` [PATCH v4 "
` [PATCH v3 23/40] cxl/core: Emit modalias for CXL devices
` [PATCH v3 25/40] cxl/core/port: Remove @host argument for dport + decoder enumeration
` [PATCH v3 26/40] cxl/pci: Store component register base in cxlds
` [PATCH v3 27/40] cxl/pci: Cache device DVSEC offset
` [PATCH v3 28/40] cxl/pci: Retrieve CXL DVSEC memory info
` [PATCH v3 29/40] cxl/pci: Implement wait for media active
` [PATCH v3 30/40] cxl/pci: Emit device serial number
` [PATCH v4 "
` [PATCH v3 31/40] cxl/memdev: Add numa_node attribute
` [PATCH v3 32/40] cxl/core/port: Add switch port enumeration
` [PATCH v3 34/40] cxl/core: Move target_list out of base decoder attributes
` [PATCH v3 35/40] cxl/core/port: Add endpoint decoders
` [PATCH v3 40/40] tools/testing/cxl: Add a physical_node link
[PATCH v3 00/14] CXL Region driver
2022-02-01 14:59 UTC (19+ messages)
` [PATCH v3 01/14] cxl/region: Add region creation ABI
` [PATCH v3 02/14] cxl/region: Introduce concept of region configuration
` [PATCH v3 03/14] cxl/mem: Cache port created by the mem dev
` [PATCH v3 04/14] cxl/region: Introduce a cxl_region driver
` [PATCH v3 05/14] cxl/acpi: Handle address space allocation
` [PATCH v3 06/14] cxl/region: Address "
` [PATCH v3 07/14] cxl/region: Implement XHB verification
` [PATCH v3 08/14] cxl/region: HB port config verification
` [PATCH v3 09/14] cxl/region: Add infrastructure for decoder programming
` [PATCH v3 10/14] cxl/region: Collect host bridge decoders
` [PATCH v3 11/14] cxl/region: Add support for single switch level
` [PATCH v3 12/14] cxl: Program decoders for regions
` [PATCH v3 13/14] cxl/pmem: Convert nvdimm bridge API to use dev
` [PATCH v3 14/14] cxl/region: Create an nd_region
[PATCH 0/2] cxl/port: Robustness fixes for decoder enumeration
2022-02-01 12:59 UTC (5+ messages)
` [PATCH 1/2] cxl/core/port: Fix / relax decoder target enumeration
` [PATCH 2/2] cxl/core/port: Handle invalid decoders
[PATCH v3 33/40] cxl/mem: Add the cxl_mem driver
2022-02-01 12:45 UTC (3+ messages)
` [PATCH v4 "
[PATCH v3 18/40] cxl/pmem: Introduce a find_cxl_root() helper
2022-02-01 10:59 UTC (8+ messages)
` [PATCH v4 "
` [PATCH v5 "
` [PATCH v6 "
[PATCH v3 16/40] cxl/core/port: Use dedicated lock for decoder target list
2022-02-01 10:52 UTC (10+ messages)
` [PATCH v4 "
` [PATCH v5 "
[PATCH V6 00/10] CXL: Read CDAT and DSMAS data from the device
2022-02-01 7:19 UTC (11+ messages)
` [PATCH V6 01/10] PCI: Add vendor ID for the PCI SIG
` [PATCH V6 02/10] PCI: Replace magic constant for PCI Sig Vendor ID
` [PATCH V6 03/10] PCI/DOE: Add Data Object Exchange Aux Driver
` [PATCH V6 04/10] PCI/DOE: Introduce pci_doe_create_doe_devices
` [PATCH V6 05/10] cxl/pci: Create DOE auxiliary devices
` [PATCH V6 06/10] cxl/pci: Find the DOE mailbox which supports CDAT
` [PATCH V6 07/10] cxl/mem: Read CDAT table
` [PATCH V6 08/10] cxl/cdat: Introduce cdat_hdr_valid()
` [PATCH V6 09/10] cxl/mem: Retry reading CDAT on failure
` [PATCH V6 10/10] cxl/cdat: Parse out DSMAS data from CDAT table
[ndctl PATCH v3 0/6] Add partitioning support for CXL memdevs
2022-02-01 1:34 UTC (23+ messages)
` [ndctl PATCH v3 1/6] libcxl: add GET_PARTITION_INFO mailbox command and accessors
` [ndctl PATCH v3 2/6] libcxl: add accessors for capacity fields of the IDENTIFY command
` [ndctl PATCH v3 3/6] libcxl: return the partition alignment field in bytes
` [ndctl PATCH v3 4/6] cxl: add memdev partition information to cxl-list
` [ndctl PATCH v3 5/6] libcxl: add interfaces for SET_PARTITION_INFO mailbox command
` [ndctl PATCH v3 6/6] cxl: add command set-partition-info
[PATCH v3 24/40] cxl/port: Add a driver for 'struct cxl_port' objects
2022-01-31 18:11 UTC (3+ messages)
` [PATCH v4 "
[RFC PATCH 0/3] Add PCIe enclosure management support
2022-01-31 11:59 UTC (3+ messages)
` [RFC PATCH 2/3] Add PCIe enclosure management auxiliary driver
[ndctl PATCH v5 00/16] Initial CXL support
2022-01-31 11:47 UTC (3+ messages)
` [ndctl PATCH v5 04/16] util: add the struct_size() helper from the kernel
Treating CXL Type 3 device as a block device
2022-01-28 19:50 UTC (3+ messages)
[PATCH v4 00/42] CXl 2.0 emulation Support
2022-01-28 18:48 UTC (66+ messages)
` [PATCH v4 01/42] hw/pci/cxl: Add a CXL component type (interface)
` [PATCH v4 02/42] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)
` [PATCH v4 03/42] MAINTAINERS: Add entry for Compute Express Link Emulation
` [PATCH v4 04/42] hw/cxl/device: Introduce a CXL device (8.2.8)
` [PATCH v4 05/42] hw/cxl/device: Implement the CAP array (8.2.8.1-2)
` [PATCH v4 06/42] hw/cxl/device: Implement basic mailbox (8.2.8.4)
` [PATCH v4 07/42] hw/cxl/device: Add memory device utilities
` [PATCH v4 08/42] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1)
` [PATCH v4 09/42] hw/cxl/device: Timestamp implementation (8.2.9.3)
` [PATCH v4 10/42] hw/cxl/device: Add log commands (8.2.9.4) + CEL
` [PATCH v4 11/42] hw/pxb: Use a type for realizing expanders
` [PATCH v4 12/42] hw/pci/cxl: Create a CXL bus type
` [PATCH v4 13/42] hw/pxb: Allow creation of a CXL PXB (host bridge)
` [PATCH v4 14/42] tests/acpi: allow DSDT.viot table changes
` [PATCH v4 15/42] acpi/pci: Consolidate host bridge setup
` [PATCH v4 16/42] tests/acpi: Add update DSDT.viot
` [PATCH v4 17/42] cxl: Machine level control on whether CXL support is enabled
` [PATCH v4 27/42] hw/cxl/device: Implement get/set Label Storage Area (LSA)
` [PATCH v4 29/42] hw/cxl/host: Add support for CXL Fixed Memory Windows
` [PATCH v4 31/42] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl
Should bios always mark CXL DRAM as EFI_MEMORY_SP?
2022-01-28 16:12 UTC (6+ messages)
[PATCH 0/4] Unify meaning of interleave attributes
2022-01-28 10:15 UTC (9+ messages)
` [PATCH 1/4] cxl/acpi: Store interleave granularity absolutely
` [PATCH 2/4] cxl/core: Add more decoder attributes to sysfs
` [PATCH 3/4] cxl/core: Extract IW/IG decoding
` [PATCH 4/4] cxl/acpi: Use common "
Patch: Make ACPI subsystem provide CEDT table
2022-01-27 10:15 UTC (5+ messages)
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