From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F279C433B4 for ; Thu, 15 Apr 2021 20:53:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 80BA761166 for ; Thu, 15 Apr 2021 20:53:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235305AbhDOUyW (ORCPT ); Thu, 15 Apr 2021 16:54:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235063AbhDOUyV (ORCPT ); Thu, 15 Apr 2021 16:54:21 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33824C06175F for ; Thu, 15 Apr 2021 13:53:58 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id j12so4685436edy.3 for ; Thu, 15 Apr 2021 13:53:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Caxsq6e5w5hQHzn1UKSM5N/N92XMDfAKUSIuBiGg3co=; b=jfaruwTDBJhPEKQ+qT+r2RQ5DZYvXkNdItYaLCzE+XzuI8fDE/3egCvAmxAQkQTiOw sAnxvqxSejrXWgvGuJEUrtowr3zeumlHpYbymconBrIDs3iMy2OCDXX5CmgfhI5tkUGo a1hFFpnj0UxHeaQBM57ny7f+AEJq7JmrLYtxxPlhCO7OhC+t8iy69UlGgQhVHwx6FYgz FksTuAQW5dxKrKxOAQhRX3PKSOYbISq/OpQ1catH5/zpedXM2WEZ2aRrwSEhXsTRbYXM 8fDUp+3DPqm9ap4ufqtakMIIduXVGDM8ns9Ydf2YXQFlFp7scc6yzcg68wKm58YIY1G3 J7jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Caxsq6e5w5hQHzn1UKSM5N/N92XMDfAKUSIuBiGg3co=; b=ZEyuYjuGohVxhzI1VFBlrB3z0/nGfS2GeZhCTdf+NSJbMZi5wVlOvgUyzfIfc07deH FUjWWEBV+kSlpY5nfVsNx0v/Q1+k+H/iV8RdV7/65/Mou4zJTmF0cJJradmVdHkLk80u A0p8Zv/3jeBzcgLZAQpfCzEbg0tt0evz9/8RxlfQZLr6BKeyO5U1F3dNuylgvo/V3b/6 cRuK8RMdrtVVb8Y3VmREb3InCMgf4pKsZAPuW7wctoVhadzn4namAWaIG9bjRpMlHs/y OqH/6/IvwVJbStbX4l38hNFmjCvhXQXbLhBfbAtnl4MHBlkYuWHREucNCX7w8uzjal1m z5jw== X-Gm-Message-State: AOAM5325x3lSao07Y2emdIoB5E1JU61wBfG+YxjjnS/mqbK2Jf756YNE dmXPzPYCZvcdy6VqBE7dT1WZPZO5nfp2Z6aI/ZV7Og== X-Google-Smtp-Source: ABdhPJwGTnM9gKHfSenuZUu2QdmiM+hPocsH6E5LwiEukrwmUz1IvJmjkAvwkbTmOJyECBXmisr84jGxDwbChsANS1k= X-Received: by 2002:aa7:cd7b:: with SMTP id ca27mr6607714edb.354.1618520036847; Thu, 15 Apr 2021 13:53:56 -0700 (PDT) MIME-Version: 1.0 References: <161728744224.2474040.12854720917440712854.stgit@dwillia2-desk3.amr.corp.intel.com> <161728746354.2474040.14531317270409827157.stgit@dwillia2-desk3.amr.corp.intel.com> <20210406180017.00000875@Huawei.com> In-Reply-To: <20210406180017.00000875@Huawei.com> From: Dan Williams Date: Thu, 15 Apr 2021 13:53:45 -0700 Message-ID: Subject: Re: [PATCH v2 4/8] cxl/core: Refactor CXL register lookup for bridge reuse To: Jonathan Cameron Cc: linux-cxl@vger.kernel.org, Linux PCI , Linux ACPI , "Weiny, Ira" , Vishal L Verma , "Schofield, Alison" , Ben Widawsky , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org On Tue, Apr 6, 2021 at 10:47 AM Jonathan Cameron wrote: > > On Thu, 1 Apr 2021 07:31:03 -0700 > Dan Williams wrote: > > > While CXL Memory Device endpoints locate the CXL MMIO registers in a PCI > > BAR, CXL root bridges have their MMIO base address described by platform > > firmware. Refactor the existing register lookup into a generic facility > > for endpoints and bridges to share. > > > > Reviewed-by: Ben Widawsky > > Signed-off-by: Dan Williams > > Nice to make the docs kernel-doc, but otherwise this is simple and makes sense > > Reviewed-by: Jonathan Cameron > > > --- > > drivers/cxl/core.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++- > > drivers/cxl/cxl.h | 3 +++ > > drivers/cxl/mem.c | 50 +++++----------------------------------------- > > 3 files changed, 65 insertions(+), 45 deletions(-) > > > > diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c > > index 7f8d2034038a..2ab467ef9909 100644 > > --- a/drivers/cxl/core.c > > +++ b/drivers/cxl/core.c > > @@ -1,7 +1,8 @@ > > // SPDX-License-Identifier: GPL-2.0-only > > -/* Copyright(c) 2020 Intel Corporation. All rights reserved. */ > > +/* Copyright(c) 2020-2021 Intel Corporation. All rights reserved. */ > > #include > > #include > > +#include "cxl.h" > > > > /** > > * DOC: cxl core > > @@ -10,6 +11,60 @@ > > * point for cross-device interleave coordination through cxl ports. > > */ > > > > +/* > > + * cxl_setup_device_regs() - Detect CXL Device register blocks > > + * @dev: Host device of the @base mapping > > + * @base: mapping of CXL 2.0 8.2.8 CXL Device Register Interface > > Not much to add to make this kernel-doc. Just the one missing parameter > and mark it /** Given it's exported, it would be nice to tidy that up. Will do, thanks.