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From: Dan Williams <dan.j.williams@intel.com>
To: Ben Widawsky <ben.widawsky@intel.com>
Cc: linux-cxl@vger.kernel.org, Andrew Donnellan <ajd@linux.ibm.com>,
	Bjorn Helgaas <helgaas@kernel.org>,
	"David E. Box" <david.e.box@linux.intel.com>,
	David Woodhouse <dwmw2@infradead.org>,
	Frederic Barrat <fbarrat@linux.ibm.com>,
	Kan Liang <kan.liang@linux.intel.com>,
	Lu Baolu <baolu.lu@linux.intel.com>,
	"open list:DMA MAPPING HELPERS"
	<iommu@lists.linux-foundation.org>,
	Linux PCI <linux-pci@vger.kernel.org>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH v2 4/9] cxl/pci: Refactor cxl_pci_setup_regs
Date: Tue, 28 Sep 2021 10:35:34 -0700	[thread overview]
Message-ID: <CAPcyv4i7Dytarp3Hxi_ECtCU+Ve985dNCh07a8wJX0sTgCnR0Q@mail.gmail.com> (raw)
In-Reply-To: <20210923172647.72738-5-ben.widawsky@intel.com>

On Thu, Sep 23, 2021 at 10:27 AM Ben Widawsky <ben.widawsky@intel.com> wrote:
>
> In preparation for moving parts of register mapping to cxl_core, the
> cxl_pci driver is refactored to utilize a new helper to find register
> blocks by type.
>
> cxl_pci scanned through all register blocks and mapping the ones that
> the driver will use. This logic is inverted so that the driver
> specifically requests the register blocks from a new helper. Under the
> hood, the same implementation of scanning through all register locator
> DVSEC entries exists.
>
> There are 2 behavioral changes (#2 is arguable):
> 1. A dev_err is introduced if cxl_map_regs fails.
> 2. The previous logic would try to map component registers and device
>    registers multiple times if there were present and keep the mapping
>    of the last one found (furthest offset in the register locator).
>    While this is disallowed in the spec, CXL 2.0 8.1.9: "Each register
>    block identifier shall only occur once in the Register Locator DVSEC
>    structure" it was how the driver would respond to the spec violation.
>    The new logic will take the first found register block by type and
>    move on.
>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
>
> ---
> Changes since v1:

No changes? Luckily git am strips this section...

Overall I think this refactor can be broken down further for
readability and cleanup the long standing problem that the driver maps
component registers for no reason. The main contributing factor to
readability is that cxl_setup_pci_regs() still exists after the
refactor, which also contributes to the component register problem. If
the register mapping is up leveled to the caller of
cxl_setup_pci_regs() (and drops mapping component registers) then a
follow-on patch to rename cxl_setup_pci_regs to find_register_block
becomes easier to read. Moving the cxl_register_map array out of
cxl_setup_pci_regs() also makes a later patch to pass component
register enumeration details to the endpoint-port that much cleaner.

  reply	other threads:[~2021-09-28 17:35 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-23 17:26 [PATCH v2 0/9] cxl_pci refactor for reusability Ben Widawsky
2021-09-23 17:26 ` [PATCH v2 1/9] cxl: Convert "RBI" to enum Ben Widawsky
2021-09-27 23:13   ` Dan Williams
2021-09-23 17:26 ` [PATCH v2 2/9] cxl/pci: Remove dev_dbg for unknown register blocks Ben Widawsky
2021-09-28 14:37   ` Dan Williams
2021-09-23 17:26 ` [PATCH v2 3/9] cxl/pci: Remove pci request/release regions Ben Widawsky
2021-09-28 14:42   ` Dan Williams
2021-09-23 17:26 ` [PATCH v2 4/9] cxl/pci: Refactor cxl_pci_setup_regs Ben Widawsky
2021-09-28 17:35   ` Dan Williams [this message]
2021-09-23 17:26 ` [PATCH v2 5/9] cxl/pci: Make more use of cxl_register_map Ben Widawsky
2021-09-28 17:41   ` Dan Williams
2021-09-23 17:26 ` [PATCH v2 6/9] PCI: Add pci_find_dvsec_capability to find designated VSEC Ben Widawsky
2021-09-23 21:37   ` Liang, Kan
2021-09-27 17:46   ` Bjorn Helgaas
2021-09-28  5:50   ` Andrew Donnellan
2021-10-01  9:42   ` Jonathan Cameron
2021-09-23 17:26 ` [PATCH v2 7/9] cxl/pci: Use pci core's DVSEC functionality Ben Widawsky
2021-09-28 17:43   ` Dan Williams
2021-09-23 17:26 ` [PATCH v2 8/9] ocxl: " Ben Widawsky
2021-09-28  5:52   ` Andrew Donnellan
2021-09-23 17:26 ` [PATCH v2 9/9] iommu/vt-d: " Ben Widawsky
2021-09-24  6:42   ` Christoph Hellwig
2021-09-28 17:54   ` Dan Williams
2021-09-29  1:36     ` Lu Baolu

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