From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D665BC433FE for ; Wed, 24 Nov 2021 04:15:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232238AbhKXESd (ORCPT ); Tue, 23 Nov 2021 23:18:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232641AbhKXESc (ORCPT ); Tue, 23 Nov 2021 23:18:32 -0500 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C634C061714 for ; Tue, 23 Nov 2021 20:15:23 -0800 (PST) Received: by mail-pg1-x52e.google.com with SMTP id p17so975644pgj.2 for ; Tue, 23 Nov 2021 20:15:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel-com.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wxLF7u8QoM20c372oL9wZ9ZMbqobmlvg8VEP/5FR5bw=; b=rXcXoN9mjL9HrOaVuVtr0OkHqnoLKOCUGz9XXIMvBXGU8zsOAWbjvutZy+O9pXOGbm eSjnHVSuutZ5RAPctBjRftWx5lyNMq+cLkiliGVSKtmfHOYCJJ7VI9tVMgwkEauaN837 HOYtZYddjYFnc5UDVkK960qAZVheSl1a8q2tx2YQ9k+5Z8rz1he9fx7/22JbCcnqNCxB 7FaVpqndimVqCoZ+mLq7VZLxl26PhNCrDYWot7W47EXe92rONBodpmjWZhhaUFxkcHQl OovvbP105Dtch1rSxJ3L2f75iX7pcYOkUaGfgbjeQv2k7F6wWVq3CuJMlieIVZO556BB K9CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wxLF7u8QoM20c372oL9wZ9ZMbqobmlvg8VEP/5FR5bw=; b=aU1QNS6oKIdxO5d9KryxcyepQ1hiwcp7kolmKG5n3R8OGd7bN4WAADETh0l0iUfMNf uHd2lDdqRPygYK97Ac72lFFuyeUZzmLQ9SfmccDPQmPjd1PzdkaAZjUiMm/NQk0TZbca cJXTdBig8BpN2+5OsatNNDb9iDyyrTfmAalaT09JTx5wcRSpZnYf7kvMY3BD753j/ul8 uVlgIf1+LC7pQCoWQ9KfHMkorCpFmHYsrWihFmOpsHExVpWBuNVtYZ8EeJJD8XXM/Lmf 9/Y2fJb3mkFMgK0iGCXQ/p99Nd5H8i79SPGciw7ln7SF/9HUNb0zQu5qf+UH//XD61/z U6nA== X-Gm-Message-State: AOAM533/yDIK01WMdhm3/HbEPrNOHxnHNy5B1GAqQNFVsFKjWsikCs0V fglLi7KZ/Y0fV7SKov6xyQtjEcvi+8hNf7w/J0T9hw== X-Google-Smtp-Source: ABdhPJwn8C0TVVqaIkNJMKGMZskgbr7QkoamHPCDWPdmW74faUztMSRwKmwGJ2ltAb/0UnFcxQ39nsQ7DZeKTFbl8sk= X-Received: by 2002:aa7:8d0a:0:b0:4a2:82d7:1695 with SMTP id j10-20020aa78d0a000000b004a282d71695mr2819706pfe.86.1637727323026; Tue, 23 Nov 2021 20:15:23 -0800 (PST) MIME-Version: 1.0 References: <20211120000250.1663391-1-ben.widawsky@intel.com> <20211120000250.1663391-2-ben.widawsky@intel.com> In-Reply-To: <20211120000250.1663391-2-ben.widawsky@intel.com> From: Dan Williams Date: Tue, 23 Nov 2021 20:15:12 -0800 Message-ID: Subject: Re: [PATCH 01/23] cxl: Rename CXL_MEM to CXL_PCI To: Ben Widawsky Cc: linux-cxl@vger.kernel.org, Linux PCI , Alison Schofield , Ira Weiny , Jonathan Cameron , Vishal Verma Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org On Fri, Nov 19, 2021 at 4:03 PM Ben Widawsky wrote: > > The cxl_mem module was renamed cxl_pci in commit 21e9f76733a8 ("cxl: > Rename mem to pci"). In preparation for adding an ancillary driver for > cxl_memdev devices (registered on the cxl bus by cxl_pci), go ahead and > rename CONFIG_CXL_MEM to CONFIG_CXL_PCI. Free up the CXL_MEM name for > that new driver to manage CXL.mem endpoint operations. > > Suggested-by: Dan Williams Reviewed-by: Dan Williams > Signed-off-by: Ben Widawsky > > --- > Changes since RFCv2: > - Reword commit message (Dan) > - Reword Kconfig description (Dan) > --- > drivers/cxl/Kconfig | 23 ++++++++++++----------- > drivers/cxl/Makefile | 2 +- > 2 files changed, 13 insertions(+), 12 deletions(-) > > diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig > index 67c91378f2dd..ef05e96f8f97 100644 > --- a/drivers/cxl/Kconfig > +++ b/drivers/cxl/Kconfig > @@ -13,25 +13,26 @@ menuconfig CXL_BUS > > if CXL_BUS > > -config CXL_MEM > - tristate "CXL.mem: Memory Devices" > +config CXL_PCI > + tristate "PCI manageability" > default CXL_BUS > help > - The CXL.mem protocol allows a device to act as a provider of > - "System RAM" and/or "Persistent Memory" that is fully coherent > - as if the memory was attached to the typical CPU memory > - controller. > + The CXL specification defines a "CXL memory device" sub-class in the > + PCI "memory controller" base class of devices. Device's identified by > + this class code provide support for volatile and / or persistent > + memory to be mapped into the system address map (Host-managed Device > + Memory (HDM)). > > - Say 'y/m' to enable a driver that will attach to CXL.mem devices for > - configuration and management primarily via the mailbox interface. See > - Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more > - details. > + Say 'y/m' to enable a driver that will attach to CXL memory expander > + devices enumerated by the memory device class code for configuration > + and management primarily via the mailbox interface. See Chapter 2.3 > + Type 3 CXL Device in the CXL 2.0 specification for more details. > > If unsure say 'm'. > > config CXL_MEM_RAW_COMMANDS > bool "RAW Command Interface for Memory Devices" > - depends on CXL_MEM > + depends on CXL_PCI > help > Enable CXL RAW command interface. > > diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile > index d1aaabc940f3..cf07ae6cea17 100644 > --- a/drivers/cxl/Makefile > +++ b/drivers/cxl/Makefile > @@ -1,6 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > obj-$(CONFIG_CXL_BUS) += core/ > -obj-$(CONFIG_CXL_MEM) += cxl_pci.o > +obj-$(CONFIG_CXL_PCI) += cxl_pci.o > obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o > obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o > > -- > 2.34.0 >