From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB4D1C433ED for ; Wed, 12 May 2021 06:36:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8DEB160FD9 for ; Wed, 12 May 2021 06:36:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230109AbhELGhg (ORCPT ); Wed, 12 May 2021 02:37:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229654AbhELGhf (ORCPT ); Wed, 12 May 2021 02:37:35 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62D8FC06174A for ; Tue, 11 May 2021 23:36:27 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id n2so33298599ejy.7 for ; Tue, 11 May 2021 23:36:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=nevGWaMjb5PeAfV1/F7svJNtl2lKO/LKnPavtCONiAI=; b=HPpOr4WJvmIPXKYS68buFhoAp5Li17j7jKX7/p4MM8Jdc8zp3Afy+9QrHlxyMLkqIl W0fRFCLAdUeZBL3gi7PbgBPQ2F0hcFhKcEsEbfTfQvBERFdKM/18nGInFsl/X0bSoMrR nR9pIlJU1StFIq8JAetJztmRo3A6V63sHQnOOaWpliocMXgE0ELlocl9ycD4j9pn7JFr 3n0uEjA7UdCX+6oI3KKWzREefFEM0X5ZRtOwXAlMHKHKa1Cb2PUkuaNhhHeMUmQctqYU ZdY5BRWrjlO0ZlELbBdtQu9YnCkrzUMTOZOQtTedilA/k5K62kSLy1DVIUepVg5shp51 ItYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=nevGWaMjb5PeAfV1/F7svJNtl2lKO/LKnPavtCONiAI=; b=pCvCzBD0jMUNcPhODrW8X87YsLC2E2bjPI0P2N+0QrwPiGQzcJnhw25jhEtgBa+qvz LU7TeK39iiOq+g+XDwvP9L92pUXZ0JH67tFhUNCJQFbFneiImxaNCb5iNvdogCmtwEoI TTnAfcsjTGlwV0LGCTsXn02VLRMNjHMi0+IwKhw1eX7euk0sJIEkdv3Xj+i/vwyMN5BW /8GPSqnhNijg94kEzPY/2I5g6KpnS7sj07oOUFqaJDwqSaDaHgNX/PcH5sbHB5izHc/w DKBhFQ0dcslhDihZNXAujxGhUEHwehT60/OUUQtQp2I+yzdt1ud4f3KRMYzHF6gcbN8b UHqw== X-Gm-Message-State: AOAM533QlGqIzOxbb4hho1XvDzUhn1YKleqwGJMAIARlmBLsnUVgZKD4 QoUzqrsfUoRxgKM3JVTvvCEYx1WnX0zpCJeO6FCA7Djs4YM= X-Google-Smtp-Source: ABdhPJxCxoEotHYSk6jU/Ap34pv984lwVWKfA4gMFHe/bD7fPEXF/C3Wo4s41aCcPA/bHiQZsSq+DtoYOWuPDgIL8kQ= X-Received: by 2002:a17:906:bc8e:: with SMTP id lv14mr35741607ejb.418.1620801386118; Tue, 11 May 2021 23:36:26 -0700 (PDT) MIME-Version: 1.0 References: <162042787450.1202325.5718541949681409566.stgit@dwillia2-desk3.amr.corp.intel.com> <162042791852.1202325.8197739881935753009.stgit@dwillia2-desk3.amr.corp.intel.com> <20210510162121.000042be@Huawei.com> In-Reply-To: <20210510162121.000042be@Huawei.com> From: Dan Williams Date: Tue, 11 May 2021 23:36:15 -0700 Message-ID: Subject: Re: [PATCH 7/8] cxl/port: Introduce cxl_port objects To: Jonathan Cameron Cc: linux-cxl@vger.kernel.org, Linux PCI , Linux Kernel Mailing List , Linux ACPI Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org On Mon, May 10, 2021 at 8:23 AM Jonathan Cameron wrote: > > On Fri, 7 May 2021 15:51:58 -0700 > Dan Williams wrote: > > > Once the cxl_root is established then other ports in the hierarchy can > > be attached. The cxl_port object, unlike cxl_root that is associated > > with host bridges, is associated with PCIe Root Ports or PCIe Switch > > Ports. Add cxl_port instances for all PCIe Root Ports in an ACPI0016 > > host bridge. The cxl_port instances for PCIe Switch Ports are not > > included here as those are to be modeled as another service device > > registered on the pcie_port_bus_type. > > > > A sample sysfs topology for a single-host-bridge with > > single-PCIe/CXL-port follows: > > > > /sys/bus/cxl/devices/root0 > > =E2=94=9C=E2=94=80=E2=94=80 address_space0 > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 devtype > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 end > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 start > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 supports_ram > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 supports_type2 > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 supports_type3 > > =E2=94=82 =E2=94=94=E2=94=80=E2=94=80 uevent > > =E2=94=9C=E2=94=80=E2=94=80 address_space1 > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 devtype > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 end > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 start > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 supports_pmem > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 supports_type2 > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 supports_type3 > > =E2=94=82 =E2=94=94=E2=94=80=E2=94=80 uevent > > =E2=94=9C=E2=94=80=E2=94=80 devtype > > =E2=94=9C=E2=94=80=E2=94=80 port1 > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 devtype > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 host -> ../../../../LNXSYSTM:00= /LNXSYBUS:00/ACPI0016:00 > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 port2 > > =E2=94=82 =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 devtype > > =E2=94=82 =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 host -> ../../../..= /../pci0000:34/0000:34:00.0 > > =E2=94=82 =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 subsystem -> ../../= ../../../../bus/cxl > > =E2=94=82 =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 target_id > > =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80 uevent > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 subsystem -> ../../../../../bus= /cxl > > =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 target_id > > =E2=94=82 =E2=94=94=E2=94=80=E2=94=80 uevent > > =E2=94=9C=E2=94=80=E2=94=80 subsystem -> ../../../../bus/cxl > > =E2=94=9C=E2=94=80=E2=94=80 target_id > > =E2=94=94=E2=94=80=E2=94=80 uevent > > > > In this listing the system-wide-singleton root0 has 2 address spaces, 1 > > PMEM and 1 RAM. Those address spaces are accessed through port1 which > > represents the upstream port of an ACPI0016 host-bridge. A > > multi-host-bridge system would have other ports as peers to port1 to > > additionally decode root level address spaces. Port2 in this diagram > > represents the single downstream port of the host-bridge. Were it to be > > a multi-ported-host-bridge there would be peers / siblings of port2 wit= h > > port1 as their common ancestor. > > I guess it would be a pain to emulate a system that actually had > multiple ports at the last level. Pity as would have made your > explanation here a little easier to follow. > A pain in QEMU, but maybe not with a mocked implementation similar to what gets injected for the nvdimm "nfit_test". I'll take a look. > > The rationale for this port hierarchy is to be able to walk the HDM > > decoder register sets that each port implements. Additionally it > > provides a representation of host-bridge interleave which will be > > necessary for follow-on work that adds CXL region devices. > > > > The details in the /sys/bus/cxl hierarchy that are not suitable to be > > represented in the /sys/bus/pci hierarchy are: > > - memory address spaces that are interleaved across host bridges > > - common sub-device functionality represented by CXL component + device > > registers (enumerated via DVSEC or platform firmware (ACPI CEDT)). > > I'm sold :) Thanks for the vote of confidence. It sounded like Bjorn was sold too at the end of our last thread... I'll Cc him on this patch directly in the resend. > > > > > Signed-off-by: Dan Williams > > Reviewed-by: Jonathan Cameron Thanks for the review Jonathan, appreciate it.