[PATCH 01/16] remoteproc: q6v5-mss: fixup MSM8998 MSS out of reset sequence

[PATCH 01/16] remoteproc: q6v5-mss: fixup MSM8998 MSS out of reset sequence

[Sibi Sankar]

Fixup the following in the MSS out of reset sequence on MSM8998:
* skip ACC override on MSM8998.
* wait for BHS_EN_REST_ACK to be set before setting the LDO to bypass.
* remove "mem" clock from the active pool.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_mss.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 471128a2e7239..2becf6dade936 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -100,6 +100,11 @@
 #define QDSP6SS_XO_CBCR		0x0038
 #define QDSP6SS_ACC_OVERRIDE_VAL		0x20
 
+/* QDSP6v62 parameters */
+#define QDSP6SS_BHS_EN_REST_ACK		BIT(0)
+#define BHS_CHECK_MAX_LOOPS		200
+#define QDSP6SS_BHS_STATUS		0x0C4
+
 /* QDSP6v65 parameters */
 #define QDSP6SS_SLEEP                   0x3C
 #define QDSP6SS_BOOT_CORE_START         0x400
@@ -505,8 +510,9 @@ static int q6v5proc_reset(struct q6v5 *qproc)
 		int mem_pwr_ctl;
 
 		/* Override the ACC value if required */
-		writel(QDSP6SS_ACC_OVERRIDE_VAL,
-		       qproc->reg_base + QDSP6SS_STRAP_ACC);
+		if (qproc->version == MSS_MSM8996)
+			writel(QDSP6SS_ACC_OVERRIDE_VAL,
+			       qproc->reg_base + QDSP6SS_STRAP_ACC);
 
 		/* Assert resets, stop core */
 		val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
@@ -534,6 +540,18 @@ static int q6v5proc_reset(struct q6v5 *qproc)
 		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 		udelay(1);
 
+		/* wait for BHS_EN_REST_ACK to be set */
+		if (qproc->version == MSS_MSM8998) {
+			ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BHS_STATUS,
+						 val, (val & QDSP6SS_BHS_EN_REST_ACK),
+						 1, BHS_CHECK_MAX_LOOPS);
+			if (ret) {
+				dev_err(qproc->dev,
+					"QDSP6SS_BHS_EN_REST_ACK timedout\n");
+				return -ETIMEDOUT;
+			}
+		}
+
 		/* Put LDO in bypass mode */
 		val |= QDSP6v56_LDO_BYP;
 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
@@ -1594,7 +1612,6 @@ static const struct rproc_hexagon_res msm8998_mss = {
 	.active_clk_names = (char*[]){
 			"iface",
 			"bus",
-			"mem",
 			"gpll0_mss",
 			"mnoc_axi",
 			"snoc_axi",
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 02/16] remoteproc: q6v5-mss: Streamline the MSS out of reset sequence

[Sibi Sankar]

Streamline the MSS out of reset sequence to reuse common code across
MSM8998/MSM8996/MSM8974/MSM8916 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_mss.c | 94 ++++++++++++++++--------------
 1 file changed, 51 insertions(+), 43 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 2becf6dade936..06a57db3238db 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -505,21 +505,21 @@ static int q6v5proc_reset(struct q6v5 *qproc)
 		}
 
 		goto pbl_wait;
-	} else if (qproc->version == MSS_MSM8996 ||
-		   qproc->version == MSS_MSM8998) {
-		int mem_pwr_ctl;
+	}
 
-		/* Override the ACC value if required */
-		if (qproc->version == MSS_MSM8996)
-			writel(QDSP6SS_ACC_OVERRIDE_VAL,
-			       qproc->reg_base + QDSP6SS_STRAP_ACC);
+	/* Override the ACC value if required */
+	if (qproc->version == MSS_MSM8996)
+		writel(QDSP6SS_ACC_OVERRIDE_VAL,
+		       qproc->reg_base + QDSP6SS_STRAP_ACC);
 
-		/* Assert resets, stop core */
-		val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
-		val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
-		writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+	/* Assert resets, stop core */
+	val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
+	val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
+	writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 
-		/* BHS require xo cbcr to be enabled */
+	/* BHS require xo cbcr to be enabled */
+	if (qproc->version == MSS_MSM8996 ||
+	    qproc->version == MSS_MSM8998) {
 		val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 		val |= 0x1;
 		writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
@@ -533,26 +533,35 @@ static int q6v5proc_reset(struct q6v5 *qproc)
 				"xo cbcr enabling timed out (rc:%d)\n", ret);
 			return ret;
 		}
-		/* Enable power block headswitch and wait for it to stabilize */
-		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+	}
+
+	/* Enable power block headswitch and wait for it to stabilize */
+	val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+	if (qproc->version == MSS_MSM8996 ||
+	    qproc->version == MSS_MSM8998)
 		val |= QDSP6v56_BHS_ON;
-		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-		udelay(1);
-
-		/* wait for BHS_EN_REST_ACK to be set */
-		if (qproc->version == MSS_MSM8998) {
-			ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BHS_STATUS,
-						 val, (val & QDSP6SS_BHS_EN_REST_ACK),
-						 1, BHS_CHECK_MAX_LOOPS);
-			if (ret) {
-				dev_err(qproc->dev,
-					"QDSP6SS_BHS_EN_REST_ACK timedout\n");
-				return -ETIMEDOUT;
-			}
+	else
+		val |= QDSS_BHS_ON | QDSS_LDO_BYP;
+	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+	val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+	udelay(1);
+
+	/* wait for BHS_EN_REST_ACK to be set */
+	if (qproc->version == MSS_MSM8998) {
+		ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BHS_STATUS,
+					 val, (val & QDSP6SS_BHS_EN_REST_ACK),
+					 1, BHS_CHECK_MAX_LOOPS);
+		if (ret) {
+			dev_err(qproc->dev,
+				"QDSP6SS_BHS_EN_REST_ACK timedout\n");
+			return -ETIMEDOUT;
 		}
+	}
 
+	if (qproc->version == MSS_MSM8996 ||
+	    qproc->version == MSS_MSM8998) {
 		/* Put LDO in bypass mode */
+		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 		val |= QDSP6v56_LDO_BYP;
 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 
@@ -564,7 +573,11 @@ static int q6v5proc_reset(struct q6v5 *qproc)
 		/* Deassert memory peripheral sleep and L2 memory standby */
 		val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+	}
 
+	/* Turn on memories */
+	if (qproc->version == MSS_MSM8996 || qproc->version == MSS_MSM8998) {
+		int mem_pwr_ctl;
 		/* Turn on L1, L2, ETB and JU memories 1 at a time */
 		if (qproc->version == MSS_MSM8996) {
 			mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
@@ -586,22 +599,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
 			val |= readl(qproc->reg_base + mem_pwr_ctl);
 			udelay(1);
 		}
-		/* Remove word line clamp */
-		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-		val &= ~QDSP6v56_CLAMP_WL;
-		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 	} else {
-		/* Assert resets, stop core */
-		val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
-		val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
-		writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
-
-		/* Enable power block headswitch and wait for it to stabilize */
-		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-		val |= QDSS_BHS_ON | QDSS_LDO_BYP;
-		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-		udelay(1);
 		/*
 		 * Turn on memories. L2 banks should be done individually
 		 * to minimize inrush current.
@@ -617,7 +615,17 @@ static int q6v5proc_reset(struct q6v5 *qproc)
 		val |= Q6SS_L2DATA_SLP_NRET_N_0;
 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 	}
+
+	/* Remove word line clamp */
+	if (qproc->version == MSS_MSM8996 ||
+	    qproc->version == MSS_MSM8998) {
+		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		val &= ~QDSP6v56_CLAMP_WL;
+		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+	}
+
 	/* Remove IO clamp */
+	val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 	val &= ~Q6SS_CLAMP_IO;
 	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 03/16] dt-bindings: remoteproc: qcom: Add Q6V5 Modem PIL binding for SC7180

[Sibi Sankar]

Add a new modem compatible string for Qualcomm SC7180 SoCs and introduce
the "qcom,halt-nav-regs" bindings needed by the modem sub-system running
on SC7180 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 .../bindings/remoteproc/qcom,q6v5.txt         | 23 +++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index c416746f93cfd..88dfa3fc15f78 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -13,6 +13,7 @@ on the Qualcomm Hexagon core.
 		    "qcom,msm8974-mss-pil"
 		    "qcom,msm8996-mss-pil"
 		    "qcom,msm8998-mss-pil"
+		    "qcom,sc7180-mss-pil"
 		    "qcom,sdm845-mss-pil"
 
 - reg:
@@ -43,6 +44,7 @@ on the Qualcomm Hexagon core.
 		    must be "wdog", "fatal", "ready", "handover", "stop-ack"
 	qcom,msm8996-mss-pil:
 	qcom,msm8998-mss-pil:
+	qcom,sc7180-mss-pil:
 	qcom,sdm845-mss-pil:
 		    must be "wdog", "fatal", "ready", "handover", "stop-ack",
 		    "shutdown-ack"
@@ -75,6 +77,9 @@ on the Qualcomm Hexagon core.
 	qcom,msm8998-mss-pil:
 		    must be "iface", "bus", "mem", "xo", "gpll0_mss",
 		    "snoc_axi", "mnoc_axi", "qdss"
+	qcom,sc7180-mss-pil:
+		    must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi",
+		    "mss_crypto", "mss_nav", "nav"
 	qcom,sdm845-mss-pil:
 		    must be "iface", "bus", "mem", "xo", "gpll0_mss",
 		    "snoc_axi", "mnoc_axi", "prng"
@@ -86,7 +91,7 @@ on the Qualcomm Hexagon core.
 		    reference to the list of 3 reset-controllers for the
 		    wcss sub-system
 		    reference to the list of 2 reset-controllers for the modem
-		    sub-system on SDM845 SoCs
+		    sub-system on SC7180, SDM845 SoCs
 
 - reset-names:
 	Usage: required
@@ -95,7 +100,7 @@ on the Qualcomm Hexagon core.
 		    must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
 		    for the wcss sub-system
 		    must be "mss_restart", "pdc_reset" for the modem
-		    sub-system on SDM845 SoCs
+		    sub-system on SC7180, SDM845 SoCs
 
 For the compatible strings below the following supplies are required:
   "qcom,q6v5-pil"
@@ -144,6 +149,7 @@ For the compatible string below the following supplies are required:
 	qcom,msm8996-mss-pil:
 	qcom,msm8998-mss-pil:
 		    must be "cx", "mx"
+	qcom,sc7180-mss-pil:
 	qcom,sdm845-mss-pil:
 		    must be "cx", "mx", "mss", "load_state"
 
@@ -165,6 +171,19 @@ For the compatible string below the following supplies are required:
 		    by the three offsets within syscon for q6, modem and nc
 		    halt registers.
 
+For the compatible strings below the following phandle references are required:
+  "qcom,sc7180-mss-pil"
+- qcom,halt-nav-regs:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: reference to a list of 2 phandles with one offset each for
+		    the modem sub-system running on SC7180 SoC. The first
+		    phandle reference is to the mss clock node followed by the
+		    offset within register space for nav halt register. The
+		    second phandle reference is to a syscon representing TCSR
+		    followed by the offset within syscon for conn_box_spare0
+		    register.
+
 = SUBNODES:
 The Hexagon node must contain two subnodes, named "mba" and "mpss" representing
 the memory regions used by the Hexagon firmware. Each sub-node must contain:
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 04/16] remoteproc: mss: q6v5-mss: Add modem support on SC7180

[Sibi Sankar]

Add the out of reset sequence support for modem sub-system on SC7180
SoCs. It is closer to the modem sub-system found on SDM845 SoCs. It
requires access to an additional halt nav register to put the modem
back into reset.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_mss.c | 179 ++++++++++++++++++++++++++++-
 1 file changed, 175 insertions(+), 4 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 06a57db3238db..b01ed02d9cc02 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -68,6 +68,9 @@
 #define AXI_HALTREQ_REG			0x0
 #define AXI_HALTACK_REG			0x4
 #define AXI_IDLE_REG			0x8
+#define NAV_AXI_HALTREQ_BIT		BIT(0)
+#define NAV_AXI_HALTACK_BIT		BIT(1)
+#define NAV_AXI_IDLE_BIT		BIT(2)
 
 #define HALT_ACK_TIMEOUT_MS		100
 
@@ -106,9 +109,11 @@
 #define QDSP6SS_BHS_STATUS		0x0C4
 
 /* QDSP6v65 parameters */
+#define QDSP6SS_CORE_CBCR		0x20
 #define QDSP6SS_SLEEP                   0x3C
 #define QDSP6SS_BOOT_CORE_START         0x400
 #define QDSP6SS_BOOT_CMD                0x404
+#define QDSP6SS_BOOT_STATUS		0x408
 #define SLEEP_CHECK_MAX_LOOPS           200
 #define BOOT_FSM_TIMEOUT                10000
 
@@ -136,6 +141,7 @@ struct rproc_hexagon_res {
 	int version;
 	bool need_mem_protection;
 	bool has_alt_reset;
+	bool has_halt_nav;
 };
 
 struct q6v5 {
@@ -146,9 +152,14 @@ struct q6v5 {
 	void __iomem *rmb_base;
 
 	struct regmap *halt_map;
+	struct regmap *halt_nav_map;
+	struct regmap *conn_map;
+
 	u32 halt_q6;
 	u32 halt_modem;
 	u32 halt_nc;
+	u32 halt_nav;
+	u32 conn_box;
 
 	struct reset_control *mss_restart;
 	struct reset_control *pdc_reset;
@@ -192,6 +203,7 @@ struct q6v5 {
 	struct qcom_sysmon *sysmon;
 	bool need_mem_protection;
 	bool has_alt_reset;
+	bool has_halt_nav;
 	int mpss_perm;
 	int mba_perm;
 	const char *hexagon_mdt_image;
@@ -203,6 +215,7 @@ enum {
 	MSS_MSM8974,
 	MSS_MSM8996,
 	MSS_MSM8998,
+	MSS_SC7180,
 	MSS_SDM845,
 };
 
@@ -401,6 +414,18 @@ static int q6v5_reset_assert(struct q6v5 *qproc)
 		reset_control_assert(qproc->pdc_reset);
 		ret = reset_control_reset(qproc->mss_restart);
 		reset_control_deassert(qproc->pdc_reset);
+	} else if (qproc->has_halt_nav) {
+		reset_control_assert(qproc->pdc_reset);
+		/* SWAR using conn_box_spare0 register for pipeline glitch */
+		regmap_update_bits(qproc->conn_map, qproc->conn_box,
+				   BIT(0), BIT(0));
+		regmap_update_bits(qproc->halt_nav_map, qproc->halt_nav,
+				   NAV_AXI_HALTREQ_BIT, 0);
+		reset_control_assert(qproc->mss_restart);
+		reset_control_deassert(qproc->pdc_reset);
+		regmap_update_bits(qproc->conn_map, qproc->conn_box,
+				   BIT(0), 0);
+		ret = reset_control_deassert(qproc->mss_restart);
 	} else {
 		ret = reset_control_assert(qproc->mss_restart);
 	}
@@ -418,6 +443,8 @@ static int q6v5_reset_deassert(struct q6v5 *qproc)
 		ret = reset_control_reset(qproc->mss_restart);
 		writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
 		reset_control_deassert(qproc->pdc_reset);
+	} else if (qproc->has_halt_nav) {
+		ret = reset_control_reset(qproc->mss_restart);
 	} else {
 		ret = reset_control_deassert(qproc->mss_restart);
 	}
@@ -477,7 +504,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
 	int ret;
 	int i;
 
-	if (qproc->version == MSS_SDM845) {
+	if (qproc->version == MSS_SDM845 || qproc->version == MSS_SC7180) {
 		val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 		val |= 0x1;
 		writel(val, qproc->reg_base + QDSP6SS_SLEEP);
@@ -490,13 +517,36 @@ static int q6v5proc_reset(struct q6v5 *qproc)
 			return -ETIMEDOUT;
 		}
 
+		if (qproc->version == MSS_SC7180) {
+			val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
+			val |= 0x1;
+			writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
+
+			ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
+						 val, !(val & BIT(31)), 1,
+						 SLEEP_CHECK_MAX_LOOPS);
+			if (ret) {
+				dev_err(qproc->dev, "QDSP6SS Xo clock timed out\n");
+				return -ETIMEDOUT;
+			}
+
+			val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
+			val |= 0x1;
+			writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
+		}
+
 		/* De-assert QDSP6 stop core */
 		writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 		/* Trigger boot FSM */
 		writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 
-		ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
-				val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
+		if (qproc->version == MSS_SC7180)
+			ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BOOT_STATUS,
+						 val, (val & BIT(0)) != 0, 1, SLEEP_CHECK_MAX_LOOPS);
+		else
+			ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
+						 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
+
 		if (ret) {
 			dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 			/* Reset the modem so that boot FSM is in reset state */
@@ -693,6 +743,38 @@ static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
 	regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
 }
 
+static void q6v5proc_halt_nav_axi_port(struct q6v5 *qproc,
+				       struct regmap *halt_map,
+				       u32 offset)
+{
+	unsigned long timeout;
+	unsigned int val;
+	int ret;
+
+	/* Check if we're already idle */
+	ret = regmap_read(halt_map, offset, &val);
+	if (!ret && (val & NAV_AXI_IDLE_BIT))
+		return;
+
+	/* Assert halt request */
+	regmap_update_bits(halt_map, offset, NAV_AXI_HALTREQ_BIT,
+			   NAV_AXI_HALTREQ_BIT);
+
+	/* Wait for halt ack*/
+	timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
+	for (;;) {
+		ret = regmap_read(halt_map, offset, &val);
+		if (ret || (val & NAV_AXI_HALTACK_BIT) || time_after(jiffies, timeout))
+			break;
+
+		msleep(5);
+	}
+
+	ret = regmap_read(halt_map, offset, &val);
+	if (ret || !(val & NAV_AXI_IDLE_BIT))
+		dev_err(qproc->dev, "port failed halt\n");
+}
+
 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
 {
 	unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
@@ -855,6 +937,9 @@ static int q6v5_mba_load(struct q6v5 *qproc)
 halt_axi_ports:
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
+	if (qproc->has_halt_nav)
+		q6v5proc_halt_nav_axi_port(qproc, qproc->halt_nav_map,
+					   qproc->halt_nav);
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 
 reclaim_mba:
@@ -902,6 +987,9 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
 
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
+	if (qproc->has_halt_nav)
+		q6v5proc_halt_nav_axi_port(qproc, qproc->halt_nav_map,
+					   qproc->halt_nav);
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 	if (qproc->version == MSS_MSM8996) {
 		/*
@@ -1279,6 +1367,47 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
 	qproc->halt_modem = args.args[1];
 	qproc->halt_nc = args.args[2];
 
+	if (qproc->has_halt_nav) {
+		struct platform_device *nav_pdev;
+
+		ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+						       "qcom,halt-nav-regs",
+						       1, 0, &args);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "failed to parse halt-nav-regs\n");
+			return -EINVAL;
+		}
+
+		nav_pdev = of_find_device_by_node(args.np);
+		of_node_put(args.np);
+		if (!nav_pdev) {
+			dev_err(&pdev->dev, "failed to get mss clock device\n");
+			return -EPROBE_DEFER;
+		}
+
+		qproc->halt_nav_map = dev_get_regmap(&nav_pdev->dev, NULL);
+		if (!qproc->halt_nav_map) {
+			dev_err(&pdev->dev, "failed to get map from device\n");
+			return -EINVAL;
+		}
+		qproc->halt_nav = args.args[0];
+
+		ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+						       "qcom,halt-nav-regs",
+						       1, 1, &args);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "failed to parse halt-nav-regs\n");
+			return -EINVAL;
+		}
+
+		qproc->conn_map = syscon_node_to_regmap(args.np);
+		of_node_put(args.np);
+		if (IS_ERR(qproc->conn_map))
+			return PTR_ERR(qproc->conn_map);
+
+		qproc->conn_box = args.args[0];
+	}
+
 	return 0;
 }
 
@@ -1353,7 +1482,7 @@ static int q6v5_init_reset(struct q6v5 *qproc)
 		return PTR_ERR(qproc->mss_restart);
 	}
 
-	if (qproc->has_alt_reset) {
+	if (qproc->has_alt_reset || qproc->has_halt_nav) {
 		qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
 								    "pdc_reset");
 		if (IS_ERR(qproc->pdc_reset)) {
@@ -1452,6 +1581,7 @@ static int q6v5_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, qproc);
 
+	qproc->has_halt_nav = desc->has_halt_nav;
 	ret = q6v5_init_mem(qproc, pdev);
 	if (ret)
 		goto free_rproc;
@@ -1575,6 +1705,41 @@ static int q6v5_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct rproc_hexagon_res sc7180_mss = {
+	.hexagon_mba_image = "mba.mbn",
+	.proxy_clk_names = (char*[]){
+		"xo",
+		NULL
+	},
+	.reset_clk_names = (char*[]){
+		"iface",
+		"bus",
+		"snoc_axi",
+		NULL
+	},
+	.active_clk_names = (char*[]){
+		"mnoc_axi",
+		"nav",
+		"mss_nav",
+		"mss_crypto",
+		NULL
+	},
+	.active_pd_names = (char*[]){
+		"load_state",
+		NULL
+	},
+	.proxy_pd_names = (char*[]){
+		"cx",
+		"mx",
+		"mss",
+		NULL
+	},
+	.need_mem_protection = true,
+	.has_alt_reset = false,
+	.has_halt_nav = true,
+	.version = MSS_SC7180,
+};
+
 static const struct rproc_hexagon_res sdm845_mss = {
 	.hexagon_mba_image = "mba.mbn",
 	.proxy_clk_names = (char*[]){
@@ -1606,6 +1771,7 @@ static const struct rproc_hexagon_res sdm845_mss = {
 	},
 	.need_mem_protection = true,
 	.has_alt_reset = true,
+	.has_halt_nav = false,
 	.version = MSS_SDM845,
 };
 
@@ -1632,6 +1798,7 @@ static const struct rproc_hexagon_res msm8998_mss = {
 	},
 	.need_mem_protection = true,
 	.has_alt_reset = false,
+	.has_halt_nav = false,
 	.version = MSS_MSM8998,
 };
 
@@ -1661,6 +1828,7 @@ static const struct rproc_hexagon_res msm8996_mss = {
 	},
 	.need_mem_protection = true,
 	.has_alt_reset = false,
+	.has_halt_nav = false,
 	.version = MSS_MSM8996,
 };
 
@@ -1693,6 +1861,7 @@ static const struct rproc_hexagon_res msm8916_mss = {
 	},
 	.need_mem_protection = false,
 	.has_alt_reset = false,
+	.has_halt_nav = false,
 	.version = MSS_MSM8916,
 };
 
@@ -1733,6 +1902,7 @@ static const struct rproc_hexagon_res msm8974_mss = {
 	},
 	.need_mem_protection = false,
 	.has_alt_reset = false,
+	.has_halt_nav = false,
 	.version = MSS_MSM8974,
 };
 
@@ -1742,6 +1912,7 @@ static const struct of_device_id q6v5_of_match[] = {
 	{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
 	{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
 	{ .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
+	{ .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
 	{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
 	{ },
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 05/16] remoteproc: qcom: pas: Disable interrupt on clock enable failure

[Sibi Sankar]

Disable handover smp2p interrupt on "xo" clock prepare enable failure.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pas.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index db4b3c4bacd77..0fdd3748398aa 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -86,7 +86,7 @@ static int adsp_start(struct rproc *rproc)
 
 	ret = clk_prepare_enable(adsp->xo);
 	if (ret)
-		return ret;
+		goto disable_irqs;
 
 	ret = clk_prepare_enable(adsp->aggre2_clk);
 	if (ret)
@@ -124,6 +124,8 @@ static int adsp_start(struct rproc *rproc)
 	clk_disable_unprepare(adsp->aggre2_clk);
 disable_xo_clk:
 	clk_disable_unprepare(adsp->xo);
+disable_irqs:
+	qcom_q6v5_unprepare(&adsp->q6v5);
 
 	return ret;
 }
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 06/16] dt-bindings: remoteproc: qcom: Add power-domain bindings for Q6V5 PAS

[Sibi Sankar]

Add power-domain bindings for Q6V5 PAS on MSM8974/MSM8996/QCS404/SDM845
SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 .../bindings/remoteproc/qcom,adsp.txt         | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
index 292dfda9770d7..fea25b8b050ed 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
@@ -67,6 +67,29 @@ on the Qualcomm ADSP Hexagon core.
 	Definition: reference to the px regulator to be held on behalf of the
 		    booting Hexagon core
 
+- power-domains:
+	Usage: required
+	Value type: <phandle>
+	Definition: reference to power-domains that match the power-domain-names
+
+- power-domain-names:
+	Usage: required
+	Value type: <stringlist>
+	Definition: The power-domains needed depend on the compatible string:
+	qcom,msm8974-adsp-pil:
+	qcom,msm8996-adsp-pil:
+		    must be "cx"
+	qcom,msm8996-slpi-pil:
+		    must be "ss_cx"
+	qcom,qcs404-adsp-pas:
+		    must be "lpi_cx"
+	qcom,qcs404-cdsp-pas:
+	qcom,qcs404-wcss-pas:
+		    must be "mx"
+	qcom,sdm845-adsp-pas:
+	qcom,sdm845-cdsp-pas:
+		    must be "cx", "load_state"
+
 - memory-region:
 	Usage: required
 	Value type: <phandle>
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 07/16] remoteproc: qcom: pas: Vote for active/proxy power domains

[Sibi Sankar]

On SM8150 SoCs ADSP, CDSP and MPSS need to proxy vote on multiple
rpmh ARC resources and active vote on QMP AOSS Power domains. Add
support to vote for multiple active and proxy power domains.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pas.c | 137 ++++++++++++++++++++++++++++-
 1 file changed, 133 insertions(+), 4 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 0fdd3748398aa..b60cca093400a 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -15,6 +15,8 @@
 #include <linux/of_address.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
 #include <linux/qcom_scm.h>
 #include <linux/regulator/consumer.h>
 #include <linux/remoteproc.h>
@@ -32,6 +34,9 @@ struct adsp_data {
 	int pas_id;
 	bool has_aggre2_clk;
 
+	char **active_pd_names;
+	char **proxy_pd_names;
+
 	const char *ssr_name;
 	const char *sysmon_name;
 	int ssctl_id;
@@ -49,6 +54,12 @@ struct qcom_adsp {
 	struct regulator *cx_supply;
 	struct regulator *px_supply;
 
+	struct device *active_pds[1];
+	struct device *proxy_pds[3];
+
+	int active_pd_count;
+	int proxy_pd_count;
+
 	int pas_id;
 	int crash_reason_smem;
 	bool has_aggre2_clk;
@@ -67,6 +78,41 @@ struct qcom_adsp {
 	struct qcom_sysmon *sysmon;
 };
 
+static int adsp_pds_enable(struct qcom_adsp *adsp, struct device **pds,
+			   size_t pd_count)
+{
+	int ret;
+	int i;
+
+	for (i = 0; i < pd_count; i++) {
+		dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
+		ret = pm_runtime_get_sync(pds[i]);
+		if (ret < 0)
+			goto unroll_pd_votes;
+	}
+
+	return 0;
+
+unroll_pd_votes:
+	for (i--; i >= 0; i--) {
+		dev_pm_genpd_set_performance_state(pds[i], 0);
+		pm_runtime_put(pds[i]);
+	}
+
+	return ret;
+};
+
+static void adsp_pds_disable(struct qcom_adsp *adsp, struct device **pds,
+			     size_t pd_count)
+{
+	int i;
+
+	for (i = 0; i < pd_count; i++) {
+		dev_pm_genpd_set_performance_state(pds[i], 0);
+		pm_runtime_put(pds[i]);
+	}
+}
+
 static int adsp_load(struct rproc *rproc, const struct firmware *fw)
 {
 	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
@@ -84,9 +130,17 @@ static int adsp_start(struct rproc *rproc)
 
 	qcom_q6v5_prepare(&adsp->q6v5);
 
+	ret = adsp_pds_enable(adsp, adsp->active_pds, adsp->active_pd_count);
+	if (ret < 0)
+		goto disable_irqs;
+
+	ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
+	if (ret < 0)
+		goto disable_active_pds;
+
 	ret = clk_prepare_enable(adsp->xo);
 	if (ret)
-		goto disable_irqs;
+		goto disable_proxy_pds;
 
 	ret = clk_prepare_enable(adsp->aggre2_clk);
 	if (ret)
@@ -124,6 +178,10 @@ static int adsp_start(struct rproc *rproc)
 	clk_disable_unprepare(adsp->aggre2_clk);
 disable_xo_clk:
 	clk_disable_unprepare(adsp->xo);
+disable_proxy_pds:
+	adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
+disable_active_pds:
+	adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
 disable_irqs:
 	qcom_q6v5_unprepare(&adsp->q6v5);
 
@@ -138,6 +196,7 @@ static void qcom_pas_handover(struct qcom_q6v5 *q6v5)
 	regulator_disable(adsp->cx_supply);
 	clk_disable_unprepare(adsp->aggre2_clk);
 	clk_disable_unprepare(adsp->xo);
+	adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
 }
 
 static int adsp_stop(struct rproc *rproc)
@@ -154,6 +213,7 @@ static int adsp_stop(struct rproc *rproc)
 	if (ret)
 		dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
 
+	adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
 	handover = qcom_q6v5_unprepare(&adsp->q6v5);
 	if (handover)
 		qcom_pas_handover(&adsp->q6v5);
@@ -219,6 +279,59 @@ static int adsp_init_regulator(struct qcom_adsp *adsp)
 	return PTR_ERR_OR_ZERO(adsp->px_supply);
 }
 
+static int adsp_pds_attach(struct device *dev, struct device **devs,
+			   char **pd_names)
+{
+	size_t num_pds = 0;
+	int ret;
+	int i;
+
+	if (!pd_names)
+		return 0;
+
+	/* Handle single power domain */
+	if (dev->pm_domain) {
+		devs[0] = dev;
+		pm_runtime_enable(dev);
+		return 1;
+	}
+
+	while (pd_names[num_pds])
+		num_pds++;
+
+	for (i = 0; i < num_pds; i++) {
+		devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
+		if (IS_ERR_OR_NULL(devs[i])) {
+			ret = PTR_ERR(devs[i]) ? : -ENODATA;
+			goto unroll_attach;
+		}
+	}
+
+	return num_pds;
+
+unroll_attach:
+	for (i--; i >= 0; i--)
+		dev_pm_domain_detach(devs[i], false);
+
+	return ret;
+};
+
+static void adsp_pds_detach(struct qcom_adsp *adsp, struct device **pds,
+			    size_t pd_count)
+{
+	struct device *dev = adsp->dev;
+	int i;
+
+	/* Handle single power domain */
+	if (dev->pm_domain && pd_count) {
+		pm_runtime_disable(dev);
+		return;
+	}
+
+	for (i = 0; i < pd_count; i++)
+		dev_pm_domain_detach(pds[i], false);
+}
+
 static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
 {
 	struct device_node *node;
@@ -294,10 +407,22 @@ static int adsp_probe(struct platform_device *pdev)
 	if (ret)
 		goto free_rproc;
 
+	ret = adsp_pds_attach(&pdev->dev, adsp->active_pds,
+			      desc->active_pd_names);
+	if (ret < 0)
+		goto free_rproc;
+	adsp->active_pd_count = ret;
+
+	ret = adsp_pds_attach(&pdev->dev, adsp->proxy_pds,
+			      desc->proxy_pd_names);
+	if (ret < 0)
+		goto detach_active_pds;
+	adsp->proxy_pd_count = ret;
+
 	ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
 			     qcom_pas_handover);
 	if (ret)
-		goto free_rproc;
+		goto detach_proxy_pds;
 
 	qcom_add_glink_subdev(rproc, &adsp->glink_subdev);
 	qcom_add_smd_subdev(rproc, &adsp->smd_subdev);
@@ -307,15 +432,19 @@ static int adsp_probe(struct platform_device *pdev)
 					      desc->ssctl_id);
 	if (IS_ERR(adsp->sysmon)) {
 		ret = PTR_ERR(adsp->sysmon);
-		goto free_rproc;
+		goto detach_proxy_pds;
 	}
 
 	ret = rproc_add(rproc);
 	if (ret)
-		goto free_rproc;
+		goto detach_proxy_pds;
 
 	return 0;
 
+detach_proxy_pds:
+	adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
+detach_active_pds:
+	adsp_pds_detach(adsp, adsp->active_pds, adsp->active_pd_count);
 free_rproc:
 	rproc_free(rproc);
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 08/16] dt-bindings: remoteproc: qcom: Add ADSP and SLPI support for MSM8998 SoC

[Sibi Sankar]

Add ADSP and SLPI compatibles for MSM8998 SoC.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
index fea25b8b050ed..34dc1d94a78c7 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
@@ -10,6 +10,8 @@ on the Qualcomm ADSP Hexagon core.
 		    "qcom,msm8974-adsp-pil"
 		    "qcom,msm8996-adsp-pil"
 		    "qcom,msm8996-slpi-pil"
+		    "qcom,msm8998-adsp-pas"
+		    "qcom,msm8998-slpi-pas"
 		    "qcom,qcs404-adsp-pas"
 		    "qcom,qcs404-cdsp-pas"
 		    "qcom,qcs404-wcss-pas"
@@ -29,6 +31,8 @@ on the Qualcomm ADSP Hexagon core.
 	qcom,msm8974-adsp-pil:
 	qcom,msm8996-adsp-pil:
 	qcom,msm8996-slpi-pil:
+	qcom,msm8998-adsp-pas:
+	qcom,msm8998-slpi-pas:
 	qcom,qcs404-adsp-pas:
 	qcom,qcs404-cdsp-pas:
 	qcom,sdm845-adsp-pas:
@@ -78,9 +82,12 @@ on the Qualcomm ADSP Hexagon core.
 	Definition: The power-domains needed depend on the compatible string:
 	qcom,msm8974-adsp-pil:
 	qcom,msm8996-adsp-pil:
+	qcom,msm8998-adsp-pas:
 		    must be "cx"
 	qcom,msm8996-slpi-pil:
 		    must be "ss_cx"
+	qcom,msm8998-slpi-pas:
+		    must be "ssc_cx"
 	qcom,qcs404-adsp-pas:
 		    must be "lpi_cx"
 	qcom,qcs404-cdsp-pas:
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 09/16] remoteproc: qcom: pas: Add MSM8998 ADSP and SLPI support

[Sibi Sankar]

Add support for booting the Audio and Sensor DSPs found in
Qualcomm's MSM8998 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pas.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index b60cca093400a..2dd693d443ca8 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -476,6 +476,20 @@ static const struct adsp_data adsp_resource_init = {
 		.ssctl_id = 0x14,
 };
 
+static const struct adsp_data msm8998_adsp_resource = {
+		.crash_reason_smem = 423,
+		.firmware_name = "adsp.mdt",
+		.pas_id = 1,
+		.has_aggre2_clk = false,
+		.proxy_pd_names = (char*[]){
+			"cx",
+			NULL
+		},
+		.ssr_name = "lpass",
+		.sysmon_name = "adsp",
+		.ssctl_id = 0x14,
+};
+
 static const struct adsp_data cdsp_resource_init = {
 	.crash_reason_smem = 601,
 	.firmware_name = "cdsp.mdt",
@@ -496,6 +510,20 @@ static const struct adsp_data slpi_resource_init = {
 		.ssctl_id = 0x16,
 };
 
+static const struct adsp_data msm8998_slpi_resource = {
+		.crash_reason_smem = 424,
+		.firmware_name = "slpi.mdt",
+		.pas_id = 12,
+		.has_aggre2_clk = true,
+		.proxy_pd_names = (char*[]){
+			"ssc_cx",
+			NULL
+		},
+		.ssr_name = "dsps",
+		.sysmon_name = "slpi",
+		.ssctl_id = 0x16,
+};
+
 static const struct adsp_data wcss_resource_init = {
 	.crash_reason_smem = 421,
 	.firmware_name = "wcnss.mdt",
@@ -509,6 +537,8 @@ static const struct of_device_id adsp_of_match[] = {
 	{ .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init},
 	{ .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init},
 	{ .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init},
+	{ .compatible = "qcom,msm8998-adsp-pas", .data = &msm8998_adsp_resource},
+	{ .compatible = "qcom,msm8998-slpi-pas", .data = &msm8998_slpi_resource},
 	{ .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
 	{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
 	{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 10/16] dt-bindings: remoteproc: qcom: SM8150 Add ADSP, CDSP, MPSS and SLPI support

[Sibi Sankar]

Add ADSP, CDSP, MPSS and SLPI compatibles for SM8150 SoC.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 .../devicetree/bindings/remoteproc/qcom,adsp.txt   | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
index 34dc1d94a78c7..9938918b2fea3 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
@@ -17,6 +17,10 @@ on the Qualcomm ADSP Hexagon core.
 		    "qcom,qcs404-wcss-pas"
 		    "qcom,sdm845-adsp-pas"
 		    "qcom,sdm845-cdsp-pas"
+		    "qcom,sm8150-adsp-pas"
+		    "qcom,sm8150-cdsp-pas"
+		    "qcom,sm8150-mpss-pas"
+		    "qcom,sm8150-slpi-pas"
 
 - interrupts-extended:
 	Usage: required
@@ -37,8 +41,12 @@ on the Qualcomm ADSP Hexagon core.
 	qcom,qcs404-cdsp-pas:
 	qcom,sdm845-adsp-pas:
 	qcom,sdm845-cdsp-pas:
+	qcom,sm8150-adsp-pas:
+	qcom,sm8150-cdsp-pas:
+	qcom,sm8150-slpi-pas:
 		    must be "wdog", "fatal", "ready", "handover", "stop-ack"
 	qcom,qcs404-wcss-pas:
+	qcom,sm8150-mpss-pas:
 		    must be "wdog", "fatal", "ready", "handover", "stop-ack",
 		    "shutdown-ack"
 
@@ -95,7 +103,13 @@ on the Qualcomm ADSP Hexagon core.
 		    must be "mx"
 	qcom,sdm845-adsp-pas:
 	qcom,sdm845-cdsp-pas:
+	qcom,sm8150-adsp-pas:
+	qcom,sm8150-cdsp-pas:
 		    must be "cx", "load_state"
+	qcom,sm8150-mpss-pas:
+		    must be "cx", "load_state", "mss"
+	qcom,sm8150-slpi-pas:
+		    must be "lcx", "lmx", "load_state"
 
 - memory-region:
 	Usage: required
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 11/16] remoteproc: qcom: pas: Add SM8150 ADSP, CDSP, Modem and SLPI support

[Sibi Sankar]

Add support for booting the Modem, Audio, Compute and Sensor DSPs found on
Qualcomm's SM8150 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pas.c | 78 ++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 2dd693d443ca8..98e9336302844 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -490,6 +490,24 @@ static const struct adsp_data msm8998_adsp_resource = {
 		.ssctl_id = 0x14,
 };
 
+static const struct adsp_data sm8150_adsp_resource = {
+		.crash_reason_smem = 423,
+		.firmware_name = "adsp.mdt",
+		.pas_id = 1,
+		.has_aggre2_clk = false,
+		.active_pd_names = (char*[]){
+			"load_state",
+			NULL
+		},
+		.proxy_pd_names = (char*[]){
+			"cx",
+			NULL
+		},
+		.ssr_name = "lpass",
+		.sysmon_name = "adsp",
+		.ssctl_id = 0x14,
+};
+
 static const struct adsp_data cdsp_resource_init = {
 	.crash_reason_smem = 601,
 	.firmware_name = "cdsp.mdt",
@@ -500,6 +518,43 @@ static const struct adsp_data cdsp_resource_init = {
 	.ssctl_id = 0x17,
 };
 
+static const struct adsp_data sm8150_cdsp_resource = {
+	.crash_reason_smem = 601,
+	.firmware_name = "cdsp.mdt",
+	.pas_id = 18,
+	.has_aggre2_clk = false,
+	.active_pd_names = (char*[]){
+		"load_state",
+		NULL
+	},
+	.proxy_pd_names = (char*[]){
+		"cx",
+		NULL
+	},
+	.ssr_name = "cdsp",
+	.sysmon_name = "cdsp",
+	.ssctl_id = 0x17,
+};
+
+static const struct adsp_data mpss_resource_init = {
+	.crash_reason_smem = 421,
+	.firmware_name = "modem.mdt",
+	.pas_id = 4,
+	.has_aggre2_clk = false,
+	.active_pd_names = (char*[]){
+		"load_state",
+		NULL
+	},
+	.proxy_pd_names = (char*[]){
+		"cx",
+		"mss",
+		NULL
+	},
+	.ssr_name = "mpss",
+	.sysmon_name = "modem",
+	.ssctl_id = 0x12,
+};
+
 static const struct adsp_data slpi_resource_init = {
 		.crash_reason_smem = 424,
 		.firmware_name = "slpi.mdt",
@@ -524,6 +579,25 @@ static const struct adsp_data msm8998_slpi_resource = {
 		.ssctl_id = 0x16,
 };
 
+static const struct adsp_data sm8150_slpi_resource = {
+		.crash_reason_smem = 424,
+		.firmware_name = "slpi.mdt",
+		.pas_id = 12,
+		.has_aggre2_clk = false,
+		.active_pd_names = (char*[]){
+			"load_state",
+			NULL
+		},
+		.proxy_pd_names = (char*[]){
+			"lcx",
+			"lmx",
+			NULL
+		},
+		.ssr_name = "dsps",
+		.sysmon_name = "slpi",
+		.ssctl_id = 0x16,
+};
+
 static const struct adsp_data wcss_resource_init = {
 	.crash_reason_smem = 421,
 	.firmware_name = "wcnss.mdt",
@@ -544,6 +618,10 @@ static const struct of_device_id adsp_of_match[] = {
 	{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
 	{ .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
 	{ .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
+	{ .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource},
+	{ .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource},
+	{ .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init},
+	{ .compatible = "qcom,sm8150-slpi-pas", .data = &sm8150_slpi_resource},
 	{ },
 };
 MODULE_DEVICE_TABLE(of, adsp_of_match);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 12/16] remoteproc: qcom: pas: Add auto_boot flag

[Sibi Sankar]

Add auto_boot flag and set it to false for modem. This allows for
the delayed boot up of modem after the dependencies are met in
userspace.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pas.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 98e9336302844..b5b6aee6e54a3 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -33,6 +33,7 @@ struct adsp_data {
 	const char *firmware_name;
 	int pas_id;
 	bool has_aggre2_clk;
+	bool auto_boot;
 
 	char **active_pd_names;
 	char **proxy_pd_names;
@@ -388,6 +389,8 @@ static int adsp_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 
+	rproc->auto_boot = desc->auto_boot;
+
 	adsp = (struct qcom_adsp *)rproc->priv;
 	adsp->dev = &pdev->dev;
 	adsp->rproc = rproc;
@@ -471,6 +474,7 @@ static const struct adsp_data adsp_resource_init = {
 		.firmware_name = "adsp.mdt",
 		.pas_id = 1,
 		.has_aggre2_clk = false,
+		.auto_boot = true,
 		.ssr_name = "lpass",
 		.sysmon_name = "adsp",
 		.ssctl_id = 0x14,
@@ -481,6 +485,7 @@ static const struct adsp_data msm8998_adsp_resource = {
 		.firmware_name = "adsp.mdt",
 		.pas_id = 1,
 		.has_aggre2_clk = false,
+		.auto_boot = true,
 		.proxy_pd_names = (char*[]){
 			"cx",
 			NULL
@@ -495,6 +500,7 @@ static const struct adsp_data sm8150_adsp_resource = {
 		.firmware_name = "adsp.mdt",
 		.pas_id = 1,
 		.has_aggre2_clk = false,
+		.auto_boot = true,
 		.active_pd_names = (char*[]){
 			"load_state",
 			NULL
@@ -513,6 +519,7 @@ static const struct adsp_data cdsp_resource_init = {
 	.firmware_name = "cdsp.mdt",
 	.pas_id = 18,
 	.has_aggre2_clk = false,
+	.auto_boot = true,
 	.ssr_name = "cdsp",
 	.sysmon_name = "cdsp",
 	.ssctl_id = 0x17,
@@ -523,6 +530,7 @@ static const struct adsp_data sm8150_cdsp_resource = {
 	.firmware_name = "cdsp.mdt",
 	.pas_id = 18,
 	.has_aggre2_clk = false,
+	.auto_boot = true,
 	.active_pd_names = (char*[]){
 		"load_state",
 		NULL
@@ -541,6 +549,7 @@ static const struct adsp_data mpss_resource_init = {
 	.firmware_name = "modem.mdt",
 	.pas_id = 4,
 	.has_aggre2_clk = false,
+	.auto_boot = false,
 	.active_pd_names = (char*[]){
 		"load_state",
 		NULL
@@ -560,6 +569,7 @@ static const struct adsp_data slpi_resource_init = {
 		.firmware_name = "slpi.mdt",
 		.pas_id = 12,
 		.has_aggre2_clk = true,
+		.auto_boot = true,
 		.ssr_name = "dsps",
 		.sysmon_name = "slpi",
 		.ssctl_id = 0x16,
@@ -570,6 +580,7 @@ static const struct adsp_data msm8998_slpi_resource = {
 		.firmware_name = "slpi.mdt",
 		.pas_id = 12,
 		.has_aggre2_clk = true,
+		.auto_boot = true,
 		.proxy_pd_names = (char*[]){
 			"ssc_cx",
 			NULL
@@ -584,6 +595,7 @@ static const struct adsp_data sm8150_slpi_resource = {
 		.firmware_name = "slpi.mdt",
 		.pas_id = 12,
 		.has_aggre2_clk = false,
+		.auto_boot = true,
 		.active_pd_names = (char*[]){
 			"load_state",
 			NULL
@@ -602,6 +614,7 @@ static const struct adsp_data wcss_resource_init = {
 	.crash_reason_smem = 421,
 	.firmware_name = "wcnss.mdt",
 	.pas_id = 6,
+	.auto_boot = true,
 	.ssr_name = "mpss",
 	.sysmon_name = "wcnss",
 	.ssctl_id = 0x12,
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 13/16] arm64: dts: qcom: msm8998: Update reserved memory map

[Sibi Sankar]

Update existing and add missing regions to the reserved memory map, as
described in version 7.1

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8998.dtsi | 62 ++++++++++++++++++++++++---
 1 file changed, 55 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index fc7838ea9a010..707673e3cf28a 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -28,8 +28,13 @@
 		#size-cells = <2>;
 		ranges;
 
-		memory@85800000 {
-			reg = <0x0 0x85800000 0x0 0x800000>;
+		hyp_mem: memory@85800000 {
+			reg = <0x0 0x85800000 0x0 0x600000>;
+			no-map;
+		};
+
+		xbl_mem: memory@85e00000 {
+			reg = <0x0 0x85e00000 0x0 0x100000>;
 			no-map;
 		};
 
@@ -38,21 +43,64 @@
 			no-map;
 		};
 
-		memory@86200000 {
+		tz_mem: memory@86200000 {
 			reg = <0x0 0x86200000 0x0 0x2d00000>;
 			no-map;
 		};
 
-		rmtfs {
+		rmtfs_mem: memory@88f00000 {
 			compatible = "qcom,rmtfs-mem";
-
-			size = <0x0 0x200000>;
-			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
+			reg = <0x0 0x88f00000 0x0 0x200000>;
 			no-map;
 
 			qcom,client-id = <1>;
 			qcom,vmid = <15>;
 		};
+
+		spss_mem: memory@8ab00000 {
+			reg = <0x0 0x8ab00000 0x0 0x700000>;
+			no-map;
+		};
+
+		adsp_mem: memory@8b200000 {
+			reg = <0x0 0x8b200000 0x0 0x1a00000>;
+			no-map;
+		};
+
+		mpss_mem: memory@8cc00000 {
+			reg = <0x0 0x8cc00000 0x0 0x7000000>;
+			no-map;
+		};
+
+		venus_mem: memory@93c00000 {
+			reg = <0x0 0x93c00000 0x0 0x500000>;
+			no-map;
+		};
+
+		mba_mem: memory@94100000 {
+			reg = <0x0 0x94100000 0x0 0x200000>;
+			no-map;
+		};
+
+		slpi_mem: memory@94300000 {
+			reg = <0x0 0x94300000 0x0 0xf00000>;
+			no-map;
+		};
+
+		ipa_fw_mem: memory@95200000 {
+			reg = <0x0 0x95200000 0x0 0x10000>;
+			no-map;
+		};
+
+		ipa_gsi_mem: memory@95210000 {
+			reg = <0x0 0x95210000 0x0 0x5000>;
+			no-map;
+		};
+
+		gpu_mem: memory@95215000 {
+			reg = <0x0 0x95215000 0x0 0x1000>;
+			no-map;
+		};
 	};
 
 	clocks {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 14/16] arm64: dts: qcom: msm8998: Add ADSP, MPSS and SLPI nodes

[Sibi Sankar]

This patch adds ADSP, MPSS and SLPI nodes for MSM8998 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi |   8 ++
 arch/arm64/boot/dts/qcom/msm8998.dtsi     | 122 ++++++++++++++++++++++
 2 files changed, 130 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
index 5f101a20a20a2..29e0c2e988e4b 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
@@ -23,6 +23,14 @@
 	};
 };
 
+&adsp_pas {
+	status = "okay";
+};
+
+&slpi_pas {
+	status = "okay";
+};
+
 &blsp1_uart3 {
 	status = "okay";
 
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 707673e3cf28a..dd1dc35e87b63 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -337,6 +337,73 @@
 		};
 	};
 
+	adsp_pas: remoteproc-adsp {
+		compatible = "qcom,msm8998-adsp-pas";
+
+		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+				      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+				      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+				      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+				      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "wdog", "fatal", "ready",
+				  "handover", "stop-ack";
+
+		clocks = <&xo>;
+		clock-names = "xo";
+
+		memory-region = <&adsp_mem>;
+
+		qcom,smem-states = <&adsp_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		power-domains = <&rpmpd MSM8998_VDDCX>;
+		power-domain-names = "cx";
+
+		status = "disabled";
+
+		glink-edge {
+			interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
+			label = "lpass";
+			qcom,remote-pid = <2>;
+			mboxes = <&apcs_glb 9>;
+		};
+	};
+
+	slpi_pas: remoteproc-slpi {
+		compatible = "qcom,msm8998-slpi-pas";
+
+		interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
+				      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+				      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+				      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+				      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "wdog", "fatal", "ready",
+				  "handover", "stop-ack";
+
+		px-supply = <&vreg_lvs2a_1p8>;
+
+		clocks = <&xo>,
+			 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
+		clock-names = "xo", "aggre2";
+
+		memory-region = <&slpi_mem>;
+
+		qcom,smem-states = <&slpi_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		power-domains = <&rpmpd MSM8998_SSCCX>;
+		power-domain-names = "ssc_cx";
+
+		status = "disabled";
+
+		glink-edge {
+			interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
+			label = "dsps";
+			qcom,remote-pid = <3>;
+			mboxes = <&apcs_glb 27>;
+		};
+	};
+
 	tcsr_mutex: hwlock {
 		compatible = "qcom,tcsr-mutex";
 		syscon = <&tcsr_mutex_regs 0 0x1000>;
@@ -1048,6 +1115,61 @@
 			#interrupt-cells = <0x2>;
 		};
 
+		mss_pil: remoteproc@4080000 {
+			compatible = "qcom,msm8998-mss-pil";
+			reg = <0x04080000 0x100>, <0x04180000 0x20>;
+			reg-names = "qdsp6", "rmb";
+
+			interrupts-extended =
+				<&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+				<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+				<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+				<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+				<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+				<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack",
+					  "shutdown-ack";
+
+			clocks = <&xo>,
+				 <&gcc GCC_MSS_CFG_AHB_CLK>,
+				 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
+				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
+				 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
+				 <&gcc GCC_MSS_SNOC_AXI_CLK>,
+				 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
+				 <&rpmcc RPM_SMD_QDSS_CLK>;
+			clock-names = "xo", "iface", "bus", "mem", "gpll0_mss",
+				      "snoc_axi", "mnoc_axi", "qdss";
+
+			qcom,smem-states = <&modem_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			resets = <&gcc GCC_MSS_RESTART>;
+			reset-names = "mss_restart";
+
+			qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
+
+			power-domains = <&rpmpd MSM8998_VDDCX>,
+					<&rpmpd MSM8998_VDDMX>;
+			power-domain-names = "cx", "mx";
+
+			mba {
+				memory-region = <&mba_mem>;
+			};
+
+			mpss {
+				memory-region = <&mpss_mem>;
+			};
+
+			glink-edge {
+				interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
+				label = "modem";
+				qcom,remote-pid = <1>;
+				mboxes = <&apcs_glb 15>;
+			};
+		};
+
 		stm: stm@6002000 {
 			compatible = "arm,coresight-stm", "arm,primecell";
 			reg = <0x06002000 0x1000>,
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 15/16] arm64: dts: qcom: sm8150: Add ADSP, CDSP, MPSS and SLPI smp2p

[Sibi Sankar]

Add the SMP2P nodes for the remoteproc states for ADSP, CDSP, MPSS and
SLPI remoteprocs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 96 ++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 0ac257637c2af..98a96fd1d6117 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -284,6 +284,102 @@
 		hwlocks = <&tcsr_mutex 3>;
 	};
 
+	smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+
+		interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apss_shared 6>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		cdsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		cdsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-lpass {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+
+		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apss_shared 10>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-mpss {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+
+		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apss_shared 14>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-slpi {
+		compatible = "qcom,smp2p";
+		qcom,smem = <481>, <430>;
+
+		interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apss_shared 26>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <3>;
+
+		slpi_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		slpi_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
 	soc: soc@0 {
 		#address-cells = <2>;
 		#size-cells = <2>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 16/16] arm64: dts: qcom: sm8150: Add ADSP, CDSP, MPSS and SLPI remoteprocs

[Sibi Sankar]

Add ADSP, CDSP, MPSS and SLPI device tree nodes for SM8150 SoC.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sm8150-mtp.dts |  12 +++
 arch/arm64/boot/dts/qcom/sm8150.dtsi    | 135 ++++++++++++++++++++++++
 2 files changed, 147 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
index aa5de42fcae45..4d9bb8145dbba 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
@@ -348,6 +348,18 @@
 	};
 };
 
+&adsp_pas {
+	status = "okay";
+};
+
+&cdsp_pas {
+	status = "okay";
+};
+
+&slpi_pas {
+	status = "okay";
+};
+
 &qupv3_id_1 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 98a96fd1d6117..58f4ce95bd966 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -5,6 +5,8 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-sm8150.h>
+#include <dt-bindings/power/qcom-aoss-qmp.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
@@ -278,6 +280,139 @@
 		};
 	};
 
+	adsp_pas: remoteproc-adsp {
+		compatible = "qcom,sm8150-adsp-pas";
+
+		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+				      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+				      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+				      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+				      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "wdog", "fatal", "ready",
+				  "handover", "stop-ack";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
+				<&rpmhpd SM8150_CX>;
+		power-domain-names = "load_state", "cx";
+
+		memory-region = <&adsp_mem>;
+
+		qcom,smem-states = <&adsp_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		status = "disabled";
+
+		glink-edge {
+			interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+			label = "lpass";
+			qcom,remote-pid = <2>;
+			mboxes = <&apss_shared 8>;
+		};
+	};
+
+	cdsp_pas: remoteproc-cdsp {
+		compatible = "qcom,sm8150-cdsp-pas";
+
+		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+				      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+				      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+				      <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+				      <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "wdog", "fatal", "ready",
+				  "handover", "stop-ack";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
+				<&rpmhpd SM8150_CX>;
+		power-domain-names = "load_state", "cx";
+
+		memory-region = <&cdsp_mem>;
+
+		qcom,smem-states = <&cdsp_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		status = "disabled";
+
+		glink-edge {
+			interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
+			label = "cdsp";
+			qcom,remote-pid = <5>;
+			mboxes = <&apss_shared 4>;
+		};
+	};
+
+	mpss_pas: remoteproc-mpss {
+		compatible = "qcom,sm8150-mpss-pas";
+
+		interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
+				      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+				      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+				      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+				      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+				      <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "wdog", "fatal", "ready", "handover",
+				  "stop-ack", "shutdown-ack";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
+				<&rpmhpd SM8150_CX>,
+				<&rpmhpd SM8150_MSS>;
+		power-domain-names = "load_state", "cx", "mss";
+
+		memory-region = <&mpss_mem>;
+
+		qcom,smem-states = <&modem_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink-edge {
+			interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
+			label = "modem";
+			qcom,remote-pid = <1>;
+			mboxes = <&apss_shared 12>;
+		};
+	};
+
+	slpi_pas: remoteproc-slpi {
+		compatible = "qcom,sm8150-slpi-pas";
+
+		interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
+				      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+				      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+				      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+				      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "wdog", "fatal", "ready",
+				  "handover", "stop-ack";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
+				<&rpmhpd SM8150_LCX>,
+				<&rpmhpd SM8150_LMX>;
+		power-domain-names = "load_state", "lcx", "lmx";
+
+		memory-region = <&slpi_mem>;
+
+		qcom,smem-states = <&slpi_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		status = "disabled";
+
+		glink-edge {
+			interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
+			label = "dsps";
+			qcom,remote-pid = <3>;
+			mboxes = <&apss_shared 24>;
+		};
+	};
+
 	smem {
 		compatible = "qcom,smem";
 		memory-region = <&smem_mem>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 01/16] remoteproc: q6v5-mss: fixup MSM8998 MSS out of reset sequence

[Jeffrey Hugo]

On Mon, Nov 18, 2019 at 2:43 PM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> Fixup the following in the MSS out of reset sequence on MSM8998:
> * skip ACC override on MSM8998.
> * wait for BHS_EN_REST_ACK to be set before setting the LDO to bypass.
> * remove "mem" clock from the active pool.

Why any of this is necessary isn't explained.
Seems like it should be 3 separate patches.
Regarding the mem clock change, wouldn't it be an issue if we don't
vote for that?

>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  drivers/remoteproc/qcom_q6v5_mss.c | 23 ++++++++++++++++++++---
>  1 file changed, 20 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
> index 471128a2e7239..2becf6dade936 100644
> --- a/drivers/remoteproc/qcom_q6v5_mss.c
> +++ b/drivers/remoteproc/qcom_q6v5_mss.c
> @@ -100,6 +100,11 @@
>  #define QDSP6SS_XO_CBCR                0x0038
>  #define QDSP6SS_ACC_OVERRIDE_VAL               0x20
>
> +/* QDSP6v62 parameters */
> +#define QDSP6SS_BHS_EN_REST_ACK                BIT(0)
> +#define BHS_CHECK_MAX_LOOPS            200
> +#define QDSP6SS_BHS_STATUS             0x0C4
> +
>  /* QDSP6v65 parameters */
>  #define QDSP6SS_SLEEP                   0x3C
>  #define QDSP6SS_BOOT_CORE_START         0x400
> @@ -505,8 +510,9 @@ static int q6v5proc_reset(struct q6v5 *qproc)
>                 int mem_pwr_ctl;
>
>                 /* Override the ACC value if required */
> -               writel(QDSP6SS_ACC_OVERRIDE_VAL,
> -                      qproc->reg_base + QDSP6SS_STRAP_ACC);
> +               if (qproc->version == MSS_MSM8996)
> +                       writel(QDSP6SS_ACC_OVERRIDE_VAL,
> +                              qproc->reg_base + QDSP6SS_STRAP_ACC);
>
>                 /* Assert resets, stop core */
>                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
> @@ -534,6 +540,18 @@ static int q6v5proc_reset(struct q6v5 *qproc)
>                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>                 udelay(1);
>
> +               /* wait for BHS_EN_REST_ACK to be set */
> +               if (qproc->version == MSS_MSM8998) {
> +                       ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BHS_STATUS,
> +                                                val, (val & QDSP6SS_BHS_EN_REST_ACK),
> +                                                1, BHS_CHECK_MAX_LOOPS);
> +                       if (ret) {
> +                               dev_err(qproc->dev,
> +                                       "QDSP6SS_BHS_EN_REST_ACK timedout\n");
> +                               return -ETIMEDOUT;
> +                       }
> +               }
> +
>                 /* Put LDO in bypass mode */
>                 val |= QDSP6v56_LDO_BYP;
>                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> @@ -1594,7 +1612,6 @@ static const struct rproc_hexagon_res msm8998_mss = {
>         .active_clk_names = (char*[]){
>                         "iface",
>                         "bus",
> -                       "mem",
>                         "gpll0_mss",
>                         "mnoc_axi",
>                         "snoc_axi",
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>

Re: [PATCH 13/16] arm64: dts: qcom: msm8998: Update reserved memory map

[Jeffrey Hugo]

On Mon, Nov 18, 2019 at 2:45 PM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> Update existing and add missing regions to the reserved memory map, as
> described in version 7.1
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/msm8998.dtsi | 62 ++++++++++++++++++++++++---
>  1 file changed, 55 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index fc7838ea9a010..707673e3cf28a 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -28,8 +28,13 @@
>                 #size-cells = <2>;
>                 ranges;
>
> -               memory@85800000 {
> -                       reg = <0x0 0x85800000 0x0 0x800000>;
> +               hyp_mem: memory@85800000 {
> +                       reg = <0x0 0x85800000 0x0 0x600000>;
> +                       no-map;
> +               };
> +
> +               xbl_mem: memory@85e00000 {

Are we ever going to use this label?

> +                       reg = <0x0 0x85e00000 0x0 0x100000>;
>                         no-map;
>                 };
>
> @@ -38,21 +43,64 @@
>                         no-map;
>                 };
>
> -               memory@86200000 {
> +               tz_mem: memory@86200000 {

Again, are we ever going to use this?

>                         reg = <0x0 0x86200000 0x0 0x2d00000>;
>                         no-map;
>                 };
>
> -               rmtfs {
> +               rmtfs_mem: memory@88f00000 {
>                         compatible = "qcom,rmtfs-mem";
> -
> -                       size = <0x0 0x200000>;
> -                       alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
> +                       reg = <0x0 0x88f00000 0x0 0x200000>;

This seems to overlap with a defined region in the memory map.
0x9fa00000 seems to be a better address.

>                         no-map;
>
>                         qcom,client-id = <1>;
>                         qcom,vmid = <15>;
>                 };
> +
> +               spss_mem: memory@8ab00000 {
> +                       reg = <0x0 0x8ab00000 0x0 0x700000>;
> +                       no-map;
> +               };
> +
> +               adsp_mem: memory@8b200000 {
> +                       reg = <0x0 0x8b200000 0x0 0x1a00000>;
> +                       no-map;
> +               };
> +
> +               mpss_mem: memory@8cc00000 {
> +                       reg = <0x0 0x8cc00000 0x0 0x7000000>;
> +                       no-map;
> +               };
> +
> +               venus_mem: memory@93c00000 {
> +                       reg = <0x0 0x93c00000 0x0 0x500000>;
> +                       no-map;
> +               };
> +
> +               mba_mem: memory@94100000 {
> +                       reg = <0x0 0x94100000 0x0 0x200000>;
> +                       no-map;
> +               };
> +
> +               slpi_mem: memory@94300000 {
> +                       reg = <0x0 0x94300000 0x0 0xf00000>;
> +                       no-map;
> +               };
> +
> +               ipa_fw_mem: memory@95200000 {
> +                       reg = <0x0 0x95200000 0x0 0x10000>;
> +                       no-map;
> +               };
> +
> +               ipa_gsi_mem: memory@95210000 {
> +                       reg = <0x0 0x95210000 0x0 0x5000>;
> +                       no-map;
> +               };
> +
> +               gpu_mem: memory@95215000 {
> +                       reg = <0x0 0x95215000 0x0 0x1000>;

This is the wrong size for the zap region.

> +                       no-map;
> +               };
>         };
>
>         clocks {
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>

Re: [PATCH 14/16] arm64: dts: qcom: msm8998: Add ADSP, MPSS and SLPI nodes

[Jeffrey Hugo]

On Mon, Nov 18, 2019 at 2:45 PM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> This patch adds ADSP, MPSS and SLPI nodes for MSM8998 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi |   8 ++
>  arch/arm64/boot/dts/qcom/msm8998.dtsi     | 122 ++++++++++++++++++++++
>  2 files changed, 130 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
> index 5f101a20a20a2..29e0c2e988e4b 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
> @@ -23,6 +23,14 @@
>         };
>  };
>
> +&adsp_pas {
> +       status = "okay";
> +};
> +
> +&slpi_pas {

"b" comes before "s", no?

> +       status = "okay";
> +};
> +
>  &blsp1_uart3 {
>         status = "okay";
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index 707673e3cf28a..dd1dc35e87b63 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -337,6 +337,73 @@
>                 };
>         };
>
> +       adsp_pas: remoteproc-adsp {
> +               compatible = "qcom,msm8998-adsp-pas";
> +
> +               interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
> +                                     <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                     <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                     <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                     <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> +               interrupt-names = "wdog", "fatal", "ready",
> +                                 "handover", "stop-ack";
> +
> +               clocks = <&xo>;
> +               clock-names = "xo";
> +
> +               memory-region = <&adsp_mem>;
> +
> +               qcom,smem-states = <&adsp_smp2p_out 0>;
> +               qcom,smem-state-names = "stop";
> +
> +               power-domains = <&rpmpd MSM8998_VDDCX>;
> +               power-domain-names = "cx";
> +
> +               status = "disabled";
> +
> +               glink-edge {
> +                       interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
> +                       label = "lpass";
> +                       qcom,remote-pid = <2>;
> +                       mboxes = <&apcs_glb 9>;
> +               };
> +       };
> +
> +       slpi_pas: remoteproc-slpi {
> +               compatible = "qcom,msm8998-slpi-pas";
> +
> +               interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
> +                                     <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                                     <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                                     <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                                     <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> +               interrupt-names = "wdog", "fatal", "ready",
> +                                 "handover", "stop-ack";
> +
> +               px-supply = <&vreg_lvs2a_1p8>;
> +
> +               clocks = <&xo>,
> +                        <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
> +               clock-names = "xo", "aggre2";
> +
> +               memory-region = <&slpi_mem>;
> +
> +               qcom,smem-states = <&slpi_smp2p_out 0>;
> +               qcom,smem-state-names = "stop";
> +
> +               power-domains = <&rpmpd MSM8998_SSCCX>;
> +               power-domain-names = "ssc_cx";
> +
> +               status = "disabled";
> +
> +               glink-edge {
> +                       interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
> +                       label = "dsps";
> +                       qcom,remote-pid = <3>;
> +                       mboxes = <&apcs_glb 27>;
> +               };
> +       };
> +
>         tcsr_mutex: hwlock {
>                 compatible = "qcom,tcsr-mutex";
>                 syscon = <&tcsr_mutex_regs 0 0x1000>;
> @@ -1048,6 +1115,61 @@
>                         #interrupt-cells = <0x2>;
>                 };
>
> +               mss_pil: remoteproc@4080000 {
> +                       compatible = "qcom,msm8998-mss-pil";
> +                       reg = <0x04080000 0x100>, <0x04180000 0x20>;
> +                       reg-names = "qdsp6", "rmb";
> +
> +                       interrupts-extended =
> +                               <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> +                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> +                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> +                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> +                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> +                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "wdog", "fatal", "ready",
> +                                         "handover", "stop-ack",
> +                                         "shutdown-ack";
> +
> +                       clocks = <&xo>,
> +                                <&gcc GCC_MSS_CFG_AHB_CLK>,
> +                                <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
> +                                <&gcc GCC_BOOT_ROM_AHB_CLK>,
> +                                <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
> +                                <&gcc GCC_MSS_SNOC_AXI_CLK>,
> +                                <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
> +                                <&rpmcc RPM_SMD_QDSS_CLK>;
> +                       clock-names = "xo", "iface", "bus", "mem", "gpll0_mss",
> +                                     "snoc_axi", "mnoc_axi", "qdss";
> +
> +                       qcom,smem-states = <&modem_smp2p_out 0>;
> +                       qcom,smem-state-names = "stop";
> +
> +                       resets = <&gcc GCC_MSS_RESTART>;
> +                       reset-names = "mss_restart";
> +
> +                       qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
> +
> +                       power-domains = <&rpmpd MSM8998_VDDCX>,
> +                                       <&rpmpd MSM8998_VDDMX>;
> +                       power-domain-names = "cx", "mx";
> +
> +                       mba {
> +                               memory-region = <&mba_mem>;
> +                       };
> +
> +                       mpss {
> +                               memory-region = <&mpss_mem>;
> +                       };
> +
> +                       glink-edge {
> +                               interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
> +                               label = "modem";
> +                               qcom,remote-pid = <1>;
> +                               mboxes = <&apcs_glb 15>;
> +                       };
> +               };
> +
>                 stm: stm@6002000 {
>                         compatible = "arm,coresight-stm", "arm,primecell";
>                         reg = <0x06002000 0x1000>,
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>

Re: [PATCH 13/16] arm64: dts: qcom: msm8998: Update reserved memory map

[sibis]

Hey Jeff,
Thanks for taking time to review
the series.

On 2019-11-19 03:34, Jeffrey Hugo wrote:
> On Mon, Nov 18, 2019 at 2:45 PM Sibi Sankar <sibis@codeaurora.org> 
> wrote:
>> 
>> Update existing and add missing regions to the reserved memory map, as
>> described in version 7.1
>> 
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/msm8998.dtsi | 62 
>> ++++++++++++++++++++++++---
>>  1 file changed, 55 insertions(+), 7 deletions(-)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi 
>> b/arch/arm64/boot/dts/qcom/msm8998.dtsi
>> index fc7838ea9a010..707673e3cf28a 100644
>> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
>> @@ -28,8 +28,13 @@
>>                 #size-cells = <2>;
>>                 ranges;
>> 
>> -               memory@85800000 {
>> -                       reg = <0x0 0x85800000 0x0 0x800000>;
>> +               hyp_mem: memory@85800000 {
>> +                       reg = <0x0 0x85800000 0x0 0x600000>;
>> +                       no-map;
>> +               };
>> +
>> +               xbl_mem: memory@85e00000 {
> 
> Are we ever going to use this label?

just leaving it here for info with the
added benefit of being deleteable
if MSM8998 uses a different boot chain
where xbl_mem/tz_mem remains unused as
in the case of Cheza

> 
>> +                       reg = <0x0 0x85e00000 0x0 0x100000>;
>>                         no-map;
>>                 };
>> 
>> @@ -38,21 +43,64 @@
>>                         no-map;
>>                 };
>> 
>> -               memory@86200000 {
>> +               tz_mem: memory@86200000 {
> 
> Again, are we ever going to use this?

ditto

> 
>>                         reg = <0x0 0x86200000 0x0 0x2d00000>;
>>                         no-map;
>>                 };
>> 
>> -               rmtfs {
>> +               rmtfs_mem: memory@88f00000 {
>>                         compatible = "qcom,rmtfs-mem";
>> -
>> -                       size = <0x0 0x200000>;
>> -                       alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
>> +                       reg = <0x0 0x88f00000 0x0 0x200000>;
> 
> This seems to overlap with a defined region in the memory map.
> 0x9fa00000 seems to be a better address.

just following the what we did
for SDM845 SoC 0x88f00000 should
be safe to use.

> 
>>                         no-map;
>> 
>>                         qcom,client-id = <1>;
>>                         qcom,vmid = <15>;
>>                 };
>> +
>> +               spss_mem: memory@8ab00000 {
>> +                       reg = <0x0 0x8ab00000 0x0 0x700000>;
>> +                       no-map;
>> +               };
>> +
>> +               adsp_mem: memory@8b200000 {
>> +                       reg = <0x0 0x8b200000 0x0 0x1a00000>;
>> +                       no-map;
>> +               };
>> +
>> +               mpss_mem: memory@8cc00000 {
>> +                       reg = <0x0 0x8cc00000 0x0 0x7000000>;
>> +                       no-map;
>> +               };
>> +
>> +               venus_mem: memory@93c00000 {
>> +                       reg = <0x0 0x93c00000 0x0 0x500000>;
>> +                       no-map;
>> +               };
>> +
>> +               mba_mem: memory@94100000 {
>> +                       reg = <0x0 0x94100000 0x0 0x200000>;
>> +                       no-map;
>> +               };
>> +
>> +               slpi_mem: memory@94300000 {
>> +                       reg = <0x0 0x94300000 0x0 0xf00000>;
>> +                       no-map;
>> +               };
>> +
>> +               ipa_fw_mem: memory@95200000 {
>> +                       reg = <0x0 0x95200000 0x0 0x10000>;
>> +                       no-map;
>> +               };
>> +
>> +               ipa_gsi_mem: memory@95210000 {
>> +                       reg = <0x0 0x95210000 0x0 0x5000>;
>> +                       no-map;
>> +               };
>> +
>> +               gpu_mem: memory@95215000 {
>> +                       reg = <0x0 0x95215000 0x0 0x1000>;
> 
> This is the wrong size for the zap region.

double checked the memory maps,
gpu mem size is mentioned as 4kb
is that not the case?


> 
>> +                       no-map;
>> +               };
>>         };
>> 
>>         clocks {
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
>> Forum,
>> a Linux Foundation Collaborative Project
>> 

Re: [PATCH 14/16] arm64: dts: qcom: msm8998: Add ADSP, MPSS and SLPI nodes

[sibis]

On 2019-11-19 03:37, Jeffrey Hugo wrote:
> On Mon, Nov 18, 2019 at 2:45 PM Sibi Sankar <sibis@codeaurora.org> 
> wrote:
>> 
>> This patch adds ADSP, MPSS and SLPI nodes for MSM8998 SoCs.
>> 
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi |   8 ++
>>  arch/arm64/boot/dts/qcom/msm8998.dtsi     | 122 
>> ++++++++++++++++++++++
>>  2 files changed, 130 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi 
>> b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
>> index 5f101a20a20a2..29e0c2e988e4b 100644
>> --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
>> @@ -23,6 +23,14 @@
>>         };
>>  };
>> 
>> +&adsp_pas {
>> +       status = "okay";
>> +};
>> +
>> +&slpi_pas {
> 
> "b" comes before "s", no?

will re-order it in the next
re-spin.

> 
>> +       status = "okay";
>> +};
>> +
>>  &blsp1_uart3 {
>>         status = "okay";
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi 
>> b/arch/arm64/boot/dts/qcom/msm8998.dtsi
>> index 707673e3cf28a..dd1dc35e87b63 100644
>> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
>> @@ -337,6 +337,73 @@
>>                 };
>>         };
>> 
>> +       adsp_pas: remoteproc-adsp {
>> +               compatible = "qcom,msm8998-adsp-pas";
>> +
>> +               interrupts-extended = <&intc GIC_SPI 162 
>> IRQ_TYPE_EDGE_RISING>,
>> +                                     <&adsp_smp2p_in 0 
>> IRQ_TYPE_EDGE_RISING>,
>> +                                     <&adsp_smp2p_in 1 
>> IRQ_TYPE_EDGE_RISING>,
>> +                                     <&adsp_smp2p_in 2 
>> IRQ_TYPE_EDGE_RISING>,
>> +                                     <&adsp_smp2p_in 3 
>> IRQ_TYPE_EDGE_RISING>;
>> +               interrupt-names = "wdog", "fatal", "ready",
>> +                                 "handover", "stop-ack";
>> +
>> +               clocks = <&xo>;
>> +               clock-names = "xo";
>> +
>> +               memory-region = <&adsp_mem>;
>> +
>> +               qcom,smem-states = <&adsp_smp2p_out 0>;
>> +               qcom,smem-state-names = "stop";
>> +
>> +               power-domains = <&rpmpd MSM8998_VDDCX>;
>> +               power-domain-names = "cx";
>> +
>> +               status = "disabled";
>> +
>> +               glink-edge {
>> +                       interrupts = <GIC_SPI 157 
>> IRQ_TYPE_EDGE_RISING>;
>> +                       label = "lpass";
>> +                       qcom,remote-pid = <2>;
>> +                       mboxes = <&apcs_glb 9>;
>> +               };
>> +       };
>> +
>> +       slpi_pas: remoteproc-slpi {
>> +               compatible = "qcom,msm8998-slpi-pas";
>> +
>> +               interrupts-extended = <&intc GIC_SPI 390 
>> IRQ_TYPE_EDGE_RISING>,
>> +                                     <&slpi_smp2p_in 0 
>> IRQ_TYPE_EDGE_RISING>,
>> +                                     <&slpi_smp2p_in 1 
>> IRQ_TYPE_EDGE_RISING>,
>> +                                     <&slpi_smp2p_in 2 
>> IRQ_TYPE_EDGE_RISING>,
>> +                                     <&slpi_smp2p_in 3 
>> IRQ_TYPE_EDGE_RISING>;
>> +               interrupt-names = "wdog", "fatal", "ready",
>> +                                 "handover", "stop-ack";
>> +
>> +               px-supply = <&vreg_lvs2a_1p8>;
>> +
>> +               clocks = <&xo>,
>> +                        <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> +               clock-names = "xo", "aggre2";
>> +
>> +               memory-region = <&slpi_mem>;
>> +
>> +               qcom,smem-states = <&slpi_smp2p_out 0>;
>> +               qcom,smem-state-names = "stop";
>> +
>> +               power-domains = <&rpmpd MSM8998_SSCCX>;
>> +               power-domain-names = "ssc_cx";
>> +
>> +               status = "disabled";
>> +
>> +               glink-edge {
>> +                       interrupts = <GIC_SPI 179 
>> IRQ_TYPE_EDGE_RISING>;
>> +                       label = "dsps";
>> +                       qcom,remote-pid = <3>;
>> +                       mboxes = <&apcs_glb 27>;
>> +               };
>> +       };
>> +
>>         tcsr_mutex: hwlock {
>>                 compatible = "qcom,tcsr-mutex";
>>                 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> @@ -1048,6 +1115,61 @@
>>                         #interrupt-cells = <0x2>;
>>                 };
>> 
>> +               mss_pil: remoteproc@4080000 {
>> +                       compatible = "qcom,msm8998-mss-pil";
>> +                       reg = <0x04080000 0x100>, <0x04180000 0x20>;
>> +                       reg-names = "qdsp6", "rmb";
>> +
>> +                       interrupts-extended =
>> +                               <&intc GIC_SPI 448 
>> IRQ_TYPE_EDGE_RISING>,
>> +                               <&modem_smp2p_in 0 
>> IRQ_TYPE_EDGE_RISING>,
>> +                               <&modem_smp2p_in 1 
>> IRQ_TYPE_EDGE_RISING>,
>> +                               <&modem_smp2p_in 2 
>> IRQ_TYPE_EDGE_RISING>,
>> +                               <&modem_smp2p_in 3 
>> IRQ_TYPE_EDGE_RISING>,
>> +                               <&modem_smp2p_in 7 
>> IRQ_TYPE_EDGE_RISING>;
>> +                       interrupt-names = "wdog", "fatal", "ready",
>> +                                         "handover", "stop-ack",
>> +                                         "shutdown-ack";
>> +
>> +                       clocks = <&xo>,
>> +                                <&gcc GCC_MSS_CFG_AHB_CLK>,
>> +                                <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
>> +                                <&gcc GCC_BOOT_ROM_AHB_CLK>,
>> +                                <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
>> +                                <&gcc GCC_MSS_SNOC_AXI_CLK>,
>> +                                <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
>> +                                <&rpmcc RPM_SMD_QDSS_CLK>;
>> +                       clock-names = "xo", "iface", "bus", "mem", 
>> "gpll0_mss",
>> +                                     "snoc_axi", "mnoc_axi", "qdss";
>> +
>> +                       qcom,smem-states = <&modem_smp2p_out 0>;
>> +                       qcom,smem-state-names = "stop";
>> +
>> +                       resets = <&gcc GCC_MSS_RESTART>;
>> +                       reset-names = "mss_restart";
>> +
>> +                       qcom,halt-regs = <&tcsr_mutex_regs 0x23000 
>> 0x25000 0x24000>;
>> +
>> +                       power-domains = <&rpmpd MSM8998_VDDCX>,
>> +                                       <&rpmpd MSM8998_VDDMX>;
>> +                       power-domain-names = "cx", "mx";
>> +
>> +                       mba {
>> +                               memory-region = <&mba_mem>;
>> +                       };
>> +
>> +                       mpss {
>> +                               memory-region = <&mpss_mem>;
>> +                       };
>> +
>> +                       glink-edge {
>> +                               interrupts = <GIC_SPI 452 
>> IRQ_TYPE_EDGE_RISING>;
>> +                               label = "modem";
>> +                               qcom,remote-pid = <1>;
>> +                               mboxes = <&apcs_glb 15>;
>> +                       };
>> +               };
>> +
>>                 stm: stm@6002000 {
>>                         compatible = "arm,coresight-stm", 
>> "arm,primecell";
>>                         reg = <0x06002000 0x1000>,
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
>> Forum,
>> a Linux Foundation Collaborative Project
>> 

Re: [PATCH 01/16] remoteproc: q6v5-mss: fixup MSM8998 MSS out of reset sequence

[Sibi Sankar]

Hey Jeff,

On 11/19/19 3:24 AM, Jeffrey Hugo wrote:
> On Mon, Nov 18, 2019 at 2:43 PM Sibi Sankar <sibis@codeaurora.org> wrote:
>>
>> Fixup the following in the MSS out of reset sequence on MSM8998:
>> * skip ACC override on MSM8998.
>> * wait for BHS_EN_REST_ACK to be set before setting the LDO to bypass.
>> * remove "mem" clock from the active pool.
> 
> Why any of this is necessary isn't explained.

Honestly the above two fixes didn't seem to have any impact when I
tested it on MSM8998 MTP just making sure that we allign with the
out of reset sequence found on msm-4.4.

> Seems like it should be 3 separate patches.
> Regarding the mem clock change, wouldn't it be an issue if we don't
> vote for that?

we already proxy vote for it though.

> 
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>>   drivers/remoteproc/qcom_q6v5_mss.c | 23 ++++++++++++++++++++---
>>   1 file changed, 20 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
>> index 471128a2e7239..2becf6dade936 100644
>> --- a/drivers/remoteproc/qcom_q6v5_mss.c
>> +++ b/drivers/remoteproc/qcom_q6v5_mss.c
>> @@ -100,6 +100,11 @@
>>   #define QDSP6SS_XO_CBCR                0x0038
>>   #define QDSP6SS_ACC_OVERRIDE_VAL               0x20
>>
>> +/* QDSP6v62 parameters */
>> +#define QDSP6SS_BHS_EN_REST_ACK                BIT(0)
>> +#define BHS_CHECK_MAX_LOOPS            200
>> +#define QDSP6SS_BHS_STATUS             0x0C4
>> +
>>   /* QDSP6v65 parameters */
>>   #define QDSP6SS_SLEEP                   0x3C
>>   #define QDSP6SS_BOOT_CORE_START         0x400
>> @@ -505,8 +510,9 @@ static int q6v5proc_reset(struct q6v5 *qproc)
>>                  int mem_pwr_ctl;
>>
>>                  /* Override the ACC value if required */
>> -               writel(QDSP6SS_ACC_OVERRIDE_VAL,
>> -                      qproc->reg_base + QDSP6SS_STRAP_ACC);
>> +               if (qproc->version == MSS_MSM8996)
>> +                       writel(QDSP6SS_ACC_OVERRIDE_VAL,
>> +                              qproc->reg_base + QDSP6SS_STRAP_ACC);
>>
>>                  /* Assert resets, stop core */
>>                  val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
>> @@ -534,6 +540,18 @@ static int q6v5proc_reset(struct q6v5 *qproc)
>>                  val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>>                  udelay(1);
>>
>> +               /* wait for BHS_EN_REST_ACK to be set */
>> +               if (qproc->version == MSS_MSM8998) {
>> +                       ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BHS_STATUS,
>> +                                                val, (val & QDSP6SS_BHS_EN_REST_ACK),
>> +                                                1, BHS_CHECK_MAX_LOOPS);
>> +                       if (ret) {
>> +                               dev_err(qproc->dev,
>> +                                       "QDSP6SS_BHS_EN_REST_ACK timedout\n");
>> +                               return -ETIMEDOUT;
>> +                       }
>> +               }
>> +
>>                  /* Put LDO in bypass mode */
>>                  val |= QDSP6v56_LDO_BYP;
>>                  writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> @@ -1594,7 +1612,6 @@ static const struct rproc_hexagon_res msm8998_mss = {
>>          .active_clk_names = (char*[]){
>>                          "iface",
>>                          "bus",
>> -                       "mem",
>>                          "gpll0_mss",
>>                          "mnoc_axi",
>>                          "snoc_axi",
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>> a Linux Foundation Collaborative Project
>>
> 

-- 
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 01/16] remoteproc: q6v5-mss: fixup MSM8998 MSS out of reset sequence

[Jeffrey Hugo]

On Tue, Nov 19, 2019 at 8:25 AM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> Hey Jeff,
>
> On 11/19/19 3:24 AM, Jeffrey Hugo wrote:
> > On Mon, Nov 18, 2019 at 2:43 PM Sibi Sankar <sibis@codeaurora.org> wrote:
> >>
> >> Fixup the following in the MSS out of reset sequence on MSM8998:
> >> * skip ACC override on MSM8998.
> >> * wait for BHS_EN_REST_ACK to be set before setting the LDO to bypass.
> >> * remove "mem" clock from the active pool.
> >
> > Why any of this is necessary isn't explained.
>
> Honestly the above two fixes didn't seem to have any impact when I
> tested it on MSM8998 MTP just making sure that we allign with the
> out of reset sequence found on msm-4.4.

That should be mentioned in the commit text then.

>
> > Seems like it should be 3 separate patches.
> > Regarding the mem clock change, wouldn't it be an issue if we don't
> > vote for that?
>
> we already proxy vote for it though.

Ah, so we do.  That should be mentioned in the commit text.

>
> >
> >>
> >> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> >> ---
> >>   drivers/remoteproc/qcom_q6v5_mss.c | 23 ++++++++++++++++++++---
> >>   1 file changed, 20 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
> >> index 471128a2e7239..2becf6dade936 100644
> >> --- a/drivers/remoteproc/qcom_q6v5_mss.c
> >> +++ b/drivers/remoteproc/qcom_q6v5_mss.c
> >> @@ -100,6 +100,11 @@
> >>   #define QDSP6SS_XO_CBCR                0x0038
> >>   #define QDSP6SS_ACC_OVERRIDE_VAL               0x20
> >>
> >> +/* QDSP6v62 parameters */
> >> +#define QDSP6SS_BHS_EN_REST_ACK                BIT(0)
> >> +#define BHS_CHECK_MAX_LOOPS            200
> >> +#define QDSP6SS_BHS_STATUS             0x0C4
> >> +
> >>   /* QDSP6v65 parameters */
> >>   #define QDSP6SS_SLEEP                   0x3C
> >>   #define QDSP6SS_BOOT_CORE_START         0x400
> >> @@ -505,8 +510,9 @@ static int q6v5proc_reset(struct q6v5 *qproc)
> >>                  int mem_pwr_ctl;
> >>
> >>                  /* Override the ACC value if required */
> >> -               writel(QDSP6SS_ACC_OVERRIDE_VAL,
> >> -                      qproc->reg_base + QDSP6SS_STRAP_ACC);
> >> +               if (qproc->version == MSS_MSM8996)
> >> +                       writel(QDSP6SS_ACC_OVERRIDE_VAL,
> >> +                              qproc->reg_base + QDSP6SS_STRAP_ACC);
> >>
> >>                  /* Assert resets, stop core */
> >>                  val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
> >> @@ -534,6 +540,18 @@ static int q6v5proc_reset(struct q6v5 *qproc)
> >>                  val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> >>                  udelay(1);
> >>
> >> +               /* wait for BHS_EN_REST_ACK to be set */
> >> +               if (qproc->version == MSS_MSM8998) {
> >> +                       ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BHS_STATUS,
> >> +                                                val, (val & QDSP6SS_BHS_EN_REST_ACK),
> >> +                                                1, BHS_CHECK_MAX_LOOPS);
> >> +                       if (ret) {
> >> +                               dev_err(qproc->dev,
> >> +                                       "QDSP6SS_BHS_EN_REST_ACK timedout\n");
> >> +                               return -ETIMEDOUT;
> >> +                       }
> >> +               }
> >> +
> >>                  /* Put LDO in bypass mode */
> >>                  val |= QDSP6v56_LDO_BYP;
> >>                  writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> >> @@ -1594,7 +1612,6 @@ static const struct rproc_hexagon_res msm8998_mss = {
> >>          .active_clk_names = (char*[]){
> >>                          "iface",
> >>                          "bus",
> >> -                       "mem",
> >>                          "gpll0_mss",
> >>                          "mnoc_axi",
> >>                          "snoc_axi",
> >> --
> >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> >> a Linux Foundation Collaborative Project
> >>
> >
>
> --
> Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project

Re: [PATCH 01/16] remoteproc: q6v5-mss: fixup MSM8998 MSS out of reset sequence

[Sibi Sankar]

On 2019-11-19 21:13, Jeffrey Hugo wrote:
> On Tue, Nov 19, 2019 at 8:25 AM Sibi Sankar <sibis@codeaurora.org> 
> wrote:
>> 
>> Hey Jeff,
>> 
>> On 11/19/19 3:24 AM, Jeffrey Hugo wrote:
>> > On Mon, Nov 18, 2019 at 2:43 PM Sibi Sankar <sibis@codeaurora.org> wrote:
>> >>
>> >> Fixup the following in the MSS out of reset sequence on MSM8998:
>> >> * skip ACC override on MSM8998.
>> >> * wait for BHS_EN_REST_ACK to be set before setting the LDO to bypass.
>> >> * remove "mem" clock from the active pool.
>> >
>> > Why any of this is necessary isn't explained.
>> 
>> Honestly the above two fixes didn't seem to have any impact when I
>> tested it on MSM8998 MTP just making sure that we allign with the
>> out of reset sequence found on msm-4.4.
> 
> That should be mentioned in the commit text then.
> 
>> 
>> > Seems like it should be 3 separate patches.
>> > Regarding the mem clock change, wouldn't it be an issue if we don't
>> > vote for that?
>> 
>> we already proxy vote for it though.
> 
> Ah, so we do.  That should be mentioned in the commit text.

okay I'll add more details in the
in the next-respin :)

> 
>> 
>> >
>> >>
>> >> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> >> ---
>> >>   drivers/remoteproc/qcom_q6v5_mss.c | 23 ++++++++++++++++++++---
>> >>   1 file changed, 20 insertions(+), 3 deletions(-)
>> >>
>> >> diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
>> >> index 471128a2e7239..2becf6dade936 100644
>> >> --- a/drivers/remoteproc/qcom_q6v5_mss.c
>> >> +++ b/drivers/remoteproc/qcom_q6v5_mss.c
>> >> @@ -100,6 +100,11 @@
>> >>   #define QDSP6SS_XO_CBCR                0x0038
>> >>   #define QDSP6SS_ACC_OVERRIDE_VAL               0x20
>> >>
>> >> +/* QDSP6v62 parameters */
>> >> +#define QDSP6SS_BHS_EN_REST_ACK                BIT(0)
>> >> +#define BHS_CHECK_MAX_LOOPS            200
>> >> +#define QDSP6SS_BHS_STATUS             0x0C4
>> >> +
>> >>   /* QDSP6v65 parameters */
>> >>   #define QDSP6SS_SLEEP                   0x3C
>> >>   #define QDSP6SS_BOOT_CORE_START         0x400
>> >> @@ -505,8 +510,9 @@ static int q6v5proc_reset(struct q6v5 *qproc)
>> >>                  int mem_pwr_ctl;
>> >>
>> >>                  /* Override the ACC value if required */
>> >> -               writel(QDSP6SS_ACC_OVERRIDE_VAL,
>> >> -                      qproc->reg_base + QDSP6SS_STRAP_ACC);
>> >> +               if (qproc->version == MSS_MSM8996)
>> >> +                       writel(QDSP6SS_ACC_OVERRIDE_VAL,
>> >> +                              qproc->reg_base + QDSP6SS_STRAP_ACC);
>> >>
>> >>                  /* Assert resets, stop core */
>> >>                  val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
>> >> @@ -534,6 +540,18 @@ static int q6v5proc_reset(struct q6v5 *qproc)
>> >>                  val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> >>                  udelay(1);
>> >>
>> >> +               /* wait for BHS_EN_REST_ACK to be set */
>> >> +               if (qproc->version == MSS_MSM8998) {
>> >> +                       ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BHS_STATUS,
>> >> +                                                val, (val & QDSP6SS_BHS_EN_REST_ACK),
>> >> +                                                1, BHS_CHECK_MAX_LOOPS);
>> >> +                       if (ret) {
>> >> +                               dev_err(qproc->dev,
>> >> +                                       "QDSP6SS_BHS_EN_REST_ACK timedout\n");
>> >> +                               return -ETIMEDOUT;
>> >> +                       }
>> >> +               }
>> >> +
>> >>                  /* Put LDO in bypass mode */
>> >>                  val |= QDSP6v56_LDO_BYP;
>> >>                  writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> >> @@ -1594,7 +1612,6 @@ static const struct rproc_hexagon_res msm8998_mss = {
>> >>          .active_clk_names = (char*[]){
>> >>                          "iface",
>> >>                          "bus",
>> >> -                       "mem",
>> >>                          "gpll0_mss",
>> >>                          "mnoc_axi",
>> >>                          "snoc_axi",
>> >> --
>> >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>> >> a Linux Foundation Collaborative Project
>> >>
>> >
>> 
>> --
>> Qualcomm Innovation Center, Inc.
>> Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
>> a Linux Foundation Collaborative Project

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.

Re: [PATCH 03/16] dt-bindings: remoteproc: qcom: Add Q6V5 Modem PIL binding for SC7180

[Rob Herring]

On Mon, 18 Nov 2019 21:43:20 +0000, Sibi Sankar wrote:
> Add a new modem compatible string for Qualcomm SC7180 SoCs and introduce
> the "qcom,halt-nav-regs" bindings needed by the modem sub-system running
> on SC7180 SoCs.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  .../bindings/remoteproc/qcom,q6v5.txt         | 23 +++++++++++++++++--
>  1 file changed, 21 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 06/16] dt-bindings: remoteproc: qcom: Add power-domain bindings for Q6V5 PAS

[Rob Herring]

On Mon, 18 Nov 2019 21:43:34 +0000, Sibi Sankar wrote:
> Add power-domain bindings for Q6V5 PAS on MSM8974/MSM8996/QCS404/SDM845
> SoCs.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  .../bindings/remoteproc/qcom,adsp.txt         | 23 +++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 08/16] dt-bindings: remoteproc: qcom: Add ADSP and SLPI support for MSM8998 SoC

[Rob Herring]

On Mon, 18 Nov 2019 21:43:45 +0000, Sibi Sankar wrote:
> Add ADSP and SLPI compatibles for MSM8998 SoC.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt | 7 +++++++
>  1 file changed, 7 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 10/16] dt-bindings: remoteproc: qcom: SM8150 Add ADSP, CDSP, MPSS and SLPI support

[Rob Herring]

On Mon, 18 Nov 2019 21:43:54 +0000, Sibi Sankar wrote:
> Add ADSP, CDSP, MPSS and SLPI compatibles for SM8150 SoC.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  .../devicetree/bindings/remoteproc/qcom,adsp.txt   | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 16/16] arm64: dts: qcom: sm8150: Add ADSP, CDSP, MPSS and SLPI remoteprocs

[Bjorn Andersson]

On Mon 18 Nov 13:44 PST 2019, Sibi Sankar wrote:

> Add ADSP, CDSP, MPSS and SLPI device tree nodes for SM8150 SoC.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8150-mtp.dts |  12 +++
>  arch/arm64/boot/dts/qcom/sm8150.dtsi    | 135 ++++++++++++++++++++++++
>  2 files changed, 147 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> index aa5de42fcae45..4d9bb8145dbba 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> @@ -348,6 +348,18 @@
>  	};
>  };
>  
> +&adsp_pas {
> +	status = "okay";
> +};
> +
> +&cdsp_pas {
> +	status = "okay";
> +};
> +
> +&slpi_pas {
> +	status = "okay";
> +};
> +
>  &qupv3_id_1 {
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 98a96fd1d6117..58f4ce95bd966 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -5,6 +5,8 @@
>   */
>  
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-sm8150.h>
> +#include <dt-bindings/power/qcom-aoss-qmp.h>
>  #include <dt-bindings/power/qcom-rpmpd.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
> @@ -278,6 +280,139 @@
>  		};
>  	};
>  
> +	adsp_pas: remoteproc-adsp {

Please move this in under /soc, name it "remoteproc" and slap a reg = <>
on it. Even if qcom,*-pas doesn't use the information I find it look
better in the DT and it becomes more consistent between PAS and non-PAS
targets.

Regards,
Bjorn