[PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Po Liu]

On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file.

Signed-off-by: Po Liu <po.liu@nxp.com>
---
 drivers/pci/pcie/portdrv_core.c | 31 ++++++++++++++++++++++++++++---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 32d4d0a..64833e5 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -15,6 +15,7 @@
 #include <linux/slab.h>
 #include <linux/pcieport_if.h>
 #include <linux/aer.h>
+#include <linux/of_irq.h>
 
 #include "../pci.h"
 #include "portdrv.h"
@@ -199,6 +200,28 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
 static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
 {
 	int i, irq = -1;
+	int ret;
+	struct device_node *np = NULL;
+
+	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
+		irqs[i] = 0;
+
+	if (dev->bus->dev.of_node)
+		np = dev->bus->dev.of_node;
+
+	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+	 * request irq for aer
+	 */
+	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
+			(mask & PCIE_PORT_SERVICE_PME)) {
+		ret = of_irq_get_byname(np, "aer");
+		if (ret > 0) {
+			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
+			if (dev->irq)
+				irq = dev->irq;
+			goto no_msi;
+		}
+	}
 
 	/*
 	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
@@ -224,11 +247,13 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
 		irq = dev->irq;
 
  no_msi:
-	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
-		irqs[i] = irq;
+	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
+		if (!irqs[i])
+			irqs[i] = irq;
+	}
 	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
 
-	if (irq < 0)
+	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
 		return -ENODEV;
 	return 0;
 }
-- 
2.1.0.27.g96db324

Re: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Bjorn Helgaas]

[+cc Rob]

Hi Po,

On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu wrote:
> On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> maybe there is interrupt line for aer pme etc. Search the interrupt
> number in the fdt file.

My understanding is that AER interrupt signaling can be done via INTx,
MSI, or MSI-X (PCIe spec r3.0, sec 6.2.4.1.2).  Apparently your device
doesn't support MSI or MSI-X.  Are you saying it doesn't support INTx
either?  How is the interrupt you're requesting here different from
INTx?

My guess is that your device *does* support INTx, and we should use
that.  ACPI has the generic _PRT that describes INTx routing.  There
must be something similar for DT, but I don't know what it is.  It
seems like this should be described using that DT mechanism (whatever
it is), and we shouldn't need special-case code in the portdrv code.

> Signed-off-by: Po Liu <po.liu@nxp.com>
> ---
>  drivers/pci/pcie/portdrv_core.c | 31 ++++++++++++++++++++++++++++---
>  1 file changed, 28 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
> index 32d4d0a..64833e5 100644
> --- a/drivers/pci/pcie/portdrv_core.c
> +++ b/drivers/pci/pcie/portdrv_core.c
> @@ -15,6 +15,7 @@
>  #include <linux/slab.h>
>  #include <linux/pcieport_if.h>
>  #include <linux/aer.h>
> +#include <linux/of_irq.h>
>  
>  #include "../pci.h"
>  #include "portdrv.h"
> @@ -199,6 +200,28 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
>  static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
>  {
>  	int i, irq = -1;
> +	int ret;
> +	struct device_node *np = NULL;
> +
> +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> +		irqs[i] = 0;
> +
> +	if (dev->bus->dev.of_node)
> +		np = dev->bus->dev.of_node;
> +
> +	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> +	 * request irq for aer
> +	 */
> +	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
> +			(mask & PCIE_PORT_SERVICE_PME)) {
> +		ret = of_irq_get_byname(np, "aer");
> +		if (ret > 0) {
> +			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
> +			if (dev->irq)
> +				irq = dev->irq;
> +			goto no_msi;
> +		}
> +	}
>  
>  	/*
>  	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
> @@ -224,11 +247,13 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
>  		irq = dev->irq;
>  
>   no_msi:
> -	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> -		irqs[i] = irq;
> +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
> +		if (!irqs[i])
> +			irqs[i] = irq;
> +	}
>  	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
>  
> -	if (irq < 0)
> +	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
>  		return -ENODEV;
>  	return 0;
>  }
> -- 
> 2.1.0.27.g96db324
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

RE: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Po Liu]

Hi Bjorn,


>  -----Original Message-----
>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>  Sent: Thursday, June 02, 2016 11:48 AM
>  To: Po Liu
>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Arnd Bergmann;
>  Roy Zang; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn
>  Helgaas; Shawn Guo; Mingkai Hu; Rob Herring
>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with none
>  MSI/MSI-X/INTx mode
>  
>  [+cc Rob]
>  
>  Hi Po,
>  
>  On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu wrote:
>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
>  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
>  > maybe there is interrupt line for aer pme etc. Search the interrupt
>  > number in the fdt file.
>  
>  My understanding is that AER interrupt signaling can be done via INTx,
>  MSI, or MSI-X (PCIe spec r3.0, sec 6.2.4.1.2).  Apparently your device
>  doesn't support MSI or MSI-X.  Are you saying it doesn't support INTx
>  either?  How is the interrupt you're requesting here different from INTx?

Layerscape use none of MSI or MSI-X or INTx to indicate the devices or root error
in RC mode. But use an independent SPI interrupt(arm interrupt controller) line.
And at same time, AER capability list in PCIe register descriptors. And also,
The Root Error Command/status register was proper to enable/disable the AER interrupt.

This hardware implementation make sense in some platforms, and this was described
in the function init_service_irqs() in the drivers/pci/pcie/portdrv_core.c in current
kernel as:

241      * We're not going to use MSI-X, so try MSI and fall back to INTx.     
242      * If neither MSI/MSI-X nor INTx available, try other interrupt.  On  
243      * some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode
244      */                                                                             

So I think this was the proper place to update the irq number before aer service
driver was loaded.

>  
>  My guess is that your device *does* support INTx, and we should use that.
>  ACPI has the generic _PRT that describes INTx routing.  There must be
>  something similar for DT, but I don't know what it is.  It seems like
>  this should be described using that DT mechanism (whatever it is), and
>  we shouldn't need special-case code in the portdrv code.
>  
>  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  > ---
>  >  drivers/pci/pcie/portdrv_core.c | 31 ++++++++++++++++++++++++++++---
>  >  1 file changed, 28 insertions(+), 3 deletions(-)
>  >
>  > diff --git a/drivers/pci/pcie/portdrv_core.c
>  > b/drivers/pci/pcie/portdrv_core.c index 32d4d0a..64833e5 100644
>  > --- a/drivers/pci/pcie/portdrv_core.c
>  > +++ b/drivers/pci/pcie/portdrv_core.c
>  > @@ -15,6 +15,7 @@
>  >  #include <linux/slab.h>
>  >  #include <linux/pcieport_if.h>
>  >  #include <linux/aer.h>
>  > +#include <linux/of_irq.h>
>  >
>  >  #include "../pci.h"
>  >  #include "portdrv.h"
>  > @@ -199,6 +200,28 @@ static int pcie_port_enable_msix(struct pci_dev
>  > *dev, int *vectors, int mask)  static int init_service_irqs(struct
>  > pci_dev *dev, int *irqs, int mask)  {
>  >  	int i, irq = -1;
>  > +	int ret;
>  > +	struct device_node *np = NULL;
>  > +
>  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
>  > +		irqs[i] = 0;
>  > +
>  > +	if (dev->bus->dev.of_node)
>  > +		np = dev->bus->dev.of_node;
>  > +
>  > +	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
>  > +	 * request irq for aer
>  > +	 */
>  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
>  > +			(mask & PCIE_PORT_SERVICE_PME)) {
>  > +		ret = of_irq_get_byname(np, "aer");
>  > +		if (ret > 0) {
>  > +			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
>  > +			if (dev->irq)
>  > +				irq = dev->irq;
>  > +			goto no_msi;
>  > +		}
>  > +	}
>  >
>  >  	/*
>  >  	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
>  @@
>  > -224,11 +247,13 @@ static int init_service_irqs(struct pci_dev *dev,
>  int *irqs, int mask)
>  >  		irq = dev->irq;
>  >
>  >   no_msi:
>  > -	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
>  > -		irqs[i] = irq;
>  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
>  > +		if (!irqs[i])
>  > +			irqs[i] = irq;
>  > +	}
>  >  	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
>  >
>  > -	if (irq < 0)
>  > +	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
>  >  		return -ENODEV;
>  >  	return 0;
>  >  }
>  > --
>  > 2.1.0.27.g96db324
>  >
>  >
>  > _______________________________________________
>  > linux-arm-kernel mailing list
>  > linux-arm-kernel@lists.infradead.org
>  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Bjorn Helgaas]

On Thu, Jun 02, 2016 at 05:01:19AM +0000, Po Liu wrote:
> >  -----Original Message-----
> >  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
> >  Sent: Thursday, June 02, 2016 11:48 AM
> >  To: Po Liu
> >  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> >  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Arnd Bergmann;
> >  Roy Zang; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn
> >  Helgaas; Shawn Guo; Mingkai Hu; Rob Herring
> >  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with none
> >  MSI/MSI-X/INTx mode
> >  
> >  [+cc Rob]
> >  
> >  Hi Po,
> >  
> >  On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu wrote:
> >  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> >  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> >  > maybe there is interrupt line for aer pme etc. Search the interrupt
> >  > number in the fdt file.
> >  
> >  My understanding is that AER interrupt signaling can be done via INTx,
> >  MSI, or MSI-X (PCIe spec r3.0, sec 6.2.4.1.2).  Apparently your device
> >  doesn't support MSI or MSI-X.  Are you saying it doesn't support INTx
> >  either?  How is the interrupt you're requesting here different from INTx?
> 
> Layerscape use none of MSI or MSI-X or INTx to indicate the devices
> or root error in RC mode. But use an independent SPI interrupt(arm
> interrupt controller) line.  

The Root Port is a PCI device and should follow the normal PCI rules
for interrupts.  As far as I understand, that means it should use MSI,
MSI-X, or INTx.  If your Root Port doesn't use MSI or MSI-X, it should
use INTx, the PCI_INTERRUPT_PIN register should tell us which (INTA/
INTB/etc.), and PCI_COMMAND_INTX_DISABLE should work to disable it.
That's all from the PCI point of view, of course.

What's on the other end of those interrupts is outside the scope of
PCI.  An INTx interrupt (either a conventional PCI wire or a PCIe
virtual INTx wire) might be connected to an IOAPIC, an ARM SPI, or
something else.  Drivers should not care about how it is connected,
and that's why I don't think this code really fits in portdrv.

Maybe your Root Port is non-compliant in some way and maybe we need a
quirk or something to work around that hardware defect.  But I'm not
convinced yet that we have that sort of problem.  It seems like we
just don't have the correct DT description.

> And at same time, AER capability list
> in PCIe register descriptors. And also, The Root Error
> Command/status register was proper to enable/disable the AER
> interrupt.

I'm not sure what you're saying here.  Here's what I think you said;
please correct me if I'm wrong:

  - Your Root Port has an AER capability.

  - Your Root Port does not support MSI or MSI-X.  (This would
    actually be a spec violation because the PCIe spec r3.0, sec 7.7
    says "All PCI Express device Functions that are capable of
    generating interrupts must implement MSI or MSI-X or both.")
  
  - The three enable bits in the Root Error Command Register enable or
    disable generation of interrupts.  These enable bits control all
    interrupts, whether MSI, MSI-X, or INTx.

  - The Root Error Status Register contains an "Advanced Error
    Interrupt Message Number" field, but that's only applicable if MSI
    or MSI-X is enabled, and if your device doesn't support MSI or
    MSI-X, this field doesn't apply.

> This hardware implementation make sense in some platforms, and this
> was described in the function init_service_irqs() in the
> drivers/pci/pcie/portdrv_core.c in current kernel as:

> 
> 241      * We're not going to use MSI-X, so try MSI and fall back to INTx.     
> 242      * If neither MSI/MSI-X nor INTx available, try other interrupt.  On  
> 243      * some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode
> 244      */                                                                             
> 
> So I think this was the proper place to update the irq number before aer service
> driver was loaded.
> 
> >  
> >  My guess is that your device *does* support INTx, and we should use that.
> >  ACPI has the generic _PRT that describes INTx routing.  There must be
> >  something similar for DT, but I don't know what it is.  It seems like
> >  this should be described using that DT mechanism (whatever it is), and
> >  we shouldn't need special-case code in the portdrv code.
> >  
> >  > Signed-off-by: Po Liu <po.liu@nxp.com>
> >  > ---
> >  >  drivers/pci/pcie/portdrv_core.c | 31 ++++++++++++++++++++++++++++---
> >  >  1 file changed, 28 insertions(+), 3 deletions(-)
> >  >
> >  > diff --git a/drivers/pci/pcie/portdrv_core.c
> >  > b/drivers/pci/pcie/portdrv_core.c index 32d4d0a..64833e5 100644
> >  > --- a/drivers/pci/pcie/portdrv_core.c
> >  > +++ b/drivers/pci/pcie/portdrv_core.c
> >  > @@ -15,6 +15,7 @@
> >  >  #include <linux/slab.h>
> >  >  #include <linux/pcieport_if.h>
> >  >  #include <linux/aer.h>
> >  > +#include <linux/of_irq.h>
> >  >
> >  >  #include "../pci.h"
> >  >  #include "portdrv.h"
> >  > @@ -199,6 +200,28 @@ static int pcie_port_enable_msix(struct pci_dev
> >  > *dev, int *vectors, int mask)  static int init_service_irqs(struct
> >  > pci_dev *dev, int *irqs, int mask)  {
> >  >  	int i, irq = -1;
> >  > +	int ret;
> >  > +	struct device_node *np = NULL;
> >  > +
> >  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> >  > +		irqs[i] = 0;
> >  > +
> >  > +	if (dev->bus->dev.of_node)
> >  > +		np = dev->bus->dev.of_node;
> >  > +
> >  > +	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> >  > +	 * request irq for aer
> >  > +	 */
> >  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
> >  > +			(mask & PCIE_PORT_SERVICE_PME)) {
> >  > +		ret = of_irq_get_byname(np, "aer");
> >  > +		if (ret > 0) {
> >  > +			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
> >  > +			if (dev->irq)
> >  > +				irq = dev->irq;
> >  > +			goto no_msi;
> >  > +		}
> >  > +	}
> >  >
> >  >  	/*
> >  >  	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
> >  @@
> >  > -224,11 +247,13 @@ static int init_service_irqs(struct pci_dev *dev,
> >  int *irqs, int mask)
> >  >  		irq = dev->irq;
> >  >
> >  >   no_msi:
> >  > -	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> >  > -		irqs[i] = irq;
> >  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
> >  > +		if (!irqs[i])
> >  > +			irqs[i] = irq;
> >  > +	}
> >  >  	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
> >  >
> >  > -	if (irq < 0)
> >  > +	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
> >  >  		return -ENODEV;
> >  >  	return 0;
> >  >  }
> >  > --
> >  > 2.1.0.27.g96db324
> >  >
> >  >
> >  > _______________________________________________
> >  > linux-arm-kernel mailing list
> >  > linux-arm-kernel@lists.infradead.org
> >  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Murali Karicheri]

On 06/02/2016 09:55 AM, Bjorn Helgaas wrote:
> On Thu, Jun 02, 2016 at 05:01:19AM +0000, Po Liu wrote:
>>>  -----Original Message-----
>>>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>>>  Sent: Thursday, June 02, 2016 11:48 AM
>>>  To: Po Liu
>>>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>>>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Arnd Bergmann;
>>>  Roy Zang; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn
>>>  Helgaas; Shawn Guo; Mingkai Hu; Rob Herring
>>>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with none
>>>  MSI/MSI-X/INTx mode
>>>  
>>>  [+cc Rob]
>>>  
>>>  Hi Po,
>>>  
>>>  On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu wrote:
>>>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
>>>  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
>>>  > maybe there is interrupt line for aer pme etc. Search the interrupt
>>>  > number in the fdt file.
>>>  
>>>  My understanding is that AER interrupt signaling can be done via INTx,
>>>  MSI, or MSI-X (PCIe spec r3.0, sec 6.2.4.1.2).  Apparently your device
>>>  doesn't support MSI or MSI-X.  Are you saying it doesn't support INTx
>>>  either?  How is the interrupt you're requesting here different from INTx?
>>
>> Layerscape use none of MSI or MSI-X or INTx to indicate the devices
>> or root error in RC mode. But use an independent SPI interrupt(arm
>> interrupt controller) line.  
> 
> The Root Port is a PCI device and should follow the normal PCI rules
> for interrupts.  As far as I understand, that means it should use MSI,
> MSI-X, or INTx.  If your Root Port doesn't use MSI or MSI-X, it should
> use INTx, the PCI_INTERRUPT_PIN register should tell us which (INTA/
> INTB/etc.), and PCI_COMMAND_INTX_DISABLE should work to disable it.
> That's all from the PCI point of view, of course.
> 
Bjorn.

I am faced with the same issue on Keystone PCI hardware and it has been
on my TODO list  for quite some time. Keystone PCI hardware also doesn't
use MSI or MSI-X or INTx for reporting errors received at the root port,
but use a platform interrupt instead (not complaint to PCI standard as
per PCI base spec). So I would need similar change to have the error
interrupt passed to the aer driver. So there are hardware out there
like Keystone which requires to support this through platform IRQ.

> What's on the other end of those interrupts is outside the scope of
> PCI.  An INTx interrupt (either a conventional PCI wire or a PCIe
> virtual INTx wire) might be connected to an IOAPIC, an ARM SPI, or
> something else.  Drivers should not care about how it is connected,
> and that's why I don't think this code really fits in portdrv.
> 
> Maybe your Root Port is non-compliant in some way and maybe we need a
> quirk or something to work around that hardware defect.  But I'm not
> convinced yet that we have that sort of problem.  It seems like we
> just don't have the correct DT description.

Is quirk is what is suggested here to support this?

Murali
> 
>> And at same time, AER capability list
>> in PCIe register descriptors. And also, The Root Error
>> Command/status register was proper to enable/disable the AER
>> interrupt.
> 
> I'm not sure what you're saying here.  Here's what I think you said;
> please correct me if I'm wrong:
> 
>   - Your Root Port has an AER capability.
> 
>   - Your Root Port does not support MSI or MSI-X.  (This would
>     actually be a spec violation because the PCIe spec r3.0, sec 7.7
>     says "All PCI Express device Functions that are capable of
>     generating interrupts must implement MSI or MSI-X or both.")
>   
>   - The three enable bits in the Root Error Command Register enable or
>     disable generation of interrupts.  These enable bits control all
>     interrupts, whether MSI, MSI-X, or INTx.
> 
>   - The Root Error Status Register contains an "Advanced Error
>     Interrupt Message Number" field, but that's only applicable if MSI
>     or MSI-X is enabled, and if your device doesn't support MSI or
>     MSI-X, this field doesn't apply.
> 
>> This hardware implementation make sense in some platforms, and this
>> was described in the function init_service_irqs() in the
>> drivers/pci/pcie/portdrv_core.c in current kernel as:
> 
>>
>> 241      * We're not going to use MSI-X, so try MSI and fall back to INTx.     
>> 242      * If neither MSI/MSI-X nor INTx available, try other interrupt.  On  
>> 243      * some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode
>> 244      */                                                                             
>>
>> So I think this was the proper place to update the irq number before aer service
>> driver was loaded.
>>
>>>  
>>>  My guess is that your device *does* support INTx, and we should use that.
>>>  ACPI has the generic _PRT that describes INTx routing.  There must be
>>>  something similar for DT, but I don't know what it is.  It seems like
>>>  this should be described using that DT mechanism (whatever it is), and
>>>  we shouldn't need special-case code in the portdrv code.
>>>  
>>>  > Signed-off-by: Po Liu <po.liu@nxp.com>
>>>  > ---
>>>  >  drivers/pci/pcie/portdrv_core.c | 31 ++++++++++++++++++++++++++++---
>>>  >  1 file changed, 28 insertions(+), 3 deletions(-)
>>>  >
>>>  > diff --git a/drivers/pci/pcie/portdrv_core.c
>>>  > b/drivers/pci/pcie/portdrv_core.c index 32d4d0a..64833e5 100644
>>>  > --- a/drivers/pci/pcie/portdrv_core.c
>>>  > +++ b/drivers/pci/pcie/portdrv_core.c
>>>  > @@ -15,6 +15,7 @@
>>>  >  #include <linux/slab.h>
>>>  >  #include <linux/pcieport_if.h>
>>>  >  #include <linux/aer.h>
>>>  > +#include <linux/of_irq.h>
>>>  >
>>>  >  #include "../pci.h"
>>>  >  #include "portdrv.h"
>>>  > @@ -199,6 +200,28 @@ static int pcie_port_enable_msix(struct pci_dev
>>>  > *dev, int *vectors, int mask)  static int init_service_irqs(struct
>>>  > pci_dev *dev, int *irqs, int mask)  {
>>>  >  	int i, irq = -1;
>>>  > +	int ret;
>>>  > +	struct device_node *np = NULL;
>>>  > +
>>>  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
>>>  > +		irqs[i] = 0;
>>>  > +
>>>  > +	if (dev->bus->dev.of_node)
>>>  > +		np = dev->bus->dev.of_node;
>>>  > +
>>>  > +	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
>>>  > +	 * request irq for aer
>>>  > +	 */
>>>  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
>>>  > +			(mask & PCIE_PORT_SERVICE_PME)) {
>>>  > +		ret = of_irq_get_byname(np, "aer");
>>>  > +		if (ret > 0) {
>>>  > +			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
>>>  > +			if (dev->irq)
>>>  > +				irq = dev->irq;
>>>  > +			goto no_msi;
>>>  > +		}
>>>  > +	}
>>>  >
>>>  >  	/*
>>>  >  	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
>>>  @@
>>>  > -224,11 +247,13 @@ static int init_service_irqs(struct pci_dev *dev,
>>>  int *irqs, int mask)
>>>  >  		irq = dev->irq;
>>>  >
>>>  >   no_msi:
>>>  > -	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
>>>  > -		irqs[i] = irq;
>>>  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
>>>  > +		if (!irqs[i])
>>>  > +			irqs[i] = irq;
>>>  > +	}
>>>  >  	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
>>>  >
>>>  > -	if (irq < 0)
>>>  > +	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
>>>  >  		return -ENODEV;
>>>  >  	return 0;
>>>  >  }
>>>  > --
>>>  > 2.1.0.27.g96db324
>>>  >
>>>  >
>>>  > _______________________________________________
>>>  > linux-arm-kernel mailing list
>>>  > linux-arm-kernel@lists.infradead.org
>>>  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


-- 
Murali Karicheri
Linux Kernel, Keystone

Re: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Bjorn Helgaas]

On Thu, Jun 02, 2016 at 11:37:28AM -0400, Murali Karicheri wrote:
> On 06/02/2016 09:55 AM, Bjorn Helgaas wrote:
> > On Thu, Jun 02, 2016 at 05:01:19AM +0000, Po Liu wrote:
> >>>  -----Original Message-----
> >>>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
> >>>  Sent: Thursday, June 02, 2016 11:48 AM
> >>>  To: Po Liu
> >>>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> >>>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Arnd Bergmann;
> >>>  Roy Zang; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn
> >>>  Helgaas; Shawn Guo; Mingkai Hu; Rob Herring
> >>>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with none
> >>>  MSI/MSI-X/INTx mode
> >>>  
> >>>  [+cc Rob]
> >>>  
> >>>  Hi Po,
> >>>  
> >>>  On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu wrote:
> >>>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> >>>  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> >>>  > maybe there is interrupt line for aer pme etc. Search the interrupt
> >>>  > number in the fdt file.
> >>>  
> >>>  My understanding is that AER interrupt signaling can be done via INTx,
> >>>  MSI, or MSI-X (PCIe spec r3.0, sec 6.2.4.1.2).  Apparently your device
> >>>  doesn't support MSI or MSI-X.  Are you saying it doesn't support INTx
> >>>  either?  How is the interrupt you're requesting here different from INTx?
> >>
> >> Layerscape use none of MSI or MSI-X or INTx to indicate the devices
> >> or root error in RC mode. But use an independent SPI interrupt(arm
> >> interrupt controller) line.  
> > 
> > The Root Port is a PCI device and should follow the normal PCI rules
> > for interrupts.  As far as I understand, that means it should use MSI,
> > MSI-X, or INTx.  If your Root Port doesn't use MSI or MSI-X, it should
> > use INTx, the PCI_INTERRUPT_PIN register should tell us which (INTA/
> > INTB/etc.), and PCI_COMMAND_INTX_DISABLE should work to disable it.
> > That's all from the PCI point of view, of course.
> 
> I am faced with the same issue on Keystone PCI hardware and it has been
> on my TODO list  for quite some time. Keystone PCI hardware also doesn't
> use MSI or MSI-X or INTx for reporting errors received at the root port,
> but use a platform interrupt instead (not complaint to PCI standard as
> per PCI base spec). So I would need similar change to have the error
> interrupt passed to the aer driver. So there are hardware out there
> like Keystone which requires to support this through platform IRQ.

This is not a new area of the spec, and it's hard for me to believe
that these two new PCIe controllers are both broken the same way
(although I guess both are DesignWare-based, so maybe this is the same
underlying problem in both cases?).  I think it's more likely that we
just haven't figured out the right way to describe this in the DT.

I assume you have a Root Port with an AER capability, no MSI
capability, and no MSI-X capability, right?  What does its Interrupt
Pin register contain?  If it's zero, it doesn't use INTx either, so
according to the spec it should generate no interrupts.

But if Interrupt Pin is non-zero, that means the Root Port should be
able to generate virtual INTx interrupts.  Presumably the Root Complex
connects those interrupts to something; maybe to your platform
interrupt?

PCI doesn't say anything about an interrupt after it leaves the Root
Complex, so the fact that it's connected to a "platform interrupt" or
"SPI interrupt" or "IOAPIC interrupt" doesn't make it non-compliant.
Shouldn't we be able to use the interrupt-map and related DT
properties to express the fact that Root Port virtual INTx is routed
to platform interrupt Y, even without any special-case code in
portdrv?

> > What's on the other end of those interrupts is outside the scope of
> > PCI.  An INTx interrupt (either a conventional PCI wire or a PCIe
> > virtual INTx wire) might be connected to an IOAPIC, an ARM SPI, or
> > something else.  Drivers should not care about how it is connected,
> > and that's why I don't think this code really fits in portdrv.
> > 
> > Maybe your Root Port is non-compliant in some way and maybe we need a
> > quirk or something to work around that hardware defect.  But I'm not
> > convinced yet that we have that sort of problem.  It seems like we
> > just don't have the correct DT description.
> 
> Is quirk is what is suggested here to support this?

No, I don't understand the problem yet, so I'm not ready to suggest a
solution.

> >> And at same time, AER capability list
> >> in PCIe register descriptors. And also, The Root Error
> >> Command/status register was proper to enable/disable the AER
> >> interrupt.
> > 
> > I'm not sure what you're saying here.  Here's what I think you said;
> > please correct me if I'm wrong:
> > 
> >   - Your Root Port has an AER capability.
> > 
> >   - Your Root Port does not support MSI or MSI-X.  (This would
> >     actually be a spec violation because the PCIe spec r3.0, sec 7.7
> >     says "All PCI Express device Functions that are capable of
> >     generating interrupts must implement MSI or MSI-X or both.")
> >   
> >   - The three enable bits in the Root Error Command Register enable or
> >     disable generation of interrupts.  These enable bits control all
> >     interrupts, whether MSI, MSI-X, or INTx.
> > 
> >   - The Root Error Status Register contains an "Advanced Error
> >     Interrupt Message Number" field, but that's only applicable if MSI
> >     or MSI-X is enabled, and if your device doesn't support MSI or
> >     MSI-X, this field doesn't apply.
> > 
> >> This hardware implementation make sense in some platforms, and this
> >> was described in the function init_service_irqs() in the
> >> drivers/pci/pcie/portdrv_core.c in current kernel as:
> > 
> >>
> >> 241      * We're not going to use MSI-X, so try MSI and fall back to INTx.     
> >> 242      * If neither MSI/MSI-X nor INTx available, try other interrupt.  On  
> >> 243      * some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode
> >> 244      */                                                                             
> >>
> >> So I think this was the proper place to update the irq number before aer service
> >> driver was loaded.
> >>
> >>>  
> >>>  My guess is that your device *does* support INTx, and we should use that.
> >>>  ACPI has the generic _PRT that describes INTx routing.  There must be
> >>>  something similar for DT, but I don't know what it is.  It seems like
> >>>  this should be described using that DT mechanism (whatever it is), and
> >>>  we shouldn't need special-case code in the portdrv code.
> >>>  
> >>>  > Signed-off-by: Po Liu <po.liu@nxp.com>
> >>>  > ---
> >>>  >  drivers/pci/pcie/portdrv_core.c | 31 ++++++++++++++++++++++++++++---
> >>>  >  1 file changed, 28 insertions(+), 3 deletions(-)
> >>>  >
> >>>  > diff --git a/drivers/pci/pcie/portdrv_core.c
> >>>  > b/drivers/pci/pcie/portdrv_core.c index 32d4d0a..64833e5 100644
> >>>  > --- a/drivers/pci/pcie/portdrv_core.c
> >>>  > +++ b/drivers/pci/pcie/portdrv_core.c
> >>>  > @@ -15,6 +15,7 @@
> >>>  >  #include <linux/slab.h>
> >>>  >  #include <linux/pcieport_if.h>
> >>>  >  #include <linux/aer.h>
> >>>  > +#include <linux/of_irq.h>
> >>>  >
> >>>  >  #include "../pci.h"
> >>>  >  #include "portdrv.h"
> >>>  > @@ -199,6 +200,28 @@ static int pcie_port_enable_msix(struct pci_dev
> >>>  > *dev, int *vectors, int mask)  static int init_service_irqs(struct
> >>>  > pci_dev *dev, int *irqs, int mask)  {
> >>>  >  	int i, irq = -1;
> >>>  > +	int ret;
> >>>  > +	struct device_node *np = NULL;
> >>>  > +
> >>>  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> >>>  > +		irqs[i] = 0;
> >>>  > +
> >>>  > +	if (dev->bus->dev.of_node)
> >>>  > +		np = dev->bus->dev.of_node;
> >>>  > +
> >>>  > +	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> >>>  > +	 * request irq for aer
> >>>  > +	 */
> >>>  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
> >>>  > +			(mask & PCIE_PORT_SERVICE_PME)) {
> >>>  > +		ret = of_irq_get_byname(np, "aer");
> >>>  > +		if (ret > 0) {
> >>>  > +			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
> >>>  > +			if (dev->irq)
> >>>  > +				irq = dev->irq;
> >>>  > +			goto no_msi;
> >>>  > +		}
> >>>  > +	}
> >>>  >
> >>>  >  	/*
> >>>  >  	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
> >>>  @@
> >>>  > -224,11 +247,13 @@ static int init_service_irqs(struct pci_dev *dev,
> >>>  int *irqs, int mask)
> >>>  >  		irq = dev->irq;
> >>>  >
> >>>  >   no_msi:
> >>>  > -	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> >>>  > -		irqs[i] = irq;
> >>>  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
> >>>  > +		if (!irqs[i])
> >>>  > +			irqs[i] = irq;
> >>>  > +	}
> >>>  >  	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
> >>>  >
> >>>  > -	if (irq < 0)
> >>>  > +	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
> >>>  >  		return -ENODEV;
> >>>  >  	return 0;
> >>>  >  }
> >>>  > --
> >>>  > 2.1.0.27.g96db324
> >>>  >
> >>>  >
> >>>  > _______________________________________________
> >>>  > linux-arm-kernel mailing list
> >>>  > linux-arm-kernel@lists.infradead.org
> >>>  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> > 
> 
> 
> -- 
> Murali Karicheri
> Linux Kernel, Keystone

Re: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Murali Karicheri]

Po,

Sorry to hijack your discussion, but the problem seems to be same for
Keystone PCI controller which is also designware (old version) based.

On 06/03/2016 12:09 AM, Bjorn Helgaas wrote:
> On Thu, Jun 02, 2016 at 11:37:28AM -0400, Murali Karicheri wrote:
>> On 06/02/2016 09:55 AM, Bjorn Helgaas wrote:
>>> On Thu, Jun 02, 2016 at 05:01:19AM +0000, Po Liu wrote:
>>>>>  -----Original Message-----
>>>>>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>>>>>  Sent: Thursday, June 02, 2016 11:48 AM
>>>>>  To: Po Liu
>>>>>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>>>>>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Arnd Bergmann;
>>>>>  Roy Zang; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn
>>>>>  Helgaas; Shawn Guo; Mingkai Hu; Rob Herring
>>>>>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with none
>>>>>  MSI/MSI-X/INTx mode
>>>>>  
>>>>>  [+cc Rob]
>>>>>  
>>>>>  Hi Po,
>>>>>  
>>>>>  On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu wrote:
>>>>>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
>>>>>  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
>>>>>  > maybe there is interrupt line for aer pme etc. Search the interrupt
>>>>>  > number in the fdt file.
>>>>>  
>>>>>  My understanding is that AER interrupt signaling can be done via INTx,
>>>>>  MSI, or MSI-X (PCIe spec r3.0, sec 6.2.4.1.2).  Apparently your device
>>>>>  doesn't support MSI or MSI-X.  Are you saying it doesn't support INTx
>>>>>  either?  How is the interrupt you're requesting here different from INTx?
>>>>
>>>> Layerscape use none of MSI or MSI-X or INTx to indicate the devices
>>>> or root error in RC mode. But use an independent SPI interrupt(arm
>>>> interrupt controller) line.  
>>>
>>> The Root Port is a PCI device and should follow the normal PCI rules
>>> for interrupts.  As far as I understand, that means it should use MSI,
>>> MSI-X, or INTx.  If your Root Port doesn't use MSI or MSI-X, it should
>>> use INTx, the PCI_INTERRUPT_PIN register should tell us which (INTA/
>>> INTB/etc.), and PCI_COMMAND_INTX_DISABLE should work to disable it.
>>> That's all from the PCI point of view, of course.
>>
>> I am faced with the same issue on Keystone PCI hardware and it has been
>> on my TODO list  for quite some time. Keystone PCI hardware also doesn't
>> use MSI or MSI-X or INTx for reporting errors received at the root port,
>> but use a platform interrupt instead (not complaint to PCI standard as
>> per PCI base spec). So I would need similar change to have the error
>> interrupt passed to the aer driver. So there are hardware out there
>> like Keystone which requires to support this through platform IRQ.
> 
> This is not a new area of the spec, and it's hard for me to believe
> that these two new PCIe controllers are both broken the same way
> (although I guess both are DesignWare-based, so maybe this is the same
> underlying problem in both cases?).  I think it's more likely that we
> just haven't figured out the right way to describe this in the DT.

Keystone is using an older version of the designware IP and it implements
all of the interrupts in the application register space unlike other
newer version of the hardware. So I assume, the version used on Layerscape
is also an older version and the both have same issue in terms of 
non standard platform interrupt used for error reporting.

> 
> I assume you have a Root Port with an AER capability, no MSI
> capability, and no MSI-X capability, right? 

Has AER capability and both MSI and INTx (legacy) capability

> What does its Interrupt
> Pin register contain?  If it's zero, it doesn't use INTx either, so
> according to the spec it should generate no interrupts.
> 
At address offset 0x3C by default has a value of 1, but it is writable
by software. So default is INTx A.

> But if Interrupt Pin is non-zero, that means the Root Port should be
> able to generate virtual INTx interrupts.  Presumably the Root Complex
> connects those interrupts to something; maybe to your platform
> interrupt?

Probably that is what is happening. Both Power management and Error
interrupts are raised on platform interrupt lines.

12 Error Interrupts

[0] System error (OR of fatal, nonfatal, correctable errors) (RC mode only)
[1] PCIe fatal error (RC mode only)
[2] PCIe non-fatal error (RC mode only)
[3] PCIe correctable error (RC mode only)
[4] AXI Error due to fatal condition in AXI bridge (EP/RC modes)
[5] PCIe advanced error (RC mode only)

13 Power management and reset event interrupts

[0] Power management turn-off message interrupt (EP mode only)
[1] Power management ack message interrupt (RC mode only)
[2] Power management event interrupt (RC mode only)
[3] Link request reset interrupt (hot reset or link down) (RC mode only)

> 
> PCI doesn't say anything about an interrupt after it leaves the Root
> Complex, so the fact that it's connected to a "platform interrupt" or
> "SPI interrupt" or "IOAPIC interrupt" doesn't make it non-compliant.
> Shouldn't we be able to use the interrupt-map and related DT
> properties to express the fact that Root Port virtual INTx is routed
> to platform interrupt Y, even without any special-case code in
> portdrv?

My understanding is if RC also raise interrupt on INTx, then below 
map make sense, where either EP or RC can raise interrupt and the
line will be muxed for interrupt from EP or RC port.

Here is the DT entry in PCIE keystone for Legacy interrupt mapping
to host interrupt. 
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 7>;
                        interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
                                        <0 0 0 2 &pcie_intc0 1>, /* INT B */
                                        <0 0 0 3 &pcie_intc0 2>, /* INT C */
                                        <0 0 0 4 &pcie_intc0 3>; /* INT D */


And  then

                        pcie_intc0: legacy-interrupt-controller {
                                interrupt-controller;
                                #interrupt-cells = <1>;
                                interrupt-parent = <&gic>;
                                interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
                                        <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
                                        <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
                                        <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>;
                        };

So if RC interrupt for Power management and Error interrupt is a separate
line, how can software describe that using the above interrupt map?

Murali
> 
>>> What's on the other end of those interrupts is outside the scope of
>>> PCI.  An INTx interrupt (either a conventional PCI wire or a PCIe
>>> virtual INTx wire) might be connected to an IOAPIC, an ARM SPI, or
>>> something else.  Drivers should not care about how it is connected,
>>> and that's why I don't think this code really fits in portdrv.
>>>
>>> Maybe your Root Port is non-compliant in some way and maybe we need a
>>> quirk or something to work around that hardware defect.  But I'm not
>>> convinced yet that we have that sort of problem.  It seems like we
>>> just don't have the correct DT description.
>>
>> Is quirk is what is suggested here to support this?
> 
> No, I don't understand the problem yet, so I'm not ready to suggest a
> solution.
> 
>>>> And at same time, AER capability list
>>>> in PCIe register descriptors. And also, The Root Error
>>>> Command/status register was proper to enable/disable the AER
>>>> interrupt.
>>>
>>> I'm not sure what you're saying here.  Here's what I think you said;
>>> please correct me if I'm wrong:
>>>
>>>   - Your Root Port has an AER capability.
>>>
>>>   - Your Root Port does not support MSI or MSI-X.  (This would
>>>     actually be a spec violation because the PCIe spec r3.0, sec 7.7
>>>     says "All PCI Express device Functions that are capable of
>>>     generating interrupts must implement MSI or MSI-X or both.")
>>>   
>>>   - The three enable bits in the Root Error Command Register enable or
>>>     disable generation of interrupts.  These enable bits control all
>>>     interrupts, whether MSI, MSI-X, or INTx.
>>>
>>>   - The Root Error Status Register contains an "Advanced Error
>>>     Interrupt Message Number" field, but that's only applicable if MSI
>>>     or MSI-X is enabled, and if your device doesn't support MSI or
>>>     MSI-X, this field doesn't apply.
>>>
>>>> This hardware implementation make sense in some platforms, and this
>>>> was described in the function init_service_irqs() in the
>>>> drivers/pci/pcie/portdrv_core.c in current kernel as:
>>>
>>>>
>>>> 241      * We're not going to use MSI-X, so try MSI and fall back to INTx.     
>>>> 242      * If neither MSI/MSI-X nor INTx available, try other interrupt.  On  
>>>> 243      * some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode
>>>> 244      */                                                                             
>>>>
>>>> So I think this was the proper place to update the irq number before aer service
>>>> driver was loaded.
>>>>
>>>>>  
>>>>>  My guess is that your device *does* support INTx, and we should use that.
>>>>>  ACPI has the generic _PRT that describes INTx routing.  There must be
>>>>>  something similar for DT, but I don't know what it is.  It seems like
>>>>>  this should be described using that DT mechanism (whatever it is), and
>>>>>  we shouldn't need special-case code in the portdrv code.
>>>>>  
>>>>>  > Signed-off-by: Po Liu <po.liu@nxp.com>
>>>>>  > ---
>>>>>  >  drivers/pci/pcie/portdrv_core.c | 31 ++++++++++++++++++++++++++++---
>>>>>  >  1 file changed, 28 insertions(+), 3 deletions(-)
>>>>>  >
>>>>>  > diff --git a/drivers/pci/pcie/portdrv_core.c
>>>>>  > b/drivers/pci/pcie/portdrv_core.c index 32d4d0a..64833e5 100644
>>>>>  > --- a/drivers/pci/pcie/portdrv_core.c
>>>>>  > +++ b/drivers/pci/pcie/portdrv_core.c
>>>>>  > @@ -15,6 +15,7 @@
>>>>>  >  #include <linux/slab.h>
>>>>>  >  #include <linux/pcieport_if.h>
>>>>>  >  #include <linux/aer.h>
>>>>>  > +#include <linux/of_irq.h>
>>>>>  >
>>>>>  >  #include "../pci.h"
>>>>>  >  #include "portdrv.h"
>>>>>  > @@ -199,6 +200,28 @@ static int pcie_port_enable_msix(struct pci_dev
>>>>>  > *dev, int *vectors, int mask)  static int init_service_irqs(struct
>>>>>  > pci_dev *dev, int *irqs, int mask)  {
>>>>>  >  	int i, irq = -1;
>>>>>  > +	int ret;
>>>>>  > +	struct device_node *np = NULL;
>>>>>  > +
>>>>>  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
>>>>>  > +		irqs[i] = 0;
>>>>>  > +
>>>>>  > +	if (dev->bus->dev.of_node)
>>>>>  > +		np = dev->bus->dev.of_node;
>>>>>  > +
>>>>>  > +	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
>>>>>  > +	 * request irq for aer
>>>>>  > +	 */
>>>>>  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
>>>>>  > +			(mask & PCIE_PORT_SERVICE_PME)) {
>>>>>  > +		ret = of_irq_get_byname(np, "aer");
>>>>>  > +		if (ret > 0) {
>>>>>  > +			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
>>>>>  > +			if (dev->irq)
>>>>>  > +				irq = dev->irq;
>>>>>  > +			goto no_msi;
>>>>>  > +		}
>>>>>  > +	}
>>>>>  >
>>>>>  >  	/*
>>>>>  >  	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
>>>>>  @@
>>>>>  > -224,11 +247,13 @@ static int init_service_irqs(struct pci_dev *dev,
>>>>>  int *irqs, int mask)
>>>>>  >  		irq = dev->irq;
>>>>>  >
>>>>>  >   no_msi:
>>>>>  > -	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
>>>>>  > -		irqs[i] = irq;
>>>>>  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
>>>>>  > +		if (!irqs[i])
>>>>>  > +			irqs[i] = irq;
>>>>>  > +	}
>>>>>  >  	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
>>>>>  >
>>>>>  > -	if (irq < 0)
>>>>>  > +	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
>>>>>  >  		return -ENODEV;
>>>>>  >  	return 0;
>>>>>  >  }
>>>>>  > --
>>>>>  > 2.1.0.27.g96db324
>>>>>  >
>>>>>  >
>>>>>  > _______________________________________________
>>>>>  > linux-arm-kernel mailing list
>>>>>  > linux-arm-kernel@lists.infradead.org
>>>>>  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>
>>
>>
>> -- 
>> Murali Karicheri
>> Linux Kernel, Keystone


-- 
Murali Karicheri
Linux Kernel, Keystone

Re: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Bjorn Helgaas]

On Fri, Jun 03, 2016 at 01:31:11PM -0400, Murali Karicheri wrote:
> Po,
> 
> Sorry to hijack your discussion, but the problem seems to be same for
> Keystone PCI controller which is also designware (old version) based.
> 
> On 06/03/2016 12:09 AM, Bjorn Helgaas wrote:
> > On Thu, Jun 02, 2016 at 11:37:28AM -0400, Murali Karicheri wrote:
> >> On 06/02/2016 09:55 AM, Bjorn Helgaas wrote:
> >>> On Thu, Jun 02, 2016 at 05:01:19AM +0000, Po Liu wrote:
> >>>>>  -----Original Message-----
> >>>>>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
> >>>>>  Sent: Thursday, June 02, 2016 11:48 AM
> >>>>>  To: Po Liu
> >>>>>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> >>>>>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Arnd Bergmann;
> >>>>>  Roy Zang; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn
> >>>>>  Helgaas; Shawn Guo; Mingkai Hu; Rob Herring
> >>>>>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with none
> >>>>>  MSI/MSI-X/INTx mode
> >>>>>  
> >>>>>  [+cc Rob]
> >>>>>  
> >>>>>  Hi Po,
> >>>>>  
> >>>>>  On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu wrote:
> >>>>>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> >>>>>  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> >>>>>  > maybe there is interrupt line for aer pme etc. Search the interrupt
> >>>>>  > number in the fdt file.
> >>>>>  
> >>>>>  My understanding is that AER interrupt signaling can be done via INTx,
> >>>>>  MSI, or MSI-X (PCIe spec r3.0, sec 6.2.4.1.2).  Apparently your device
> >>>>>  doesn't support MSI or MSI-X.  Are you saying it doesn't support INTx
> >>>>>  either?  How is the interrupt you're requesting here different from INTx?
> >>>>
> >>>> Layerscape use none of MSI or MSI-X or INTx to indicate the devices
> >>>> or root error in RC mode. But use an independent SPI interrupt(arm
> >>>> interrupt controller) line.  
> >>>
> >>> The Root Port is a PCI device and should follow the normal PCI rules
> >>> for interrupts.  As far as I understand, that means it should use MSI,
> >>> MSI-X, or INTx.  If your Root Port doesn't use MSI or MSI-X, it should
> >>> use INTx, the PCI_INTERRUPT_PIN register should tell us which (INTA/
> >>> INTB/etc.), and PCI_COMMAND_INTX_DISABLE should work to disable it.
> >>> That's all from the PCI point of view, of course.
> >>
> >> I am faced with the same issue on Keystone PCI hardware and it has been
> >> on my TODO list  for quite some time. Keystone PCI hardware also doesn't
> >> use MSI or MSI-X or INTx for reporting errors received at the root port,
> >> but use a platform interrupt instead (not complaint to PCI standard as
> >> per PCI base spec). So I would need similar change to have the error
> >> interrupt passed to the aer driver. So there are hardware out there
> >> like Keystone which requires to support this through platform IRQ.
> > 
> > This is not a new area of the spec, and it's hard for me to believe
> > that these two new PCIe controllers are both broken the same way
> > (although I guess both are DesignWare-based, so maybe this is the same
> > underlying problem in both cases?).  I think it's more likely that we
> > just haven't figured out the right way to describe this in the DT.
> 
> Keystone is using an older version of the designware IP and it implements
> all of the interrupts in the application register space unlike other
> newer version of the hardware. So I assume, the version used on Layerscape
> is also an older version and the both have same issue in terms of 
> non standard platform interrupt used for error reporting.
> 
> > I assume you have a Root Port with an AER capability, no MSI
> > capability, and no MSI-X capability, right? 
> 
> Has AER capability and both MSI and INTx (legacy) capability
> 
> > What does its Interrupt
> > Pin register contain?  If it's zero, it doesn't use INTx either, so
> > according to the spec it should generate no interrupts.
> > 
> At address offset 0x3C by default has a value of 1, but it is writable
> by software. So default is INTx A.

0x3c is the Interrupt *Line*, which is read/write.  The Interrupt
*Pin* is at 0x3d and should be read-only.

Does your Keystone driver support MSI?  If so, since your Root Port
supports MSI, I would think we would use that by default, and the INTx
stuff wouldn't even matter.

> > But if Interrupt Pin is non-zero, that means the Root Port should be
> > able to generate virtual INTx interrupts.  Presumably the Root Complex
> > connects those interrupts to something; maybe to your platform
> > interrupt?
> 
> Probably that is what is happening. Both Power management and Error
> interrupts are raised on platform interrupt lines.
> 
> 12 Error Interrupts
> 
> [0] System error (OR of fatal, nonfatal, correctable errors) (RC mode only)
> [1] PCIe fatal error (RC mode only)
> [2] PCIe non-fatal error (RC mode only)
> [3] PCIe correctable error (RC mode only)
> [4] AXI Error due to fatal condition in AXI bridge (EP/RC modes)
> [5] PCIe advanced error (RC mode only)
> 
> 13 Power management and reset event interrupts
> 
> [0] Power management turn-off message interrupt (EP mode only)
> [1] Power management ack message interrupt (RC mode only)
> [2] Power management event interrupt (RC mode only)
> [3] Link request reset interrupt (hot reset or link down) (RC mode only)
>
> > PCI doesn't say anything about an interrupt after it leaves the Root
> > Complex, so the fact that it's connected to a "platform interrupt" or
> > "SPI interrupt" or "IOAPIC interrupt" doesn't make it non-compliant.
> > Shouldn't we be able to use the interrupt-map and related DT
> > properties to express the fact that Root Port virtual INTx is routed
> > to platform interrupt Y, even without any special-case code in
> > portdrv?
> 
> My understanding is if RC also raise interrupt on INTx, then below 
> map make sense, where either EP or RC can raise interrupt and the
> line will be muxed for interrupt from EP or RC port.

I'm sorry, I didn't quite catch your meaning here, so let me try to
clarify some terminology.  Maybe we'll eventually blunder into a
common understanding :)

INTx is a PCI concept and only means something in the PCI hierarchy.
The RC would *receive* virtual INTx interrupts from the PCI hierarchy
and turn them into some platform-specific interrupt (not INTx) on the
upstream side.

So strictly speaking, the RC might raise platform-specific interrupts
when it receives INTx interrupts, but it would not raise any INTx
interrupts itself.

> Here is the DT entry in PCIE keystone for Legacy interrupt mapping
> to host interrupt. 
>                         #interrupt-cells = <1>;
>                         interrupt-map-mask = <0 0 0 7>;
>                         interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
>                                         <0 0 0 2 &pcie_intc0 1>, /* INT B */
>                                         <0 0 0 3 &pcie_intc0 2>, /* INT C */
>                                         <0 0 0 4 &pcie_intc0 3>; /* INT D */

If I understand correctly, this is the mapping from the PCI world
(INTA, INTB, etc.) to the platform-specific world (pcie_intc0 0, etc.)

If a Root Port raises a virtual INTA, the RC should turn it into the
corresponding platform interrupt, i.e., GIC_SPI 48 from the
description below.

> And  then
> 
>                         pcie_intc0: legacy-interrupt-controller {
>                                 interrupt-controller;
>                                 #interrupt-cells = <1>;
>                                 interrupt-parent = <&gic>;
>                                 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
>                                         <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
>                                         <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
>                                         <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>;
>                         };
> 
> So if RC interrupt for Power management and Error interrupt is a separate
> line, how can software describe that using the above interrupt map?

I don't know anything about interrupts the RC might generate on its
own behalf.  A lot of the RC behavior is not specified by the PCIe
spec because the RC is on the border between the upstream
platform-specific stuff and the downstream PCIe stuff.  Is there
something in the PCIe spec about the power management and error
interrupts you're talking about?  Of maybe you can point me to a
section of the Keystone spec that talks about interrupts generated by
the RC?

In any event, the AER interrupts we're looking for in portdrv are from
the Root Port, not from the RC.  For INTx, my understanding is that
the RC *transforms* virtual INTx messages from the Root Port in the
PCIe domain into GIC transactions in the platform domain.

Bjorn

RE: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Po Liu]

Hi Bjorn,
I confirm we met same problem with KeyStone base on DesignWare design.


Best regards,
Liu Po

>  -----Original Message-----
>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>  Sent: Saturday, June 04, 2016 11:49 AM
>  To: Murali Karicheri
>  Cc: Po Liu; linux-pci@vger.kernel.org; linux-arm-
>  kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
>  devicetree@vger.kernel.org; Arnd Bergmann; Roy Zang; Marc Zyngier;
>  Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn Helgaas; Shawn Guo;
>  Mingkai Hu; Rob Herring
>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with none
>  MSI/MSI-X/INTx mode
>  
>  On Fri, Jun 03, 2016 at 01:31:11PM -0400, Murali Karicheri wrote:
>  > Po,
>  >
>  > Sorry to hijack your discussion, but the problem seems to be same for
>  > Keystone PCI controller which is also designware (old version) based.
>  >
>  > On 06/03/2016 12:09 AM, Bjorn Helgaas wrote:
>  > > On Thu, Jun 02, 2016 at 11:37:28AM -0400, Murali Karicheri wrote:
>  > >> On 06/02/2016 09:55 AM, Bjorn Helgaas wrote:
>  > >>> On Thu, Jun 02, 2016 at 05:01:19AM +0000, Po Liu wrote:
>  > >>>>>  -----Original Message-----
>  > >>>>>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>  > >>>>>  Sent: Thursday, June 02, 2016 11:48 AM
>  > >>>>>  To: Po Liu
>  > >>>>>  Cc: linux-pci@vger.kernel.org;
>  > >>>>> linux-arm-kernel@lists.infradead.org;
>  > >>>>>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Arnd
>  > >>>>> Bergmann;  Roy Zang; Marc Zyngier; Stuart Yoder; Yang-Leo Li;
>  > >>>>> Minghuan Lian; Bjorn  Helgaas; Shawn Guo; Mingkai Hu; Rob
>  > >>>>> Herring
>  > >>>>>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with
>  > >>>>> none  MSI/MSI-X/INTx mode
>  > >>>>>
>  > >>>>>  [+cc Rob]
>  > >>>>>
>  > >>>>>  Hi Po,
>  > >>>>>
>  > >>>>>  On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu wrote:
>  > >>>>>  > On some platforms, root port doesn't support MSI/MSI-X/INTx
>  in RC mode.
>  > >>>>>  > When chip support the aer interrupt with none MSI/MSI-X/INTx
>  > >>>>> mode,  > maybe there is interrupt line for aer pme etc. Search
>  > >>>>> the interrupt  > number in the fdt file.
>  > >>>>>
>  > >>>>>  My understanding is that AER interrupt signaling can be done
>  > >>>>> via INTx,  MSI, or MSI-X (PCIe spec r3.0, sec 6.2.4.1.2).
>  > >>>>> Apparently your device  doesn't support MSI or MSI-X.  Are you
>  > >>>>> saying it doesn't support INTx  either?  How is the interrupt
>  you're requesting here different from INTx?
>  > >>>>
>  > >>>> Layerscape use none of MSI or MSI-X or INTx to indicate the
>  > >>>> devices or root error in RC mode. But use an independent SPI
>  > >>>> interrupt(arm interrupt controller) line.
>  > >>>
>  > >>> The Root Port is a PCI device and should follow the normal PCI
>  > >>> rules for interrupts.  As far as I understand, that means it
>  > >>> should use MSI, MSI-X, or INTx.  If your Root Port doesn't use MSI
>  > >>> or MSI-X, it should use INTx, the PCI_INTERRUPT_PIN register
>  > >>> should tell us which (INTA/ INTB/etc.), and
>  PCI_COMMAND_INTX_DISABLE should work to disable it.
>  > >>> That's all from the PCI point of view, of course.
>  > >>
>  > >> I am faced with the same issue on Keystone PCI hardware and it has
>  > >> been on my TODO list  for quite some time. Keystone PCI hardware
>  > >> also doesn't use MSI or MSI-X or INTx for reporting errors received
>  > >> at the root port, but use a platform interrupt instead (not
>  > >> complaint to PCI standard as per PCI base spec). So I would need
>  > >> similar change to have the error interrupt passed to the aer
>  > >> driver. So there are hardware out there like Keystone which
>  requires to support this through platform IRQ.
>  > >
>  > > This is not a new area of the spec, and it's hard for me to believe
>  > > that these two new PCIe controllers are both broken the same way
>  > > (although I guess both are DesignWare-based, so maybe this is the
>  > > same underlying problem in both cases?).  I think it's more likely
>  > > that we just haven't figured out the right way to describe this in
>  the DT.
>  >
>  > Keystone is using an older version of the designware IP and it
>  > implements all of the interrupts in the application register space
>  > unlike other newer version of the hardware. So I assume, the version
>  > used on Layerscape is also an older version and the both have same
>  > issue in terms of non standard platform interrupt used for error
>  reporting.
>  >
>  > > I assume you have a Root Port with an AER capability, no MSI
>  > > capability, and no MSI-X capability, right?
>  >
>  > Has AER capability and both MSI and INTx (legacy) capability
>  >
>  > > What does its Interrupt
>  > > Pin register contain?  If it's zero, it doesn't use INTx either, so
>  > > according to the spec it should generate no interrupts.
>  > >
>  > At address offset 0x3C by default has a value of 1, but it is writable
>  > by software. So default is INTx A.
>  
>  0x3c is the Interrupt *Line*, which is read/write.  The Interrupt
>  *Pin* is at 0x3d and should be read-only.
>  
>  Does your Keystone driver support MSI?  If so, since your Root Port
>  supports MSI, I would think we would use that by default, and the INTx
>  stuff wouldn't even matter.

Layerscape is also shows "Both message signaled interrupts (MSI) and legacy INTx are supported."
But both of them not work for AER interrupt when devices or root port report aer error.
But another GIC interrupt line do.

>  
>  > > But if Interrupt Pin is non-zero, that means the Root Port should be
>  > > able to generate virtual INTx interrupts.  Presumably the Root
>  > > Complex connects those interrupts to something; maybe to your
>  > > platform interrupt?
>  >
>  > Probably that is what is happening. Both Power management and Error
>  > interrupts are raised on platform interrupt lines.
>  >
>  > 12 Error Interrupts
>  >
>  > [0] System error (OR of fatal, nonfatal, correctable errors) (RC mode
>  > only) [1] PCIe fatal error (RC mode only) [2] PCIe non-fatal error (RC
>  > mode only) [3] PCIe correctable error (RC mode only) [4] AXI Error due
>  > to fatal condition in AXI bridge (EP/RC modes) [5] PCIe advanced error
>  > (RC mode only)
>  >
>  > 13 Power management and reset event interrupts
>  >
>  > [0] Power management turn-off message interrupt (EP mode only) [1]
>  > Power management ack message interrupt (RC mode only) [2] Power
>  > management event interrupt (RC mode only) [3] Link request reset
>  > interrupt (hot reset or link down) (RC mode only)
>  >
>  > > PCI doesn't say anything about an interrupt after it leaves the Root
>  > > Complex, so the fact that it's connected to a "platform interrupt"
>  > > or "SPI interrupt" or "IOAPIC interrupt" doesn't make it non-
>  compliant.
>  > > Shouldn't we be able to use the interrupt-map and related DT
>  > > properties to express the fact that Root Port virtual INTx is routed
>  > > to platform interrupt Y, even without any special-case code in
>  > > portdrv?
>  >
>  > My understanding is if RC also raise interrupt on INTx, then below map
>  > make sense, where either EP or RC can raise interrupt and the line
>  > will be muxed for interrupt from EP or RC port.
>  
>  I'm sorry, I didn't quite catch your meaning here, so let me try to
>  clarify some terminology.  Maybe we'll eventually blunder into a common
>  understanding :)
>  
>  INTx is a PCI concept and only means something in the PCI hierarchy.
>  The RC would *receive* virtual INTx interrupts from the PCI hierarchy
>  and turn them into some platform-specific interrupt (not INTx) on the
>  upstream side.
>  
>  So strictly speaking, the RC might raise platform-specific interrupts
>  when it receives INTx interrupts, but it would not raise any INTx
>  interrupts itself.
>  
>  > Here is the DT entry in PCIE keystone for Legacy interrupt mapping to
>  > host interrupt.
>  >                         #interrupt-cells = <1>;
>  >                         interrupt-map-mask = <0 0 0 7>;
>  >                         interrupt-map = <0 0 0 1 &pcie_intc0 0>, /*
>  INT A */
>  >                                         <0 0 0 2 &pcie_intc0 1>, /*
>  INT B */
>  >                                         <0 0 0 3 &pcie_intc0 2>, /*
>  INT C */
>  >                                         <0 0 0 4 &pcie_intc0 3>; /*
>  > INT D */
>  
>  If I understand correctly, this is the mapping from the PCI world (INTA,
>  INTB, etc.) to the platform-specific world (pcie_intc0 0, etc.)
>  
>  If a Root Port raises a virtual INTA, the RC should turn it into the
>  corresponding platform interrupt, i.e., GIC_SPI 48 from the description
>  below.
>  
>  > And  then
>  >
>  >                         pcie_intc0: legacy-interrupt-controller {
>  >                                 interrupt-controller;
>  >                                 #interrupt-cells = <1>;
>  >                                 interrupt-parent = <&gic>;
>  >                                 interrupts = <GIC_SPI 48
>  IRQ_TYPE_EDGE_RISING>,
>  >                                         <GIC_SPI 49
>  IRQ_TYPE_EDGE_RISING>,
>  >                                         <GIC_SPI 50
>  IRQ_TYPE_EDGE_RISING>,
>  >                                         <GIC_SPI 51
>  IRQ_TYPE_EDGE_RISING>;
>  >                         };
>  >
>  > So if RC interrupt for Power management and Error interrupt is a
>  > separate line, how can software describe that using the above
>  interrupt map?
>  
>  I don't know anything about interrupts the RC might generate on its own
>  behalf.  A lot of the RC behavior is not specified by the PCIe spec
>  because the RC is on the border between the upstream platform-specific
>  stuff and the downstream PCIe stuff.  Is there something in the PCIe
>  spec about the power management and error interrupts you're talking
>  about?  Of maybe you can point me to a section of the Keystone spec that
>  talks about interrupts generated by the RC?

Below is one of the PCIE controller interrupts list: 

142 PEX1 INTA 
143 PEX1 INTB 
144 PEX1 INTC 
145 PEX1 INTD 
146-147 Reserved
148 PEX1 MSI 
149 PEX1 PME 
150 PEX1 CFG err interrupt

Only the "150 PEX1 CFG err interrupt" routing to the aer interrupt. 


>  
>  In any event, the AER interrupts we're looking for in portdrv are from
>  the Root Port, not from the RC.  For INTx, my understanding is that the
>  RC *transforms* virtual INTx messages from the Root Port in the PCIe
>  domain into GIC transactions in the platform domain.
>  
>  Bjorn

Re: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Murali Karicheri]

On 06/06/2016 03:32 AM, Po Liu wrote:
> Hi Bjorn,
> I confirm we met same problem with KeyStone base on DesignWare design.
> 
> 
> Best regards,
> Liu Po
> 
>>  -----Original Message-----
>>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>>  Sent: Saturday, June 04, 2016 11:49 AM
>>  To: Murali Karicheri
>>  Cc: Po Liu; linux-pci@vger.kernel.org; linux-arm-
>>  kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
>>  devicetree@vger.kernel.org; Arnd Bergmann; Roy Zang; Marc Zyngier;
>>  Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn Helgaas; Shawn Guo;
>>  Mingkai Hu; Rob Herring
>>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with none
>>  MSI/MSI-X/INTx mode
>>  
>>  On Fri, Jun 03, 2016 at 01:31:11PM -0400, Murali Karicheri wrote:
>>  > Po,
>>  >
>>  > Sorry to hijack your discussion, but the problem seems to be same for
>>  > Keystone PCI controller which is also designware (old version) based.
>>  >
>>  > On 06/03/2016 12:09 AM, Bjorn Helgaas wrote:
>>  > > On Thu, Jun 02, 2016 at 11:37:28AM -0400, Murali Karicheri wrote:
>>  > >> On 06/02/2016 09:55 AM, Bjorn Helgaas wrote:
>>  > >>> On Thu, Jun 02, 2016 at 05:01:19AM +0000, Po Liu wrote:
>>  > >>>>>  -----Original Message-----
>>  > >>>>>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>>  > >>>>>  Sent: Thursday, June 02, 2016 11:48 AM
>>  > >>>>>  To: Po Liu
>>  > >>>>>  Cc: linux-pci@vger.kernel.org;
>>  > >>>>> linux-arm-kernel@lists.infradead.org;
>>  > >>>>>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Arnd
>>  > >>>>> Bergmann;  Roy Zang; Marc Zyngier; Stuart Yoder; Yang-Leo Li;
>>  > >>>>> Minghuan Lian; Bjorn  Helgaas; Shawn Guo; Mingkai Hu; Rob
>>  > >>>>> Herring
>>  > >>>>>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with
>>  > >>>>> none  MSI/MSI-X/INTx mode
>>  > >>>>>
>>  > >>>>>  [+cc Rob]
>>  > >>>>>
>>  > >>>>>  Hi Po,
>>  > >>>>>
>>  > >>>>>  On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu wrote:
>>  > >>>>>  > On some platforms, root port doesn't support MSI/MSI-X/INTx
>>  in RC mode.
>>  > >>>>>  > When chip support the aer interrupt with none MSI/MSI-X/INTx
>>  > >>>>> mode,  > maybe there is interrupt line for aer pme etc. Search
>>  > >>>>> the interrupt  > number in the fdt file.
>>  > >>>>>
>>  > >>>>>  My understanding is that AER interrupt signaling can be done
>>  > >>>>> via INTx,  MSI, or MSI-X (PCIe spec r3.0, sec 6.2.4.1.2).
>>  > >>>>> Apparently your device  doesn't support MSI or MSI-X.  Are you
>>  > >>>>> saying it doesn't support INTx  either?  How is the interrupt
>>  you're requesting here different from INTx?
>>  > >>>>
>>  > >>>> Layerscape use none of MSI or MSI-X or INTx to indicate the
>>  > >>>> devices or root error in RC mode. But use an independent SPI
>>  > >>>> interrupt(arm interrupt controller) line.
>>  > >>>
>>  > >>> The Root Port is a PCI device and should follow the normal PCI
>>  > >>> rules for interrupts.  As far as I understand, that means it
>>  > >>> should use MSI, MSI-X, or INTx.  If your Root Port doesn't use MSI
>>  > >>> or MSI-X, it should use INTx, the PCI_INTERRUPT_PIN register
>>  > >>> should tell us which (INTA/ INTB/etc.), and
>>  PCI_COMMAND_INTX_DISABLE should work to disable it.
>>  > >>> That's all from the PCI point of view, of course.
>>  > >>
>>  > >> I am faced with the same issue on Keystone PCI hardware and it has
>>  > >> been on my TODO list  for quite some time. Keystone PCI hardware
>>  > >> also doesn't use MSI or MSI-X or INTx for reporting errors received
>>  > >> at the root port, but use a platform interrupt instead (not
>>  > >> complaint to PCI standard as per PCI base spec). So I would need
>>  > >> similar change to have the error interrupt passed to the aer
>>  > >> driver. So there are hardware out there like Keystone which
>>  requires to support this through platform IRQ.
>>  > >
>>  > > This is not a new area of the spec, and it's hard for me to believe
>>  > > that these two new PCIe controllers are both broken the same way
>>  > > (although I guess both are DesignWare-based, so maybe this is the
>>  > > same underlying problem in both cases?).  I think it's more likely
>>  > > that we just haven't figured out the right way to describe this in
>>  the DT.
>>  >
>>  > Keystone is using an older version of the designware IP and it
>>  > implements all of the interrupts in the application register space
>>  > unlike other newer version of the hardware. So I assume, the version
>>  > used on Layerscape is also an older version and the both have same
>>  > issue in terms of non standard platform interrupt used for error
>>  reporting.
>>  >
>>  > > I assume you have a Root Port with an AER capability, no MSI
>>  > > capability, and no MSI-X capability, right?
>>  >
>>  > Has AER capability and both MSI and INTx (legacy) capability
>>  >
>>  > > What does its Interrupt
>>  > > Pin register contain?  If it's zero, it doesn't use INTx either, so
>>  > > according to the spec it should generate no interrupts.
>>  > >
>>  > At address offset 0x3C by default has a value of 1, but it is writable
>>  > by software. So default is INTx A.
>>  
>>  0x3c is the Interrupt *Line*, which is read/write.  The Interrupt
>>  *Pin* is at 0x3d and should be read-only.
>>  

You are right. But default is 1 at this address.

>>  Does your Keystone driver support MSI?  If so, since your Root Port
>>  supports MSI, I would think we would use that by default, and the INTx
>>  stuff wouldn't even matter.
> 
> Layerscape is also shows "Both message signaled interrupts (MSI) and legacy INTx are supported."
> But both of them not work for AER interrupt when devices or root port report aer error.
> But another GIC interrupt line do.

Same with Keystone. Even though both MSI and INTx are supported
error interrupt at root port is reported on a different interrupt
line than MSI/INTx. So for Power Management event interrupt is also
different line.

Murali
> 
>>  
>>  > > But if Interrupt Pin is non-zero, that means the Root Port should be
>>  > > able to generate virtual INTx interrupts.  Presumably the Root
>>  > > Complex connects those interrupts to something; maybe to your
>>  > > platform interrupt?
>>  >
>>  > Probably that is what is happening. Both Power management and Error
>>  > interrupts are raised on platform interrupt lines.
>>  >
>>  > 12 Error Interrupts
>>  >
>>  > [0] System error (OR of fatal, nonfatal, correctable errors) (RC mode
>>  > only) [1] PCIe fatal error (RC mode only) [2] PCIe non-fatal error (RC
>>  > mode only) [3] PCIe correctable error (RC mode only) [4] AXI Error due
>>  > to fatal condition in AXI bridge (EP/RC modes) [5] PCIe advanced error
>>  > (RC mode only)
>>  >
>>  > 13 Power management and reset event interrupts
>>  >
>>  > [0] Power management turn-off message interrupt (EP mode only) [1]
>>  > Power management ack message interrupt (RC mode only) [2] Power
>>  > management event interrupt (RC mode only) [3] Link request reset
>>  > interrupt (hot reset or link down) (RC mode only)
>>  >
>>  > > PCI doesn't say anything about an interrupt after it leaves the Root
>>  > > Complex, so the fact that it's connected to a "platform interrupt"
>>  > > or "SPI interrupt" or "IOAPIC interrupt" doesn't make it non-
>>  compliant.
>>  > > Shouldn't we be able to use the interrupt-map and related DT
>>  > > properties to express the fact that Root Port virtual INTx is routed
>>  > > to platform interrupt Y, even without any special-case code in
>>  > > portdrv?
>>  >
>>  > My understanding is if RC also raise interrupt on INTx, then below map
>>  > make sense, where either EP or RC can raise interrupt and the line
>>  > will be muxed for interrupt from EP or RC port.
>>  
>>  I'm sorry, I didn't quite catch your meaning here, so let me try to
>>  clarify some terminology.  Maybe we'll eventually blunder into a common
>>  understanding :)
>>  
>>  INTx is a PCI concept and only means something in the PCI hierarchy.
>>  The RC would *receive* virtual INTx interrupts from the PCI hierarchy
>>  and turn them into some platform-specific interrupt (not INTx) on the
>>  upstream side.
>>  
>>  So strictly speaking, the RC might raise platform-specific interrupts
>>  when it receives INTx interrupts, but it would not raise any INTx
>>  interrupts itself.
>>  
>>  > Here is the DT entry in PCIE keystone for Legacy interrupt mapping to
>>  > host interrupt.
>>  >                         #interrupt-cells = <1>;
>>  >                         interrupt-map-mask = <0 0 0 7>;
>>  >                         interrupt-map = <0 0 0 1 &pcie_intc0 0>, /*
>>  INT A */
>>  >                                         <0 0 0 2 &pcie_intc0 1>, /*
>>  INT B */
>>  >                                         <0 0 0 3 &pcie_intc0 2>, /*
>>  INT C */
>>  >                                         <0 0 0 4 &pcie_intc0 3>; /*
>>  > INT D */
>>  
>>  If I understand correctly, this is the mapping from the PCI world (INTA,
>>  INTB, etc.) to the platform-specific world (pcie_intc0 0, etc.)
>>  
>>  If a Root Port raises a virtual INTA, the RC should turn it into the
>>  corresponding platform interrupt, i.e., GIC_SPI 48 from the description
>>  below.
>>  
>>  > And  then
>>  >
>>  >                         pcie_intc0: legacy-interrupt-controller {
>>  >                                 interrupt-controller;
>>  >                                 #interrupt-cells = <1>;
>>  >                                 interrupt-parent = <&gic>;
>>  >                                 interrupts = <GIC_SPI 48
>>  IRQ_TYPE_EDGE_RISING>,
>>  >                                         <GIC_SPI 49
>>  IRQ_TYPE_EDGE_RISING>,
>>  >                                         <GIC_SPI 50
>>  IRQ_TYPE_EDGE_RISING>,
>>  >                                         <GIC_SPI 51
>>  IRQ_TYPE_EDGE_RISING>;
>>  >                         };
>>  >
>>  > So if RC interrupt for Power management and Error interrupt is a
>>  > separate line, how can software describe that using the above
>>  interrupt map?
>>  
>>  I don't know anything about interrupts the RC might generate on its own
>>  behalf.  A lot of the RC behavior is not specified by the PCIe spec
>>  because the RC is on the border between the upstream platform-specific
>>  stuff and the downstream PCIe stuff.  Is there something in the PCIe
>>  spec about the power management and error interrupts you're talking
>>  about?  Of maybe you can point me to a section of the Keystone spec that
>>  talks about interrupts generated by the RC?
> 
> Below is one of the PCIE controller interrupts list: 
> 
> 142 PEX1 INTA 
> 143 PEX1 INTB 
> 144 PEX1 INTC 
> 145 PEX1 INTD 
> 146-147 Reserved
> 148 PEX1 MSI 
> 149 PEX1 PME 
> 150 PEX1 CFG err interrupt
> 
> Only the "150 PEX1 CFG err interrupt" routing to the aer interrupt. 
> 
> 
>>  
>>  In any event, the AER interrupts we're looking for in portdrv are from
>>  the Root Port, not from the RC.  For INTx, my understanding is that the
>>  RC *transforms* virtual INTx messages from the Root Port in the PCIe
>>  domain into GIC transactions in the platform domain.
>>  
>>  Bjorn


-- 
Murali Karicheri
Linux Kernel, Keystone

Re: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Bjorn Helgaas]

On Mon, Jun 06, 2016 at 10:01:44AM -0400, Murali Karicheri wrote:
> On 06/06/2016 03:32 AM, Po Liu wrote:
> > Hi Bjorn,
> > I confirm we met same problem with KeyStone base on DesignWare design.
> > 
> > 
> > Best regards,
> > Liu Po
> > 
> >>  -----Original Message-----
> >>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
> >>  Sent: Saturday, June 04, 2016 11:49 AM
> >>  To: Murali Karicheri
> >>  Cc: Po Liu; linux-pci@vger.kernel.org; linux-arm-
> >>  kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> >>  devicetree@vger.kernel.org; Arnd Bergmann; Roy Zang; Marc Zyngier;
> >>  Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn Helgaas; Shawn Guo;
> >>  Mingkai Hu; Rob Herring
> >>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with none
> >>  MSI/MSI-X/INTx mode
> >>  
> >>  On Fri, Jun 03, 2016 at 01:31:11PM -0400, Murali Karicheri wrote:
> >>  > Po,
> >>  >
> >>  > Sorry to hijack your discussion, but the problem seems to be same for
> >>  > Keystone PCI controller which is also designware (old version) based.
> >>  >
> >>  > On 06/03/2016 12:09 AM, Bjorn Helgaas wrote:
> >>  > > On Thu, Jun 02, 2016 at 11:37:28AM -0400, Murali Karicheri wrote:
> >>  > >> On 06/02/2016 09:55 AM, Bjorn Helgaas wrote:
> >>  > >>> On Thu, Jun 02, 2016 at 05:01:19AM +0000, Po Liu wrote:
> >>  > >>>>>  -----Original Message-----
> >>  > >>>>>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
> >>  > >>>>>  Sent: Thursday, June 02, 2016 11:48 AM
> >>  > >>>>>  To: Po Liu
> >>  > >>>>>  Cc: linux-pci@vger.kernel.org;
> >>  > >>>>> linux-arm-kernel@lists.infradead.org;
> >>  > >>>>>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Arnd
> >>  > >>>>> Bergmann;  Roy Zang; Marc Zyngier; Stuart Yoder; Yang-Leo Li;
> >>  > >>>>> Minghuan Lian; Bjorn  Helgaas; Shawn Guo; Mingkai Hu; Rob
> >>  > >>>>> Herring
> >>  > >>>>>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with
> >>  > >>>>> none  MSI/MSI-X/INTx mode
> >>  > >>>>>
> >>  > >>>>>  [+cc Rob]
> >>  > >>>>>
> >>  > >>>>>  Hi Po,
> >>  > >>>>>
> >>  > >>>>>  On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu wrote:
> >>  > >>>>>  > On some platforms, root port doesn't support MSI/MSI-X/INTx
> >>  in RC mode.
> >>  > >>>>>  > When chip support the aer interrupt with none MSI/MSI-X/INTx
> >>  > >>>>> mode,  > maybe there is interrupt line for aer pme etc. Search
> >>  > >>>>> the interrupt  > number in the fdt file.
> >>  > >>>>>
> >>  > >>>>>  My understanding is that AER interrupt signaling can be done
> >>  > >>>>> via INTx,  MSI, or MSI-X (PCIe spec r3.0, sec 6.2.4.1.2).
> >>  > >>>>> Apparently your device  doesn't support MSI or MSI-X.  Are you
> >>  > >>>>> saying it doesn't support INTx  either?  How is the interrupt
> >>  you're requesting here different from INTx?
> >>  > >>>>
> >>  > >>>> Layerscape use none of MSI or MSI-X or INTx to indicate the
> >>  > >>>> devices or root error in RC mode. But use an independent SPI
> >>  > >>>> interrupt(arm interrupt controller) line.
> >>  > >>>
> >>  > >>> The Root Port is a PCI device and should follow the normal PCI
> >>  > >>> rules for interrupts.  As far as I understand, that means it
> >>  > >>> should use MSI, MSI-X, or INTx.  If your Root Port doesn't use MSI
> >>  > >>> or MSI-X, it should use INTx, the PCI_INTERRUPT_PIN register
> >>  > >>> should tell us which (INTA/ INTB/etc.), and
> >>  PCI_COMMAND_INTX_DISABLE should work to disable it.
> >>  > >>> That's all from the PCI point of view, of course.
> >>  > >>
> >>  > >> I am faced with the same issue on Keystone PCI hardware and it has
> >>  > >> been on my TODO list  for quite some time. Keystone PCI hardware
> >>  > >> also doesn't use MSI or MSI-X or INTx for reporting errors received
> >>  > >> at the root port, but use a platform interrupt instead (not
> >>  > >> complaint to PCI standard as per PCI base spec). So I would need
> >>  > >> similar change to have the error interrupt passed to the aer
> >>  > >> driver. So there are hardware out there like Keystone which
> >>  requires to support this through platform IRQ.
> >>  > >
> >>  > > This is not a new area of the spec, and it's hard for me to believe
> >>  > > that these two new PCIe controllers are both broken the same way
> >>  > > (although I guess both are DesignWare-based, so maybe this is the
> >>  > > same underlying problem in both cases?).  I think it's more likely
> >>  > > that we just haven't figured out the right way to describe this in
> >>  the DT.
> >>  >
> >>  > Keystone is using an older version of the designware IP and it
> >>  > implements all of the interrupts in the application register space
> >>  > unlike other newer version of the hardware. So I assume, the version
> >>  > used on Layerscape is also an older version and the both have same
> >>  > issue in terms of non standard platform interrupt used for error
> >>  reporting.
> >>  >
> >>  > > I assume you have a Root Port with an AER capability, no MSI
> >>  > > capability, and no MSI-X capability, right?
> >>  >
> >>  > Has AER capability and both MSI and INTx (legacy) capability
> >>  >
> >>  > > What does its Interrupt
> >>  > > Pin register contain?  If it's zero, it doesn't use INTx either, so
> >>  > > according to the spec it should generate no interrupts.
> >>  > >
> >>  > At address offset 0x3C by default has a value of 1, but it is writable
> >>  > by software. So default is INTx A.
> >>  
> >>  0x3c is the Interrupt *Line*, which is read/write.  The Interrupt
> >>  *Pin* is at 0x3d and should be read-only.
> >>  
> 
> You are right. But default is 1 at this address.
> 
> >>  Does your Keystone driver support MSI?  If so, since your Root Port
> >>  supports MSI, I would think we would use that by default, and the INTx
> >>  stuff wouldn't even matter.
> > 
> > Layerscape is also shows "Both message signaled interrupts (MSI) and legacy INTx are supported."
> > But both of them not work for AER interrupt when devices or root port report aer error.
> > But another GIC interrupt line do.
> 
> Same with Keystone. Even though both MSI and INTx are supported
> error interrupt at root port is reported on a different interrupt
> line than MSI/INTx. So for Power Management event interrupt is also
> different line.

I'm looking at the "Error Message Controls" diagram in the PCIe spec
r3.0, sec 6.2.6.  Does this hardware fit into the platform-specific
"System Error" case there?  Do the Root Control enable bits (in the
PCIe Capability) control this interrupt?  If so, maybe this makes more
sense than I thought.

We have to assume both notification paths work (the normal
INTx/MSI/MSI-X AER interrupts as well as the platform-specific System
Errors), so if we add support for System Errors, it should be
structured so we prefer INTx/MSI/MSI-X, and only fall back to System
Errors if they don't work.  AER would have to know which path it's
using so aer_enable_rootport() can disable the other one (currently it
always disables System Errors).

Then you'd have to add quirks to mark MSI/MSI-X/INTx as being broken
on your devices to force the fallback to System Errors.

How much would this screw up other PCIe services (PME, hotplug, VC,
etc)?  Does MSI work for them?

Bjorn

RE: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Po Liu]

Hi Bjorn,

>  -----Original Message-----
>  
>  On Mon, Jun 06, 2016 at 10:01:44AM -0400, Murali Karicheri wrote:
>  > On 06/06/2016 03:32 AM, Po Liu wrote:
>  > > Hi Bjorn,
>  > > I confirm we met same problem with KeyStone base on DesignWare
>  design.
>  > >
>  > >
>  > > Best regards,
>  > > Liu Po
>  > >
>  > >>  -----Original Message-----
>  > >>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>  > >>  Sent: Saturday, June 04, 2016 11:49 AM
>  > >>  To: Murali Karicheri
>  > >>  Cc: Po Liu; linux-pci@vger.kernel.org; linux-arm-
>  > >> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
>  > >> devicetree@vger.kernel.org; Arnd Bergmann; Roy Zang; Marc Zyngier;
>  > >> Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn Helgaas; Shawn Guo;
>  > >> Mingkai Hu; Rob Herring
>  > >>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with none
>  > >> MSI/MSI-X/INTx mode
>  > >>
>  > >>  On Fri, Jun 03, 2016 at 01:31:11PM -0400, Murali Karicheri wrote:
>  > >>  > Po,
>  > >>  >
>  > >>  > Sorry to hijack your discussion, but the problem seems to be
>  > >> same for  > Keystone PCI controller which is also designware (old
>  version) based.
>  > >>  >
>  > >>  > On 06/03/2016 12:09 AM, Bjorn Helgaas wrote:
>  > >>  > > On Thu, Jun 02, 2016 at 11:37:28AM -0400, Murali Karicheri
>  wrote:
>  > >>  > >> On 06/02/2016 09:55 AM, Bjorn Helgaas wrote:
>  > >>  > >>> On Thu, Jun 02, 2016 at 05:01:19AM +0000, Po Liu wrote:
>  > >>  > >>>>>  -----Original Message-----  > >>>>>  From: Bjorn Helgaas
>  > >> [mailto:helgaas@kernel.org]  > >>>>>  Sent: Thursday, June 02, 2016
>  > >> 11:48 AM  > >>>>>  To: Po Liu  > >>>>>  Cc:
>  > >> linux-pci@vger.kernel.org;  > >>>>>
>  > >> linux-arm-kernel@lists.infradead.org;
>  > >>  > >>>>>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
>  > >> Arnd  > >>>>> Bergmann;  Roy Zang; Marc Zyngier; Stuart Yoder;
>  > >> Yang-Leo Li;  > >>>>> Minghuan Lian; Bjorn  Helgaas; Shawn Guo;
>  > >> Mingkai Hu; Rob  > >>>>> Herring  > >>>>>  Subject: Re: [PATCH 2/2]
>  > >> aer: add support aer interrupt with  > >>>>> none  MSI/MSI-X/INTx
>  > >> mode  > >>>>>  > >>>>>  [+cc Rob]  > >>>>>  > >>>>>  Hi Po,  >
>  > >> >>>>>  > >>>>>  On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu
>  > >> wrote:
>  > >>  > >>>>>  > On some platforms, root port doesn't support
>  > >> MSI/MSI-X/INTx  in RC mode.
>  > >>  > >>>>>  > When chip support the aer interrupt with none
>  > >> MSI/MSI-X/INTx  > >>>>> mode,  > maybe there is interrupt line for
>  > >> aer pme etc. Search  > >>>>> the interrupt  > number in the fdt
>  file.
>  > >>  > >>>>>
>  > >>  > >>>>>  My understanding is that AER interrupt signaling can be
>  > >> done  > >>>>> via INTx,  MSI, or MSI-X (PCIe spec r3.0, sec
>  6.2.4.1.2).
>  > >>  > >>>>> Apparently your device  doesn't support MSI or MSI-X.  Are
>  > >> you  > >>>>> saying it doesn't support INTx  either?  How is the
>  > >> interrupt  you're requesting here different from INTx?
>  > >>  > >>>>
>  > >>  > >>>> Layerscape use none of MSI or MSI-X or INTx to indicate the
>  > >> > >>>> devices or root error in RC mode. But use an independent SPI
>  > >> > >>>> interrupt(arm interrupt controller) line.
>  > >>  > >>>
>  > >>  > >>> The Root Port is a PCI device and should follow the normal
>  > >> PCI  > >>> rules for interrupts.  As far as I understand, that
>  > >> means it  > >>> should use MSI, MSI-X, or INTx.  If your Root Port
>  > >> doesn't use MSI  > >>> or MSI-X, it should use INTx, the
>  > >> PCI_INTERRUPT_PIN register  > >>> should tell us which (INTA/
>  > >> INTB/etc.), and  PCI_COMMAND_INTX_DISABLE should work to disable it.
>  > >>  > >>> That's all from the PCI point of view, of course.
>  > >>  > >>
>  > >>  > >> I am faced with the same issue on Keystone PCI hardware and
>  > >> it has  > >> been on my TODO list  for quite some time. Keystone
>  > >> PCI hardware  > >> also doesn't use MSI or MSI-X or INTx for
>  > >> reporting errors received  > >> at the root port, but use a
>  > >> platform interrupt instead (not  > >> complaint to PCI standard as
>  > >> per PCI base spec). So I would need  > >> similar change to have
>  > >> the error interrupt passed to the aer  > >> driver. So there are
>  > >> hardware out there like Keystone which  requires to support this
>  through platform IRQ.
>  > >>  > >
>  > >>  > > This is not a new area of the spec, and it's hard for me to
>  > >> believe  > > that these two new PCIe controllers are both broken
>  > >> the same way  > > (although I guess both are DesignWare-based, so
>  > >> maybe this is the  > > same underlying problem in both cases?).  I
>  > >> think it's more likely  > > that we just haven't figured out the
>  > >> right way to describe this in  the DT.
>  > >>  >
>  > >>  > Keystone is using an older version of the designware IP and it
>  > >> > implements all of the interrupts in the application register
>  > >> space  > unlike other newer version of the hardware. So I assume,
>  > >> the version  > used on Layerscape is also an older version and the
>  > >> both have same  > issue in terms of non standard platform interrupt
>  > >> used for error  reporting.
>  > >>  >
>  > >>  > > I assume you have a Root Port with an AER capability, no MSI
>  > >> > > capability, and no MSI-X capability, right?
>  > >>  >
>  > >>  > Has AER capability and both MSI and INTx (legacy) capability  >
>  > >> > > What does its Interrupt  > > Pin register contain?  If it's
>  > >> zero, it doesn't use INTx either, so  > > according to the spec it
>  > >> should generate no interrupts.
>  > >>  > >
>  > >>  > At address offset 0x3C by default has a value of 1, but it is
>  > >> writable  > by software. So default is INTx A.
>  > >>
>  > >>  0x3c is the Interrupt *Line*, which is read/write.  The Interrupt
>  > >>  *Pin* is at 0x3d and should be read-only.
>  > >>
>  >
>  > You are right. But default is 1 at this address.
>  >
>  > >>  Does your Keystone driver support MSI?  If so, since your Root
>  > >> Port  supports MSI, I would think we would use that by default, and
>  > >> the INTx  stuff wouldn't even matter.
>  > >
>  > > Layerscape is also shows "Both message signaled interrupts (MSI) and
>  legacy INTx are supported."
>  > > But both of them not work for AER interrupt when devices or root
>  port report aer error.
>  > > But another GIC interrupt line do.
>  >
>  > Same with Keystone. Even though both MSI and INTx are supported error
>  > interrupt at root port is reported on a different interrupt line than
>  > MSI/INTx. So for Power Management event interrupt is also different
>  > line.
>  
>  I'm looking at the "Error Message Controls" diagram in the PCIe spec
>  r3.0, sec 6.2.6.  Does this hardware fit into the platform-specific
>  "System Error" case there?  Do the Root Control enable bits (in the PCIe
>  Capability) control this interrupt?  If so, maybe this makes more sense
>  than I thought.

It supposedly not the "System Error" case. But "the Error Interrupt" case.
Which means " Root Error Command register " could control the interrupt
 line we have now. (refer PCIe spec r3.0, sec 6.2.6)

May this kind of hardware design route broken the spec? 

>  
>  We have to assume both notification paths work (the normal INTx/MSI/MSI-
>  X AER interrupts as well as the platform-specific System Errors), so if
>  we add support for System Errors, it should be structured so we prefer
>  INTx/MSI/MSI-X, and only fall back to System Errors if they don't work.
>  AER would have to know which path it's using so aer_enable_rootport()
>  can disable the other one (currently it always disables System Errors).
>  
>  Then you'd have to add quirks to mark MSI/MSI-X/INTx as being broken on
>  your devices to force the fallback to System Errors.
>  
>  How much would this screw up other PCIe services (PME, hotplug, VC, etc)?
>  Does MSI work for them?

PME also like the AER. Hotplug is not supported. Others not known.
Po Liu

>  
>  Bjorn

Re: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Bjorn Helgaas]

On Tue, Jun 07, 2016 at 10:07:40AM +0000, Po Liu wrote:
> Hi Bjorn,
> 
> >  -----Original Message-----
> >  
> >  On Mon, Jun 06, 2016 at 10:01:44AM -0400, Murali Karicheri wrote:
> >  > On 06/06/2016 03:32 AM, Po Liu wrote:
> >  > > Hi Bjorn,
> >  > > I confirm we met same problem with KeyStone base on DesignWare
> >  design.
> >  > >
> >  > >
> >  > > Best regards,
> >  > > Liu Po
> >  > >
> >  > >>  -----Original Message-----
> >  > >>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
> >  > >>  Sent: Saturday, June 04, 2016 11:49 AM
> >  > >>  To: Murali Karicheri
> >  > >>  Cc: Po Liu; linux-pci@vger.kernel.org; linux-arm-
> >  > >> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> >  > >> devicetree@vger.kernel.org; Arnd Bergmann; Roy Zang; Marc Zyngier;
> >  > >> Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn Helgaas; Shawn Guo;
> >  > >> Mingkai Hu; Rob Herring
> >  > >>  Subject: Re: [PATCH 2/2] aer: add support aer interrupt with none
> >  > >> MSI/MSI-X/INTx mode
> >  > >>
> >  > >>  On Fri, Jun 03, 2016 at 01:31:11PM -0400, Murali Karicheri wrote:
> >  > >>  > Po,
> >  > >>  >
> >  > >>  > Sorry to hijack your discussion, but the problem seems to be
> >  > >> same for  > Keystone PCI controller which is also designware (old
> >  version) based.
> >  > >>  >
> >  > >>  > On 06/03/2016 12:09 AM, Bjorn Helgaas wrote:
> >  > >>  > > On Thu, Jun 02, 2016 at 11:37:28AM -0400, Murali Karicheri
> >  wrote:
> >  > >>  > >> On 06/02/2016 09:55 AM, Bjorn Helgaas wrote:
> >  > >>  > >>> On Thu, Jun 02, 2016 at 05:01:19AM +0000, Po Liu wrote:
> >  > >>  > >>>>>  -----Original Message-----  > >>>>>  From: Bjorn Helgaas
> >  > >> [mailto:helgaas@kernel.org]  > >>>>>  Sent: Thursday, June 02, 2016
> >  > >> 11:48 AM  > >>>>>  To: Po Liu  > >>>>>  Cc:
> >  > >> linux-pci@vger.kernel.org;  > >>>>>
> >  > >> linux-arm-kernel@lists.infradead.org;
> >  > >>  > >>>>>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> >  > >> Arnd  > >>>>> Bergmann;  Roy Zang; Marc Zyngier; Stuart Yoder;
> >  > >> Yang-Leo Li;  > >>>>> Minghuan Lian; Bjorn  Helgaas; Shawn Guo;
> >  > >> Mingkai Hu; Rob  > >>>>> Herring  > >>>>>  Subject: Re: [PATCH 2/2]
> >  > >> aer: add support aer interrupt with  > >>>>> none  MSI/MSI-X/INTx
> >  > >> mode  > >>>>>  > >>>>>  [+cc Rob]  > >>>>>  > >>>>>  Hi Po,  >
> >  > >> >>>>>  > >>>>>  On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu
> >  > >> wrote:
> >  > >>  > >>>>>  > On some platforms, root port doesn't support
> >  > >> MSI/MSI-X/INTx  in RC mode.
> >  > >>  > >>>>>  > When chip support the aer interrupt with none
> >  > >> MSI/MSI-X/INTx  > >>>>> mode,  > maybe there is interrupt line for
> >  > >> aer pme etc. Search  > >>>>> the interrupt  > number in the fdt
> >  file.
> >  > >>  > >>>>>
> >  > >>  > >>>>>  My understanding is that AER interrupt signaling can be
> >  > >> done  > >>>>> via INTx,  MSI, or MSI-X (PCIe spec r3.0, sec
> >  6.2.4.1.2).
> >  > >>  > >>>>> Apparently your device  doesn't support MSI or MSI-X.  Are
> >  > >> you  > >>>>> saying it doesn't support INTx  either?  How is the
> >  > >> interrupt  you're requesting here different from INTx?
> >  > >>  > >>>>
> >  > >>  > >>>> Layerscape use none of MSI or MSI-X or INTx to indicate the
> >  > >> > >>>> devices or root error in RC mode. But use an independent SPI
> >  > >> > >>>> interrupt(arm interrupt controller) line.
> >  > >>  > >>>
> >  > >>  > >>> The Root Port is a PCI device and should follow the normal
> >  > >> PCI  > >>> rules for interrupts.  As far as I understand, that
> >  > >> means it  > >>> should use MSI, MSI-X, or INTx.  If your Root Port
> >  > >> doesn't use MSI  > >>> or MSI-X, it should use INTx, the
> >  > >> PCI_INTERRUPT_PIN register  > >>> should tell us which (INTA/
> >  > >> INTB/etc.), and  PCI_COMMAND_INTX_DISABLE should work to disable it.
> >  > >>  > >>> That's all from the PCI point of view, of course.
> >  > >>  > >>
> >  > >>  > >> I am faced with the same issue on Keystone PCI hardware and
> >  > >> it has  > >> been on my TODO list  for quite some time. Keystone
> >  > >> PCI hardware  > >> also doesn't use MSI or MSI-X or INTx for
> >  > >> reporting errors received  > >> at the root port, but use a
> >  > >> platform interrupt instead (not  > >> complaint to PCI standard as
> >  > >> per PCI base spec). So I would need  > >> similar change to have
> >  > >> the error interrupt passed to the aer  > >> driver. So there are
> >  > >> hardware out there like Keystone which  requires to support this
> >  through platform IRQ.
> >  > >>  > >
> >  > >>  > > This is not a new area of the spec, and it's hard for me to
> >  > >> believe  > > that these two new PCIe controllers are both broken
> >  > >> the same way  > > (although I guess both are DesignWare-based, so
> >  > >> maybe this is the  > > same underlying problem in both cases?).  I
> >  > >> think it's more likely  > > that we just haven't figured out the
> >  > >> right way to describe this in  the DT.
> >  > >>  >
> >  > >>  > Keystone is using an older version of the designware IP and it
> >  > >> > implements all of the interrupts in the application register
> >  > >> space  > unlike other newer version of the hardware. So I assume,
> >  > >> the version  > used on Layerscape is also an older version and the
> >  > >> both have same  > issue in terms of non standard platform interrupt
> >  > >> used for error  reporting.
> >  > >>  >
> >  > >>  > > I assume you have a Root Port with an AER capability, no MSI
> >  > >> > > capability, and no MSI-X capability, right?
> >  > >>  >
> >  > >>  > Has AER capability and both MSI and INTx (legacy) capability  >
> >  > >> > > What does its Interrupt  > > Pin register contain?  If it's
> >  > >> zero, it doesn't use INTx either, so  > > according to the spec it
> >  > >> should generate no interrupts.
> >  > >>  > >
> >  > >>  > At address offset 0x3C by default has a value of 1, but it is
> >  > >> writable  > by software. So default is INTx A.
> >  > >>
> >  > >>  0x3c is the Interrupt *Line*, which is read/write.  The Interrupt
> >  > >>  *Pin* is at 0x3d and should be read-only.
> >  > >>
> >  >
> >  > You are right. But default is 1 at this address.
> >  >
> >  > >>  Does your Keystone driver support MSI?  If so, since your Root
> >  > >> Port  supports MSI, I would think we would use that by default, and
> >  > >> the INTx  stuff wouldn't even matter.
> >  > >
> >  > > Layerscape is also shows "Both message signaled interrupts (MSI) and
> >  legacy INTx are supported."
> >  > > But both of them not work for AER interrupt when devices or root
> >  port report aer error.
> >  > > But another GIC interrupt line do.
> >  >
> >  > Same with Keystone. Even though both MSI and INTx are supported error
> >  > interrupt at root port is reported on a different interrupt line than
> >  > MSI/INTx. So for Power Management event interrupt is also different
> >  > line.
> >  
> >  I'm looking at the "Error Message Controls" diagram in the PCIe spec
> >  r3.0, sec 6.2.6.  Does this hardware fit into the platform-specific
> >  "System Error" case there?  Do the Root Control enable bits (in the PCIe
> >  Capability) control this interrupt?  If so, maybe this makes more sense
> >  than I thought.
> 
> It supposedly not the "System Error" case. But "the Error Interrupt" case.
> Which means " Root Error Command register " could control the interrupt
>  line we have now. (refer PCIe spec r3.0, sec 6.2.6)

Did you actually try this out and verify that the PCIe Root Control
enable bits have no effect and the AER Root Error Command bits do
control it?  The names are very similar, so there's lots of room for
misunderstanding here :)

If the AER Root Error Command does control this interrupt, I think the
PCI_COMMAND_INTX_DISABLE bit in the PCI Command register should also
control it (per sec 6.2.4.1.2).

> May this kind of hardware design route broken the spec? 

If the Reporting Enable bits in the Root Port's AER Root Error Command
register control the interrupt, but the interrupt is not delivered via
the Root Port's INTx or MSI/MSI-X, I think the design is not following
the spec.

All the information needed by the AER driver should be communicated
via the config space mechanisms described in the spec (AER capability,
MSI/MSI-X capabilities, Interrupt Pin, etc.)  That way the driver
works without change on future spec-compliant hardware.

> PME also like the AER. Hotplug is not supported. Others not known.
> Po Liu

Per sec 6.1.6, I think PME *should* be signaled by the Root Port's
INTx or MSI/MSI-X.

In particular, it says "Note that all other interrupt sources within
the same Function will assert the same virtual INTx wire when
requesting service."  To me, that means that if we're using INTx, it
will be the same INTx for AER, PME, hotplug, etc., and it should be
the one indicated by the Interrupt Pin register.

But I think on your Root Port:

  - There is an MSI capability, but MSI doesn't actually work at all
  - Interrupt Pin contains 1, indicating INTA, which is routed to IRQ X
  - AER interrupts are routed to some different IRQ Y
  - PME interrupts are routed to a third IRQ Z

So how should we work around this?  I think you should be able to get
partway there with a quirk that sets:

  dev->no_msi = 1;
  dev->irq = Y;

for this device.  That should make AER work, but of course PME would
not work.

Is there a way to set up your interrupt controller so these three
interrupts (X, Y, Z above) all map to the same Linux IRQ?  If you can
do that, you could set up INTA, the AER interrupt, and the PME
interrupt to all be on the same IRQ and everything should work.

Bjorn

RE: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Po Liu]

Hi Bjorn,

Thanks for the kindly reply. All these are helpful.

>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>  On Wed, June 08, 2016 6:47 AM
>  
>  On Tue, Jun 07, 2016 at 10:07:40AM +0000, Po Liu wrote:
>  > Hi Bjorn,
>  >
>  > >  -----Original Message-----
>  > >
>  > >  On Mon, Jun 06, 2016 at 10:01:44AM -0400, Murali Karicheri wrote:
>  > >  > On 06/06/2016 03:32 AM, Po Liu wrote:
>  > >  > > Hi Bjorn,
>  > >  > > I confirm we met same problem with KeyStone base on DesignWare
>  > > design.
>  > >  > >
>  > >  > >
>  > >  > > Best regards,
>  > >  > > Liu Po
>  > >  > >
>  > >  > >>  -----Original Message-----
>  > >  > >>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]  > >>  Sent:
>  > > Saturday, June 04, 2016 11:49 AM  > >>  To: Murali Karicheri  > >>
>  > > Cc: Po Liu; linux-pci@vger.kernel.org; linux-arm-  > >>
>  > > kernel@lists.infradead.org; linux-kernel@vger.kernel.org;  > >>
>  > > devicetree@vger.kernel.org; Arnd Bergmann; Roy Zang; Marc Zyngier;
>  > > > >> Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn Helgaas; Shawn
>  > > Guo;  > >> Mingkai Hu; Rob Herring  > >>  Subject: Re: [PATCH 2/2]
>  > > aer: add support aer interrupt with none  > >> MSI/MSI-X/INTx mode
>  > > > >>  > >>  On Fri, Jun 03, 2016 at 01:31:11PM -0400, Murali
>  > > Karicheri wrote:
>  > >  > >>  > Po,
>  > >  > >>  >
>  > >  > >>  > Sorry to hijack your discussion, but the problem seems to
>  > > be  > >> same for  > Keystone PCI controller which is also
>  > > designware (old
>  > >  version) based.
>  > >  > >>  >
>  > >  > >>  > On 06/03/2016 12:09 AM, Bjorn Helgaas wrote:
>  > >  > >>  > > On Thu, Jun 02, 2016 at 11:37:28AM -0400, Murali
>  > > Karicheri
>  > >  wrote:
>  > >  > >>  > >> On 06/02/2016 09:55 AM, Bjorn Helgaas wrote:
>  > >  > >>  > >>> On Thu, Jun 02, 2016 at 05:01:19AM +0000, Po Liu wrote:
>  > >  > >>  > >>>>>  -----Original Message-----  > >>>>>  From: Bjorn
>  > > Helgaas  > >> [mailto:helgaas@kernel.org]  > >>>>>  Sent: Thursday,
>  > > June 02, 2016  > >> 11:48 AM  > >>>>>  To: Po Liu  > >>>>>  Cc:
>  > >  > >> linux-pci@vger.kernel.org;  > >>>>>  > >>
>  > > linux-arm-kernel@lists.infradead.org;
>  > >  > >>  > >>>>>  linux-kernel@vger.kernel.org;
>  > > devicetree@vger.kernel.org;  > >> Arnd  > >>>>> Bergmann;  Roy Zang;
>  > > Marc Zyngier; Stuart Yoder;  > >> Yang-Leo Li;  > >>>>> Minghuan
>  > > Lian; Bjorn  Helgaas; Shawn Guo;  > >> Mingkai Hu; Rob  > >>>>>
>  > > Herring  > >>>>>  Subject: Re: [PATCH 2/2]  > >> aer: add support
>  > > aer interrupt with  > >>>>> none  MSI/MSI-X/INTx  > >> mode  > >>>>>
>  > > > >>>>>  [+cc Rob]  > >>>>>  > >>>>>  Hi Po,  >  > >> >>>>>  > >>>>>
>  > > On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu  > >> wrote:
>  > >  > >>  > >>>>>  > On some platforms, root port doesn't support  > >>
>  > > MSI/MSI-X/INTx  in RC mode.
>  > >  > >>  > >>>>>  > When chip support the aer interrupt with none  >
>  > > >> MSI/MSI-X/INTx  > >>>>> mode,  > maybe there is interrupt line
>  > > for  > >> aer pme etc. Search  > >>>>> the interrupt  > number in
>  > > the fdt  file.
>  > >  > >>  > >>>>>
>  > >  > >>  > >>>>>  My understanding is that AER interrupt signaling can
>  > > be  > >> done  > >>>>> via INTx,  MSI, or MSI-X (PCIe spec r3.0, sec
>  > > 6.2.4.1.2).
>  > >  > >>  > >>>>> Apparently your device  doesn't support MSI or MSI-X.
>  > > Are  > >> you  > >>>>> saying it doesn't support INTx  either?  How
>  > > is the  > >> interrupt  you're requesting here different from INTx?
>  > >  > >>  > >>>>
>  > >  > >>  > >>>> Layerscape use none of MSI or MSI-X or INTx to
>  > > indicate the  > >> > >>>> devices or root error in RC mode. But use
>  > > an independent SPI  > >> > >>>> interrupt(arm interrupt controller)
>  line.
>  > >  > >>  > >>>
>  > >  > >>  > >>> The Root Port is a PCI device and should follow the
>  > > normal  > >> PCI  > >>> rules for interrupts.  As far as I
>  > > understand, that  > >> means it  > >>> should use MSI, MSI-X, or
>  > > INTx.  If your Root Port  > >> doesn't use MSI  > >>> or MSI-X, it
>  > > should use INTx, the  > >> PCI_INTERRUPT_PIN register  > >>> should
>  > > tell us which (INTA/  > >> INTB/etc.), and  PCI_COMMAND_INTX_DISABLE
>  should work to disable it.
>  > >  > >>  > >>> That's all from the PCI point of view, of course.
>  > >  > >>  > >>
>  > >  > >>  > >> I am faced with the same issue on Keystone PCI hardware
>  > > and  > >> it has  > >> been on my TODO list  for quite some time.
>  > > Keystone  > >> PCI hardware  > >> also doesn't use MSI or MSI-X or
>  > > INTx for  > >> reporting errors received  > >> at the root port, but
>  > > use a  > >> platform interrupt instead (not  > >> complaint to PCI
>  > > standard as  > >> per PCI base spec). So I would need  > >> similar
>  > > change to have  > >> the error interrupt passed to the aer  > >>
>  > > driver. So there are  > >> hardware out there like Keystone which
>  > > requires to support this  through platform IRQ.
>  > >  > >>  > >
>  > >  > >>  > > This is not a new area of the spec, and it's hard for me
>  > > to  > >> believe  > > that these two new PCIe controllers are both
>  > > broken  > >> the same way  > > (although I guess both are
>  > > DesignWare-based, so  > >> maybe this is the  > > same underlying
>  > > problem in both cases?).  I  > >> think it's more likely  > > that
>  > > we just haven't figured out the  > >> right way to describe this in
>  the DT.
>  > >  > >>  >
>  > >  > >>  > Keystone is using an older version of the designware IP and
>  > > it  > >> > implements all of the interrupts in the application
>  > > register  > >> space  > unlike other newer version of the hardware.
>  > > So I assume,  > >> the version  > used on Layerscape is also an
>  > > older version and the  > >> both have same  > issue in terms of non
>  > > standard platform interrupt  > >> used for error  reporting.
>  > >  > >>  >
>  > >  > >>  > > I assume you have a Root Port with an AER capability, no
>  > > MSI  > >> > > capability, and no MSI-X capability, right?
>  > >  > >>  >
>  > >  > >>  > Has AER capability and both MSI and INTx (legacy)
>  > > capability  >  > >> > > What does its Interrupt  > > Pin register
>  > > contain?  If it's  > >> zero, it doesn't use INTx either, so  > >
>  > > according to the spec it  > >> should generate no interrupts.
>  > >  > >>  > >
>  > >  > >>  > At address offset 0x3C by default has a value of 1, but it
>  > > is  > >> writable  > by software. So default is INTx A.
>  > >  > >>
>  > >  > >>  0x3c is the Interrupt *Line*, which is read/write.  The
>  > > Interrupt  > >>  *Pin* is at 0x3d and should be read-only.
>  > >  > >>
>  > >  >
>  > >  > You are right. But default is 1 at this address.
>  > >  >
>  > >  > >>  Does your Keystone driver support MSI?  If so, since your
>  > > Root  > >> Port  supports MSI, I would think we would use that by
>  > > default, and  > >> the INTx  stuff wouldn't even matter.
>  > >  > >
>  > >  > > Layerscape is also shows "Both message signaled interrupts
>  > > (MSI) and  legacy INTx are supported."
>  > >  > > But both of them not work for AER interrupt when devices or
>  > > root  port report aer error.
>  > >  > > But another GIC interrupt line do.
>  > >  >
>  > >  > Same with Keystone. Even though both MSI and INTx are supported
>  > > error  > interrupt at root port is reported on a different interrupt
>  > > line than  > MSI/INTx. So for Power Management event interrupt is
>  > > also different  > line.
>  > >
>  > >  I'm looking at the "Error Message Controls" diagram in the PCIe
>  > > spec  r3.0, sec 6.2.6.  Does this hardware fit into the
>  > > platform-specific  "System Error" case there?  Do the Root Control
>  > > enable bits (in the PCIe
>  > >  Capability) control this interrupt?  If so, maybe this makes more
>  > > sense  than I thought.
>  >
>  > It supposedly not the "System Error" case. But "the Error Interrupt"
>  case.
>  > Which means " Root Error Command register " could control the
>  > interrupt  line we have now. (refer PCIe spec r3.0, sec 6.2.6)
>  
>  Did you actually try this out and verify that the PCIe Root Control
>  enable bits have no effect and the AER Root Error Command bits do
>  control it?  The names are very similar, so there's lots of room for
>  misunderstanding here :)

Yes, all these result were tested before reply.

>  
>  If the AER Root Error Command does control this interrupt, I think the
>  PCI_COMMAND_INTX_DISABLE bit in the PCI Command register should also
>  control it (per sec 6.2.4.1.2).

Yes, I am sure the PCI_COMMAND_INTX_DISABLE bit can also control this interrupt.

>  
>  > May this kind of hardware design route broken the spec?
>  
>  If the Reporting Enable bits in the Root Port's AER Root Error Command
>  register control the interrupt, but the interrupt is not delivered via
>  the Root Port's INTx or MSI/MSI-X, I think the design is not following
>  the spec.
>  
>  All the information needed by the AER driver should be communicated via
>  the config space mechanisms described in the spec (AER capability,
>  MSI/MSI-X capabilities, Interrupt Pin, etc.)  That way the driver works
>  without change on future spec-compliant hardware.
>  
>  > PME also like the AER. Hotplug is not supported. Others not known.
>  > Po Liu
>  
>  Per sec 6.1.6, I think PME *should* be signaled by the Root Port's INTx
>  or MSI/MSI-X.
>  
>  In particular, it says "Note that all other interrupt sources within the
>  same Function will assert the same virtual INTx wire when requesting
>  service."  To me, that means that if we're using INTx, it will be the
>  same INTx for AER, PME, hotplug, etc., and it should be the one
>  indicated by the Interrupt Pin register.
>  
>  But I think on your Root Port:
>  
>    - There is an MSI capability, but MSI doesn't actually work at all
>    - Interrupt Pin contains 1, indicating INTA, which is routed to IRQ X
>    - AER interrupts are routed to some different IRQ Y
>    - PME interrupts are routed to a third IRQ Z
>  

The descriptions are all right.

>  So how should we work around this?  I think you should be able to get
>  partway there with a quirk that sets:
>  
>    dev->no_msi = 1;
>    dev->irq = Y;
>  
>  for this device.  That should make AER work, but of course PME would not
>  work.
>  
>  Is there a way to set up your interrupt controller so these three
>  interrupts (X, Y, Z above) all map to the same Linux IRQ?  If you can do
>  that, you could set up INTA, the AER interrupt, and the PME interrupt to
>  all be on the same IRQ and everything should work.
>  
>  Bjorn

We'll think about all the ways. It is really helpful, thanks!  

[PATCH v2 1/2] nxp/dts: add pcie aer interrupt-name property in the dts

[Po Liu]

NXP some platforms aer interrupt was not MSI/MSI-X/INTx
but using interrupt line independently. This patch add a "aer"
interrupt-names for aer interrupt.

Signed-off-by: Po Liu <po.liu@nxp.com>
---
Changes for V2:
	- None.

 .../devicetree/bindings/pci/layerscape-pci.txt         |  4 ++--
 arch/arm/boot/dts/ls1021a.dtsi                         |  6 ++++--
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi         | 18 +++++++++---------
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi         | 16 ++++++++--------
 4 files changed, 23 insertions(+), 21 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index ef683b2..d27973a 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -19,7 +19,7 @@ Required properties:
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
 - interrupt-names: Must include the following entries:
-  "intr": The interrupt that is asserted for controller interrupts
+  "aer" : The interrupt that is asserted for aer interrupts
 - fsl,pcie-scfg: Must include two entries.
   The first entry must be a link to the SCFG device node
   The second entry must be '0' or '1' based on physical PCIe controller index.
@@ -33,7 +33,7 @@ Example:
 		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 		reg-names = "regs", "config";
 		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-		interrupt-names = "intr";
+		interrupt-names = "aer";
 		fsl,pcie-scfg = <&scfg 0>;
 		#address-cells = <3>;
 		#size-cells = <2>;
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 5ae8e92..b638697 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -633,7 +633,8 @@
 			reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
 			fsl,pcie-scfg = <&scfg 0>;
 			#address-cells = <3>;
 			#size-cells = <2>;
@@ -656,7 +657,8 @@
 			reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
 			fsl,pcie-scfg = <&scfg 1>;
 			#address-cells = <3>;
 			#size-cells = <2>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index de0323b..4beb760 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -473,9 +473,9 @@
 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 118 0x4>, /* controller interrupt */
-				     <0 117 0x4>; /* PME interrupt */
-			interrupt-names = "intr", "pme";
+			interrupts = <0 117 0x4>, /* PME interrupt */
+					 <0 118 0x4>; /* aer interrupt */
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -497,9 +497,9 @@
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 128 0x4>,
-				     <0 127 0x4>;
-			interrupt-names = "intr", "pme";
+			interrupts = <0 127 0x4>,
+					 <0 128 0x4>;
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -521,9 +521,9 @@
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 162 0x4>,
-				     <0 161 0x4>;
-			interrupt-names = "intr", "pme";
+			interrupts = <0 161 0x4>,
+					 <0 162 0x4>;
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 3187c82..6edf24b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -559,8 +559,8 @@
 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 			       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 108 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 108 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -583,8 +583,8 @@
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 			       0x12 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 113 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 113 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -607,8 +607,8 @@
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 			       0x14 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 118 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 118 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -631,8 +631,8 @@
 			reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
 			       0x16 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 123 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 123 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-- 
2.1.0.27.g96db324

[PATCH v2 2/2] pci/aer: interrupt fixup in the quirk

[Po Liu]

On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.

Signed-off-by: Po Liu <po.liu@nxp.com>
---
changes for V2:
	- Move to the quirk file

 drivers/pci/quirks.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ee72ebe..909d479 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
 #include <linux/sched.h>
 #include <linux/ktime.h>
 #include <linux/mm.h>
+#include <linux/of_irq.h>
 #include <asm/dma.h>	/* isa_dma_bridge_buggy */
 #include "pci.h"
 
@@ -4419,3 +4420,25 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
 	}
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
+
+/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+ * but use standalone irq. Read the device tree for the aer
+ * interrupt number.
+ */
+static void quirk_aer_interrupt(struct pci_dev *dev)
+{
+	int ret;
+	struct device_node *np = NULL;
+
+	if (dev->bus->dev.of_node)
+		np = dev->bus->dev.of_node;
+
+	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
+		ret = of_irq_get_byname(np, "aer");
+		if (ret > 0) {
+			dev->no_msi = 1;
+			dev->irq = ret;
+		}
+	}
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_aer_interrupt);
-- 
2.1.0.27.g96db324

[PATCH v3 1/2] nxp/dts: add pcie aer interrupt-name property in the dts

[Po Liu]

NXP some platforms aer interrupt was not MSI/MSI-X/INTx
but using interrupt line independently. This patch add a "aer"
interrupt-names for aer interrupt.

Signed-off-by: Po Liu <po.liu@nxp.com>
---
changes for v3:
	- None;

 .../devicetree/bindings/pci/layerscape-pci.txt         |  4 ++--
 arch/arm/boot/dts/ls1021a.dtsi                         |  6 ++++--
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi         | 18 +++++++++---------
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi         | 16 ++++++++--------
 4 files changed, 23 insertions(+), 21 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index ef683b2..d27973a 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -19,7 +19,7 @@ Required properties:
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
 - interrupt-names: Must include the following entries:
-  "intr": The interrupt that is asserted for controller interrupts
+  "aer" : The interrupt that is asserted for aer interrupts
 - fsl,pcie-scfg: Must include two entries.
   The first entry must be a link to the SCFG device node
   The second entry must be '0' or '1' based on physical PCIe controller index.
@@ -33,7 +33,7 @@ Example:
 		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 		reg-names = "regs", "config";
 		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-		interrupt-names = "intr";
+		interrupt-names = "aer";
 		fsl,pcie-scfg = <&scfg 0>;
 		#address-cells = <3>;
 		#size-cells = <2>;
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 5ae8e92..b638697 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -633,7 +633,8 @@
 			reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
 			fsl,pcie-scfg = <&scfg 0>;
 			#address-cells = <3>;
 			#size-cells = <2>;
@@ -656,7 +657,8 @@
 			reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
 			fsl,pcie-scfg = <&scfg 1>;
 			#address-cells = <3>;
 			#size-cells = <2>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index de0323b..4beb760 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -473,9 +473,9 @@
 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 118 0x4>, /* controller interrupt */
-				     <0 117 0x4>; /* PME interrupt */
-			interrupt-names = "intr", "pme";
+			interrupts = <0 117 0x4>, /* PME interrupt */
+					 <0 118 0x4>; /* aer interrupt */
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -497,9 +497,9 @@
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 128 0x4>,
-				     <0 127 0x4>;
-			interrupt-names = "intr", "pme";
+			interrupts = <0 127 0x4>,
+					 <0 128 0x4>;
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -521,9 +521,9 @@
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 162 0x4>,
-				     <0 161 0x4>;
-			interrupt-names = "intr", "pme";
+			interrupts = <0 161 0x4>,
+					 <0 162 0x4>;
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 3187c82..6edf24b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -559,8 +559,8 @@
 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 			       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 108 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 108 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -583,8 +583,8 @@
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 			       0x12 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 113 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 113 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -607,8 +607,8 @@
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 			       0x14 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 118 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 118 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -631,8 +631,8 @@
 			reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
 			       0x16 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 123 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 123 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-- 
2.1.0.27.g96db324

[PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Po Liu]

On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.

Signed-off-by: Po Liu <po.liu@nxp.com>
---
changes for V3:
	- Move to quirk;
	- Only correct the irq in RC mode;

 drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ee72ebe..8b39cce 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
 #include <linux/sched.h>
 #include <linux/ktime.h>
 #include <linux/mm.h>
+#include <linux/of_irq.h>
 #include <asm/dma.h>	/* isa_dma_bridge_buggy */
 #include "pci.h"
 
@@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
 	}
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
+
+/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+ * but use standalone irq. Read the device tree for the aer
+ * interrupt number.
+ */
+static void quirk_aer_interrupt(struct pci_dev *dev)
+{
+	int ret;
+	u8 header_type;
+	struct device_node *np = NULL;
+
+	/* Only for the RC mode device */
+	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
+	if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
+		return;
+
+	if (dev->bus->dev.of_node)
+		np = dev->bus->dev.of_node;
+
+	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
+		ret = of_irq_get_byname(np, "aer");
+		if (ret > 0) {
+			dev->no_msi = 1;
+			dev->irq = ret;
+		}
+	}
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_aer_interrupt);
-- 
2.1.0.27.g96db324

Re: [PATCH v3 1/2] nxp/dts: add pcie aer interrupt-name property in the dts

[Shawn Guo]

On Tue, Jun 14, 2016 at 04:24:04PM +0800, Po Liu wrote:
> NXP some platforms aer interrupt was not MSI/MSI-X/INTx
> but using interrupt line independently. This patch add a "aer"
> interrupt-names for aer interrupt.
> 
> Signed-off-by: Po Liu <po.liu@nxp.com>
> ---
> changes for v3:
> 	- None;
> 
>  .../devicetree/bindings/pci/layerscape-pci.txt         |  4 ++--

The bindings shouldn't be part of dts patch but the driver patch who
is actually using it.

Shawn

>  arch/arm/boot/dts/ls1021a.dtsi                         |  6 ++++--
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi         | 18 +++++++++---------
>  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi         | 16 ++++++++--------
>  4 files changed, 23 insertions(+), 21 deletions(-)

RE: [PATCH v3 1/2] nxp/dts: add pcie aer interrupt-name property in the dts

[Po Liu]

Hi Shawn,

>  -----Original Message-----
>  From: Shawn Guo [mailto:shawnguo@kernel.org]
>  Sent: Thursday, June 16, 2016 8:36 AM
>  To: Po Liu
>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang; Arnd
>  Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Murali
>  Karicheri; Bjorn Helgaas; Mingkai Hu
>  Subject: Re: [PATCH v3 1/2] nxp/dts: add pcie aer interrupt-name
>  property in the dts
>  
>  On Tue, Jun 14, 2016 at 04:24:04PM +0800, Po Liu wrote:
>  > NXP some platforms aer interrupt was not MSI/MSI-X/INTx but using
>  > interrupt line independently. This patch add a "aer"
>  > interrupt-names for aer interrupt.
>  >
>  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  > ---
>  > changes for v3:
>  > 	- None;
>  >
>  >  .../devicetree/bindings/pci/layerscape-pci.txt         |  4 ++--
>  
>  The bindings shouldn't be part of dts patch but the driver patch who is
>  actually using it.
>  
>  Shawn

Ok, I'll move the doc part to the driver patch.

Po Liu
From NXP
>  
>  >  arch/arm/boot/dts/ls1021a.dtsi                         |  6 ++++--
>  >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi         | 18
>  +++++++++---------
>  >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi         | 16 ++++++++-
>  -------
>  >  4 files changed, 23 insertions(+), 21 deletions(-)

Re: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk

[Bjorn Helgaas]

On Tue, Jun 14, 2016 at 02:12:27PM +0800, Po Liu wrote:
> On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> maybe there is interrupt line for aer pme etc. Search the interrupt
> number in the fdt file. Then fixup the dev->irq with it.
> 
> Signed-off-by: Po Liu <po.liu@nxp.com>
> ---
> changes for V2:
> 	- Move to the quirk file
> 
>  drivers/pci/quirks.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index ee72ebe..909d479 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c

Is there any possibility of this part being used on different arches,
or will it only ever be on arm64 (or whatever it is)?  If the latter,
it could go somewhere like arch/arm64/kernel/quirks.c (which doesn't
exist yet).

> @@ -25,6 +25,7 @@
>  #include <linux/sched.h>
>  #include <linux/ktime.h>
>  #include <linux/mm.h>
> +#include <linux/of_irq.h>
>  #include <asm/dma.h>	/* isa_dma_bridge_buggy */
>  #include "pci.h"
>  
> @@ -4419,3 +4420,25 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
>  	}
>  }
>  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
> +
> +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> + * but use standalone irq. Read the device tree for the aer
> + * interrupt number.
> + */
> +static void quirk_aer_interrupt(struct pci_dev *dev)
> +{
> +	int ret;
> +	struct device_node *np = NULL;
> +
> +	if (dev->bus->dev.of_node)
> +		np = dev->bus->dev.of_node;
> +
> +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> +		ret = of_irq_get_byname(np, "aer");
> +		if (ret > 0) {
> +			dev->no_msi = 1;
> +			dev->irq = ret;
> +		}
> +	}

What does this mean for the other PCIe services, e.g., PME?  I
guess this makes the existing AER code work unchanged.  But I thought
PME had a similar situation and was connected up to a different
interrupt than AER was.

> +}
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_aer_interrupt);
> -- 
> 2.1.0.27.g96db324
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v3 1/2] nxp/dts: add pcie aer interrupt-name property in the dts

[Rob Herring]

On Tue, Jun 14, 2016 at 04:24:04PM +0800, Po Liu wrote:
> NXP some platforms aer interrupt was not MSI/MSI-X/INTx
> but using interrupt line independently. This patch add a "aer"
> interrupt-names for aer interrupt.

Please put your explanation why this is okay to change in the commit 
message.

> 
> Signed-off-by: Po Liu <po.liu@nxp.com>
> ---
> changes for v3:
> 	- None;
> 
>  .../devicetree/bindings/pci/layerscape-pci.txt         |  4 ++--
>  arch/arm/boot/dts/ls1021a.dtsi                         |  6 ++++--
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi         | 18 +++++++++---------
>  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi         | 16 ++++++++--------
>  4 files changed, 23 insertions(+), 21 deletions(-)

RE: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk

[Po Liu]

>  -----Original Message-----
>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>  Sent: Thursday, June 16, 2016 9:54 PM
>  To: Po Liu
>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Bjorn Helgaas;
>  Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang; Mingkai Hu; Stuart Yoder;
>  Yang-Leo Li; Arnd Bergmann; Minghuan Lian; Murali Karicheri
>  Subject: Re: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
>  
>  On Tue, Jun 14, 2016 at 02:12:27PM +0800, Po Liu wrote:
>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
>  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
>  > maybe there is interrupt line for aer pme etc. Search the interrupt
>  > number in the fdt file. Then fixup the dev->irq with it.
>  >
>  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  > ---
>  > changes for V2:
>  > 	- Move to the quirk file
>  >
>  >  drivers/pci/quirks.c | 23 +++++++++++++++++++++++
>  >  1 file changed, 23 insertions(+)
>  >
>  > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
>  > ee72ebe..909d479 100644
>  > --- a/drivers/pci/quirks.c
>  > +++ b/drivers/pci/quirks.c
>  
>  Is there any possibility of this part being used on different arches, or
>  will it only ever be on arm64 (or whatever it is)?  If the latter, it
>  could go somewhere like arch/arm64/kernel/quirks.c (which doesn't exist
>  yet).

NXP Layerscape1 is base on the arm 32bit design. Also need the fixup.

>  
>  > @@ -25,6 +25,7 @@
>  >  #include <linux/sched.h>
>  >  #include <linux/ktime.h>
>  >  #include <linux/mm.h>
>  > +#include <linux/of_irq.h>
>  >  #include <asm/dma.h>	/* isa_dma_bridge_buggy */
>  >  #include "pci.h"
>  >
>  > @@ -4419,3 +4420,25 @@ static void quirk_intel_qat_vf_cap(struct
>  pci_dev *pdev)
>  >  	}
>  >  }
>  >  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
>  > quirk_intel_qat_vf_cap);
>  > +
>  > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
>  > + * but use standalone irq. Read the device tree for the aer
>  > + * interrupt number.
>  > + */
>  > +static void quirk_aer_interrupt(struct pci_dev *dev) {
>  > +	int ret;
>  > +	struct device_node *np = NULL;
>  > +
>  > +	if (dev->bus->dev.of_node)
>  > +		np = dev->bus->dev.of_node;
>  > +
>  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
>  > +		ret = of_irq_get_byname(np, "aer");
>  > +		if (ret > 0) {
>  > +			dev->no_msi = 1;
>  > +			dev->irq = ret;
>  > +		}
>  > +	}
>  
>  What does this mean for the other PCIe services, e.g., PME?  I guess
>  this makes the existing AER code work unchanged.  But I thought PME had
>  a similar situation and was connected up to a different interrupt than
>  AER was.

Yes, PME is similar, HP is not support. I think better to disable the PME service irq in the quirk.
But seems it is no use because quirk fixup is only running in init phase time(except suspend, resume).

>  
>  > +}
>  > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
>  > +quirk_aer_interrupt);
>  > --
>  > 2.1.0.27.g96db324
>  >
>  > --
>  > To unsubscribe from this list: send the line "unsubscribe linux-pci"
>  > in the body of a message to majordomo@vger.kernel.org More majordomo
>  > info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Dongdong Liu]

在 2016/6/14 16:24, Po Liu 写道:
> On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> maybe there is interrupt line for aer pme etc. Search the interrupt
> number in the fdt file. Then fixup the dev->irq with it.
>
> Signed-off-by: Po Liu <po.liu@nxp.com>
> ---
> changes for V3:
> 	- Move to quirk;
> 	- Only correct the irq in RC mode;
>
>   drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++
>   1 file changed, 29 insertions(+)
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index ee72ebe..8b39cce 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -25,6 +25,7 @@
>   #include <linux/sched.h>
>   #include <linux/ktime.h>
>   #include <linux/mm.h>
> +#include <linux/of_irq.h>
>   #include <asm/dma.h>	/* isa_dma_bridge_buggy */
>   #include "pci.h"
>
> @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
>   	}
>   }
>   DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
> +
> +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> + * but use standalone irq. Read the device tree for the aer
> + * interrupt number.
> + */
> +static void quirk_aer_interrupt(struct pci_dev *dev)
> +{
> +	int ret;
> +	u8 header_type;
> +	struct device_node *np = NULL;
> +
> +	/* Only for the RC mode device */
> +	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
> +	if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> +		return;

How about that it is changed as below.

/* Only for the RC mode device */
if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
	return;

Dongdong
Thanks
> +
> +	if (dev->bus->dev.of_node)
> +		np = dev->bus->dev.of_node;
> +
> +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> +		ret = of_irq_get_byname(np, "aer");
> +		if (ret > 0) {
> +			dev->no_msi = 1;
> +			dev->irq = ret;
> +		}
> +	}
> +}
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_aer_interrupt);
>

RE: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Po Liu]

Hi Dongdong,

>  -----Original Message-----
>  From: Dongdong Liu [mailto:liudongdong3@huawei.com]
>  Sent: Thursday, June 23, 2016 1:44 PM
>  To: Po Liu; linux-pci@vger.kernel.org; linux-arm-
>  kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
>  devicetree@vger.kernel.org
>  Cc: Bjorn Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang;
>  Mingkai Hu; Stuart Yoder; Yang-Leo Li; Arnd Bergmann; Minghuan Lian;
>  Murali Karicheri
>  Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>  
>  
>  
>  在 2016/6/14 16:24, Po Liu 写道:
>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
>  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
>  > maybe there is interrupt line for aer pme etc. Search the interrupt
>  > number in the fdt file. Then fixup the dev->irq with it.
>  >
>  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  > ---
>  > changes for V3:
>  > 	- Move to quirk;
>  > 	- Only correct the irq in RC mode;
>  >
>  >   drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++
>  >   1 file changed, 29 insertions(+)
>  >
>  > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
>  > ee72ebe..8b39cce 100644
>  > --- a/drivers/pci/quirks.c
>  > +++ b/drivers/pci/quirks.c
>  > @@ -25,6 +25,7 @@
>  >   #include <linux/sched.h>
>  >   #include <linux/ktime.h>
>  >   #include <linux/mm.h>
>  > +#include <linux/of_irq.h>
>  >   #include <asm/dma.h>	/* isa_dma_bridge_buggy */
>  >   #include "pci.h"
>  >
>  > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
>  pci_dev *pdev)
>  >   	}
>  >   }
>  >   DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
>  > quirk_intel_qat_vf_cap);
>  > +
>  > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
>  > + * but use standalone irq. Read the device tree for the aer
>  > + * interrupt number.
>  > + */
>  > +static void quirk_aer_interrupt(struct pci_dev *dev) {
>  > +	int ret;
>  > +	u8 header_type;
>  > +	struct device_node *np = NULL;
>  > +
>  > +	/* Only for the RC mode device */
>  > +	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
>  > +	if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
>  > +		return;
>  
>  How about that it is changed as below.
>  
>  /* Only for the RC mode device */
>  if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
>  	return;
>  
>  Dongdong
>  Thanks
Yes, it is also ok to read the capability register. 
We see it is common used to read the header type register that is why we use in this way.

>  > +
>  > +	if (dev->bus->dev.of_node)
>  > +		np = dev->bus->dev.of_node;
>  > +
>  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
>  > +		ret = of_irq_get_byname(np, "aer");
>  > +		if (ret > 0) {
>  > +			dev->no_msi = 1;
>  > +			dev->irq = ret;
>  > +		}
>  > +	}
>  > +}
>  > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
>  > +quirk_aer_interrupt);
>  >

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RE: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk

[Po Liu]

Hi Bjorn,

So could we keep it in the pci/quirk.c ? 
If yes, I would only move the binding description in the documentation into this driver the next version.

>  -----Original Message-----
>  From: Po Liu
>  Sent: Friday, June 17, 2016 11:31 AM
>  To: 'Bjorn Helgaas'
>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Bjorn Helgaas;
>  Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang; Mingkai Hu; Stuart Yoder;
>  Yang-Leo Li; Arnd Bergmann; Minghuan Lian; Murali Karicheri
>  Subject: RE: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
>  
>  
>  
>  >  -----Original Message-----
>  >  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>  >  Sent: Thursday, June 16, 2016 9:54 PM
>  >  To: Po Liu
>  >  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>  >  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Bjorn
>  > Helgaas;  Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang; Mingkai Hu;
>  > Stuart Yoder;  Yang-Leo Li; Arnd Bergmann; Minghuan Lian; Murali
>  > Karicheri
>  >  Subject: Re: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
>  >
>  >  On Tue, Jun 14, 2016 at 02:12:27PM +0800, Po Liu wrote:
>  >  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC
>  mode.
>  >  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
>  > > maybe there is interrupt line for aer pme etc. Search the interrupt
>  > > number in the fdt file. Then fixup the dev->irq with it.
>  >  >
>  >  > Signed-off-by: Po Liu <po.liu@nxp.com>  > ---  > changes for V2:
>  >  > 	- Move to the quirk file
>  >  >
>  >  >  drivers/pci/quirks.c | 23 +++++++++++++++++++++++  >  1 file
>  > changed, 23 insertions(+)  >  > diff --git a/drivers/pci/quirks.c
>  > b/drivers/pci/quirks.c index  > ee72ebe..909d479 100644  > ---
>  > a/drivers/pci/quirks.c  > +++ b/drivers/pci/quirks.c
>  >
>  >  Is there any possibility of this part being used on different arches,
>  > or  will it only ever be on arm64 (or whatever it is)?  If the latter,
>  > it  could go somewhere like arch/arm64/kernel/quirks.c (which doesn't
>  > exist  yet).
>  
>  NXP Layerscape1 is base on the arm 32bit design. Also need the fixup.
>  
>  >
>  >  > @@ -25,6 +25,7 @@
>  >  >  #include <linux/sched.h>
>  >  >  #include <linux/ktime.h>
>  >  >  #include <linux/mm.h>
>  >  > +#include <linux/of_irq.h>
>  >  >  #include <asm/dma.h>	/* isa_dma_bridge_buggy */
>  >  >  #include "pci.h"
>  >  >
>  >  > @@ -4419,3 +4420,25 @@ static void quirk_intel_qat_vf_cap(struct
>  > pci_dev *pdev)
>  >  >  	}
>  >  >  }
>  >  >  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,  >
>  > quirk_intel_qat_vf_cap);  > +  > +/* If root port doesn't support
>  > MSI/MSI-X/INTx in RC mode,  > + * but use standalone irq. Read the
>  > device tree for the aer  > + * interrupt number.
>  >  > + */
>  >  > +static void quirk_aer_interrupt(struct pci_dev *dev) {
>  >  > +	int ret;
>  >  > +	struct device_node *np = NULL;
>  >  > +
>  >  > +	if (dev->bus->dev.of_node)
>  >  > +		np = dev->bus->dev.of_node;
>  >  > +
>  >  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
>  >  > +		ret = of_irq_get_byname(np, "aer");
>  >  > +		if (ret > 0) {
>  >  > +			dev->no_msi = 1;
>  >  > +			dev->irq = ret;
>  >  > +		}
>  >  > +	}
>  >
>  >  What does this mean for the other PCIe services, e.g., PME?  I guess
>  > this makes the existing AER code work unchanged.  But I thought PME
>  > had  a similar situation and was connected up to a different interrupt
>  > than  AER was.
>  
>  Yes, PME is similar, HP is not support. I think better to disable the
>  PME service irq in the quirk.
>  But seems it is no use because quirk fixup is only running in init phase
>  time(except suspend, resume).
>  
>  >
>  >  > +}
>  >  > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,  >
>  > +quirk_aer_interrupt);  > --  > 2.1.0.27.g96db324  >  > --  > To
>  > unsubscribe from this list: send the line "unsubscribe linux-pci"
>  >  > in the body of a message to majordomo@vger.kernel.org More
>  > majordomo  > info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Dongdong Liu]

Hi Po

I found a problem with the similar patch. as the below log.

[    4.287060] pci 0000:80:00.0: quirk_aer_interrupt dev->irq 416
[    4.293778] pcieport 0000:80:00.0: pci_device_probe in
[    4.299605] pcieport 0000:80:00.0: of_irq_parse_pci() failed with rc=-22
[    4.307209] pcieport 0000:80:00.0: init_service_irqs  dev->irq 0

The fucntions are called as below sequence.
1. quirk_aer_interrupt, get the aer dev->irq 416.
2. pci_device_probe->of_irq_parse_pci, of_irq_parse_pci() failed, then dev->irq changed to 0.

So this patch could not work with aer.

Thanks
Dongdong
在 2016/6/14 16:24, Po Liu 写道:
> On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> maybe there is interrupt line for aer pme etc. Search the interrupt
> number in the fdt file. Then fixup the dev->irq with it.
>
> Signed-off-by: Po Liu <po.liu@nxp.com>
> ---
> changes for V3:
> 	- Move to quirk;
> 	- Only correct the irq in RC mode;
>
>   drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++
>   1 file changed, 29 insertions(+)
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index ee72ebe..8b39cce 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -25,6 +25,7 @@
>   #include <linux/sched.h>
>   #include <linux/ktime.h>
>   #include <linux/mm.h>
> +#include <linux/of_irq.h>
>   #include <asm/dma.h>	/* isa_dma_bridge_buggy */
>   #include "pci.h"
>
> @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
>   	}
>   }
>   DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
> +
> +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> + * but use standalone irq. Read the device tree for the aer
> + * interrupt number.
> + */
> +static void quirk_aer_interrupt(struct pci_dev *dev)
> +{
> +	int ret;
> +	u8 header_type;
> +	struct device_node *np = NULL;
> +
> +	/* Only for the RC mode device */
> +	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
> +	if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> +		return;
> +
> +	if (dev->bus->dev.of_node)
> +		np = dev->bus->dev.of_node;
> +
> +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> +		ret = of_irq_get_byname(np, "aer");
> +		if (ret > 0) {
> +			dev->no_msi = 1;
> +			dev->irq = ret;
> +		}
> +	}
> +}
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_aer_interrupt);
>

RE: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Po Liu]

Hi Dongdong,

The patch were intend to fixup the NXP layerscape serial SOC and were tested ok.
I am not clear what platform are you trying to fix. 
The problem on your board may be as below comments:


>  -----Original Message-----
>  From: Dongdong Liu [mailto:liudongdong3@huawei.com]
>  Sent: Monday, July 04, 2016 4:44 PM
>  To: Po Liu; linux-pci@vger.kernel.org; linux-arm-
>  kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
>  devicetree@vger.kernel.org
>  Cc: Bjorn Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang;
>  Mingkai Hu; Stuart Yoder; Yang-Leo Li; Arnd Bergmann; Minghuan Lian;
>  Murali Karicheri; Linuxarm
>  Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>  
>  Hi Po
>  
>  I found a problem with the similar patch. as the below log.
>  
>  [    4.287060] pci 0000:80:00.0: quirk_aer_interrupt dev->irq 416
>  [    4.293778] pcieport 0000:80:00.0: pci_device_probe in
>  [    4.299605] pcieport 0000:80:00.0: of_irq_parse_pci() failed with
>  rc=-22
>  [    4.307209] pcieport 0000:80:00.0: init_service_irqs  dev->irq 0
>  
>  The fucntions are called as below sequence.
>  1. quirk_aer_interrupt, get the aer dev->irq 416.

This code quirk_aer_interrupt() should be run at pci_fixup_device(pci_fixup_final) which is in the pci_bus_add_devices()

>  2. pci_device_probe->of_irq_parse_pci, of_irq_parse_pci() failed, then
>  dev->irq changed to 0.

pci_device_probe->of_irq_parse_pci which in the pci_scan_child_bus() run before  pci_bus_add_devices(). See dw_pcie_host_init().
Apparently , your quirk_aer_interrupt() is running before the dev->irq assignment in the of_irq_parse_pci().

So make sure your configure the quirk_aer_interrupt() run in the FINAL stage in the quirk.c OR check your host driver which you are using.


>  
>  So this patch could not work with aer.
>  
>  Thanks
>  Dongdong
>  在 2016/6/14 16:24, Po Liu 写道:
>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
>  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
>  > maybe there is interrupt line for aer pme etc. Search the interrupt
>  > number in the fdt file. Then fixup the dev->irq with it.
>  >
>  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  > ---
>  > changes for V3:
>  > 	- Move to quirk;
>  > 	- Only correct the irq in RC mode;
>  >
>  >   drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++
>  >   1 file changed, 29 insertions(+)
>  >
>  > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
>  > ee72ebe..8b39cce 100644
>  > --- a/drivers/pci/quirks.c
>  > +++ b/drivers/pci/quirks.c
>  > @@ -25,6 +25,7 @@
>  >   #include <linux/sched.h>
>  >   #include <linux/ktime.h>
>  >   #include <linux/mm.h>
>  > +#include <linux/of_irq.h>
>  >   #include <asm/dma.h>	/* isa_dma_bridge_buggy */
>  >   #include "pci.h"
>  >
>  > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
>  pci_dev *pdev)
>  >   	}
>  >   }
>  >   DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
>  > quirk_intel_qat_vf_cap);
>  > +
>  > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
>  > + * but use standalone irq. Read the device tree for the aer
>  > + * interrupt number.
>  > + */
>  > +static void quirk_aer_interrupt(struct pci_dev *dev) {
>  > +	int ret;
>  > +	u8 header_type;
>  > +	struct device_node *np = NULL;
>  > +
>  > +	/* Only for the RC mode device */
>  > +	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
>  > +	if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
>  > +		return;
>  > +
>  > +	if (dev->bus->dev.of_node)
>  > +		np = dev->bus->dev.of_node;
>  > +
>  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
>  > +		ret = of_irq_get_byname(np, "aer");
>  > +		if (ret > 0) {
>  > +			dev->no_msi = 1;
>  > +			dev->irq = ret;
>  > +		}
>  > +	}
>  > +}
>  > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
>  > +quirk_aer_interrupt);
>  >
>  

Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Dongdong Liu]

Hi Po

在 2016/7/5 11:03, Po Liu 写道:
> Hi Dongdong,
>
> The patch were intend to fixup the NXP layerscape serial SOC and were tested ok.
> I am not clear what platform are you trying to fix.

My platform is an ARM64 platform, PCIe host controller also use Synopsys Designware.

> The problem on your board may be as below comments:
>
>
>>   -----Original Message-----
>>   From: Dongdong Liu [mailto:liudongdong3@huawei.com]
>>   Sent: Monday, July 04, 2016 4:44 PM
>>   To: Po Liu; linux-pci@vger.kernel.org; linux-arm-
>>   kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
>>   devicetree@vger.kernel.org
>>   Cc: Bjorn Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang;
>>   Mingkai Hu; Stuart Yoder; Yang-Leo Li; Arnd Bergmann; Minghuan Lian;
>>   Murali Karicheri; Linuxarm
>>   Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>>
>>   Hi Po
>>
>>   I found a problem with the similar patch. as the below log.
>>
>>   [    4.287060] pci 0000:80:00.0: quirk_aer_interrupt dev->irq 416
>>   [    4.293778] pcieport 0000:80:00.0: pci_device_probe in
>>   [    4.299605] pcieport 0000:80:00.0: of_irq_parse_pci() failed with
>>   rc=-22
>>   [    4.307209] pcieport 0000:80:00.0: init_service_irqs  dev->irq 0
>>
>>   The fucntions are called as below sequence.
>>   1. quirk_aer_interrupt, get the aer dev->irq 416.
>
> This code quirk_aer_interrupt() should be run at pci_fixup_device(pci_fixup_final) which is in the pci_bus_add_devices()

Yes, you are right.

>
>>   2. pci_device_probe->of_irq_parse_pci, of_irq_parse_pci() failed, then
>>   dev->irq changed to 0.
>
> pci_device_probe->of_irq_parse_pci which in the pci_scan_child_bus() run before  pci_bus_add_devices(). See dw_pcie_host_init().
> Apparently , your quirk_aer_interrupt() is running before the dev->irq assignment in the of_irq_parse_pci().
>
> So make sure your configure the quirk_aer_interrupt() run in the FINAL stage in the quirk.c OR check your host driver which you are using.

Yes , It is FINAL stage in the quirk. I use DECLARE_PCI_FIXUP_FINAL.
I find it is the below patch affect this. (https://patchwork.kernel.org/patch/9170333/),
but the patch will be applied to linux 4.8. So the problem will also be existed.

ARM64: PCI: ACPI support for legacy IRQs parsing and consolidation with DT code
diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
index d5d3d26..b3b8a2c 100644
--- a/arch/arm64/kernel/pci.c
+++ b/arch/arm64/kernel/pci.c
@@ -51,11 +51,16 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
  }

  /*
- * Try to assign the IRQ number from DT when adding a new device
+ * Try to assign the IRQ number when probing a new device
   */
-int pcibios_add_device(struct pci_dev *dev)
+int pcibios_alloc_irq(struct pci_dev *dev)
  {
-   dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
+ if (acpi_disabled)
+         dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
+#ifdef CONFIG_ACPI
+ else
+         return acpi_pci_irq_enable(dev);
+#endif

         return 0;
  }

Thanks
Dongdong
>
>
>>
>>   So this patch could not work with aer.
>>
>>   Thanks
>>   Dongdong
>>   在 2016/6/14 16:24, Po Liu 写道:
>>   > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
>>   > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
>>   > maybe there is interrupt line for aer pme etc. Search the interrupt
>>   > number in the fdt file. Then fixup the dev->irq with it.
>>   >
>>   > Signed-off-by: Po Liu <po.liu@nxp.com>
>>   > ---
>>   > changes for V3:
>>   > 	- Move to quirk;
>>   > 	- Only correct the irq in RC mode;
>>   >
>>   >   drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++
>>   >   1 file changed, 29 insertions(+)
>>   >
>>   > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
>>   > ee72ebe..8b39cce 100644
>>   > --- a/drivers/pci/quirks.c
>>   > +++ b/drivers/pci/quirks.c
>>   > @@ -25,6 +25,7 @@
>>   >   #include <linux/sched.h>
>>   >   #include <linux/ktime.h>
>>   >   #include <linux/mm.h>
>>   > +#include <linux/of_irq.h>
>>   >   #include <asm/dma.h>	/* isa_dma_bridge_buggy */
>>   >   #include "pci.h"
>>   >
>>   > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
>>   pci_dev *pdev)
>>   >   	}
>>   >   }
>>   >   DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
>>   > quirk_intel_qat_vf_cap);
>>   > +
>>   > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
>>   > + * but use standalone irq. Read the device tree for the aer
>>   > + * interrupt number.
>>   > + */
>>   > +static void quirk_aer_interrupt(struct pci_dev *dev) {
>>   > +	int ret;
>>   > +	u8 header_type;
>>   > +	struct device_node *np = NULL;
>>   > +
>>   > +	/* Only for the RC mode device */
>>   > +	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
>>   > +	if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
>>   > +		return;
>>   > +
>>   > +	if (dev->bus->dev.of_node)
>>   > +		np = dev->bus->dev.of_node;
>>   > +
>>   > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
>>   > +		ret = of_irq_get_byname(np, "aer");
>>   > +		if (ret > 0) {
>>   > +			dev->no_msi = 1;
>>   > +			dev->irq = ret;
>>   > +		}
>>   > +	}
>>   > +}
>>   > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
>>   > +quirk_aer_interrupt);
>>   >
>>
>
> \x04�{.n�+�������+%��lzwm��b�맲��r��zX��\x1a\�)���w*\x1fjg���\x1e�����ݢj/���z�ޖ��2�ޙ���&�)ߡ�a��\x7f��\x1e�G���h�\x0f�j:+v���w�٥
>


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Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Bjorn Helgaas]

On Tue, Jun 14, 2016 at 04:24:05PM +0800, Po Liu wrote:
> On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> maybe there is interrupt line for aer pme etc. Search the interrupt
> number in the fdt file. Then fixup the dev->irq with it.
> 
> Signed-off-by: Po Liu <po.liu-3arQi8VN3Tc@public.gmane.org>

I'm not sure where we're at with this.  Dongdong had some issue
(possibly with a version of the quirk on a different platform?), and I
think the suggestion of explicitly checking for a root port device was
a good one.

So please update and repost this for next cycle.

> ---
> changes for V3:
> 	- Move to quirk;
> 	- Only correct the irq in RC mode;
> 
>  drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index ee72ebe..8b39cce 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -25,6 +25,7 @@
>  #include <linux/sched.h>
>  #include <linux/ktime.h>
>  #include <linux/mm.h>
> +#include <linux/of_irq.h>
>  #include <asm/dma.h>	/* isa_dma_bridge_buggy */
>  #include "pci.h"
>  
> @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
>  	}
>  }
>  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
> +
> +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> + * but use standalone irq. Read the device tree for the aer
> + * interrupt number.
> + */
> +static void quirk_aer_interrupt(struct pci_dev *dev)
> +{
> +	int ret;
> +	u8 header_type;
> +	struct device_node *np = NULL;
> +
> +	/* Only for the RC mode device */
> +	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
> +	if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> +		return;
> +
> +	if (dev->bus->dev.of_node)
> +		np = dev->bus->dev.of_node;
> +
> +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> +		ret = of_irq_get_byname(np, "aer");
> +		if (ret > 0) {
> +			dev->no_msi = 1;
> +			dev->irq = ret;
> +		}
> +	}
> +}
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_aer_interrupt);
> -- 
> 2.1.0.27.g96db324
> 
> 
> _______________________________________________
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> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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RE: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Po Liu]

Hi Bjorn,

Sorry for late reply.

I checked the updated kernel with Dongdong mentioned ACPI patch which was truly affected my quirk patch uploaded. So I suppose the quirk patch is not qualify to fix the bug.

I were keep thinking what your "explicitly checking for a root port device" meaning. Do you mean I should upload again the first version patch which fix it in the portdrv_core.c ? I would upload again if yes. 

Thanks!


Best regards,
Liu Po

>  -----Original Message-----
>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>  Sent: Saturday, July 30, 2016 6:42 AM
>  To: Po Liu
>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang; Arnd
>  Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Murali
>  Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
>  Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>  
>  On Tue, Jun 14, 2016 at 04:24:05PM +0800, Po Liu wrote:
>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
>  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
>  > maybe there is interrupt line for aer pme etc. Search the interrupt
>  > number in the fdt file. Then fixup the dev->irq with it.
>  >
>  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  
>  I'm not sure where we're at with this.  Dongdong had some issue
>  (possibly with a version of the quirk on a different platform?), and I
>  think the suggestion of explicitly checking for a root port device was a
>  good one.
>  
>  So please update and repost this for next cycle.
>  
>  > ---
>  > changes for V3:
>  > 	- Move to quirk;
>  > 	- Only correct the irq in RC mode;
>  >
>  >  drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++
>  >  1 file changed, 29 insertions(+)
>  >
>  > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
>  > ee72ebe..8b39cce 100644
>  > --- a/drivers/pci/quirks.c
>  > +++ b/drivers/pci/quirks.c
>  > @@ -25,6 +25,7 @@
>  >  #include <linux/sched.h>
>  >  #include <linux/ktime.h>
>  >  #include <linux/mm.h>
>  > +#include <linux/of_irq.h>
>  >  #include <asm/dma.h>	/* isa_dma_bridge_buggy */
>  >  #include "pci.h"
>  >
>  > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
>  pci_dev *pdev)
>  >  	}
>  >  }
>  >  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
>  > quirk_intel_qat_vf_cap);
>  > +
>  > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
>  > + * but use standalone irq. Read the device tree for the aer
>  > + * interrupt number.
>  > + */
>  > +static void quirk_aer_interrupt(struct pci_dev *dev) {
>  > +	int ret;
>  > +	u8 header_type;
>  > +	struct device_node *np = NULL;
>  > +
>  > +	/* Only for the RC mode device */
>  > +	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
>  > +	if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
>  > +		return;
>  > +
>  > +	if (dev->bus->dev.of_node)
>  > +		np = dev->bus->dev.of_node;
>  > +
>  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
>  > +		ret = of_irq_get_byname(np, "aer");
>  > +		if (ret > 0) {
>  > +			dev->no_msi = 1;
>  > +			dev->irq = ret;
>  > +		}
>  > +	}
>  > +}
>  > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
>  > +quirk_aer_interrupt);
>  > --
>  > 2.1.0.27.g96db324
>  >
>  >
>  > _______________________________________________
>  > linux-arm-kernel mailing list
>  > linux-arm-kernel@lists.infradead.org
>  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts

[Po Liu]

NXP some platforms aer interrupt was not MSI/MSI-X/INTx
but using interrupt line independently. This patch add a "aer"
interrupt-names for aer interrupt.
With the interrupt-names "aer", code could probe aer interrupt
line for pcie root port, replace the aer interrupt service irq.
This is intend to fixup the Layerscape platforms which aer interrupt
was not MSI/MSI-X/INTx, but using interrupt line independently.

Signed-off-by: Po Liu <po.liu@nxp.com>
---
changes for V4:
	- Add comments explain why to add this patch
	- Move the binding changes to pci code patch

 arch/arm/boot/dts/ls1021a.dtsi                 |  6 ++++--
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +++++++++---------
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 ++++++++--------
 3 files changed, 21 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..443e50b 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -634,7 +634,8 @@
 			reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
 			fsl,pcie-scfg = <&scfg 0>;
 			#address-cells = <3>;
 			#size-cells = <2>;
@@ -657,7 +658,8 @@
 			reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
 			fsl,pcie-scfg = <&scfg 1>;
 			#address-cells = <3>;
 			#size-cells = <2>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index e669fbd..654071d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -527,9 +527,9 @@
 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 118 0x4>, /* controller interrupt */
-				     <0 117 0x4>; /* PME interrupt */
-			interrupt-names = "intr", "pme";
+			interrupts = <0 117 0x4>, /* PME interrupt */
+					 <0 118 0x4>; /* aer interrupt */
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -552,9 +552,9 @@
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 128 0x4>,
-				     <0 127 0x4>;
-			interrupt-names = "intr", "pme";
+			interrupts = <0 127 0x4>,
+					 <0 128 0x4>;
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -577,9 +577,9 @@
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 162 0x4>,
-				     <0 161 0x4>;
-			interrupt-names = "intr", "pme";
+			interrupts = <0 161 0x4>,
+					 <0 162 0x4>;
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 21023a3..58844e8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -583,8 +583,8 @@
 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 			       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 108 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 108 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -607,8 +607,8 @@
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 			       0x12 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 113 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 113 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -631,8 +631,8 @@
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 			       0x14 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 118 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 118 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -655,8 +655,8 @@
 			reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
 			       0x16 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 123 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 123 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-- 
2.1.0.27.g96db324

[PATCH v4 2/2] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Po Liu]

On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.

Signed-off-by: Po Liu <po.liu@nxp.com>
---
Changes for v4:
	- re-use the patch changes in the root port driver;
	- add binding information;

 .../devicetree/bindings/pci/layerscape-pci.txt     |  4 +--
 drivers/pci/pcie/portdrv_core.c                    | 31 +++++++++++++++++++---
 2 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 41e9f55..1dfb1da 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -19,7 +19,7 @@ Required properties:
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
 - interrupt-names: Must include the following entries:
-  "intr": The interrupt that is asserted for controller interrupts
+  "aer": The interrupt that is asserted for aer interrupts
 - fsl,pcie-scfg: Must include two entries.
   The first entry must be a link to the SCFG device node
   The second entry must be '0' or '1' based on physical PCIe controller index.
@@ -36,7 +36,7 @@ Example:
 		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 		reg-names = "regs", "config";
 		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-		interrupt-names = "intr";
+		interrupt-names = "aer";
 		fsl,pcie-scfg = <&scfg 0>;
 		#address-cells = <3>;
 		#size-cells = <2>;
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index e9270b4..7c4943d 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -16,6 +16,7 @@
 #include <linux/slab.h>
 #include <linux/pcieport_if.h>
 #include <linux/aer.h>
+#include <linux/of_irq.h>
 
 #include "../pci.h"
 #include "portdrv.h"
@@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
 static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
 {
 	int i, irq = -1;
+	int ret;
+	struct device_node *np = NULL;
+
+	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
+		irqs[i] = 0;
+
+	if (dev->bus->dev.of_node)
+		np = dev->bus->dev.of_node;
+
+	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+	 * request irq for aer
+	 */
+	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
+			(mask & PCIE_PORT_SERVICE_PME)) {
+		ret = of_irq_get_byname(np, "aer");
+		if (ret > 0) {
+			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
+			if (dev->irq)
+				irq = dev->irq;
+			goto no_msi;
+		}
+	}
 
 	/*
 	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
@@ -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
 		irq = dev->irq;
 
  no_msi:
-	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
-		irqs[i] = irq;
+	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
+		if (!irqs[i])
+			irqs[i] = irq;
+	}
 	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
 
-	if (irq < 0)
+	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
 		return -ENODEV;
 	return 0;
 }
-- 
2.1.0.27.g96db324

Re: [PATCH v4 2/2] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Rob Herring]

On Wed, Aug 31, 2016 at 02:37:22PM +0800, Po Liu wrote:
> On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> maybe there is interrupt line for aer pme etc. Search the interrupt
> number in the fdt file. Then fixup the dev->irq with it.
> 
> Signed-off-by: Po Liu <po.liu@nxp.com>
> ---
> Changes for v4:
> 	- re-use the patch changes in the root port driver;
> 	- add binding information;
> 
>  .../devicetree/bindings/pci/layerscape-pci.txt     |  4 +--
>  drivers/pci/pcie/portdrv_core.c                    | 31 +++++++++++++++++++---
>  2 files changed, 30 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 41e9f55..1dfb1da 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -19,7 +19,7 @@ Required properties:
>  - interrupts: A list of interrupt outputs of the controller. Must contain an
>    entry for each entry in the interrupt-names property.
>  - interrupt-names: Must include the following entries:
> -  "intr": The interrupt that is asserted for controller interrupts
> +  "aer": The interrupt that is asserted for aer interrupts

You can't just change this. That breaks compatibility with old dts 
files. Plus, it is just a name. Why does it even matter? Not to mention 
having the name for a single irq is a bit pointless.

Rob

Re: [PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts

[Shawn Guo]

On Wed, Aug 31, 2016 at 02:37:21PM +0800, Po Liu wrote:
> NXP some platforms aer interrupt was not MSI/MSI-X/INTx
> but using interrupt line independently. This patch add a "aer"
> interrupt-names for aer interrupt.
> With the interrupt-names "aer", code could probe aer interrupt
> line for pcie root port, replace the aer interrupt service irq.
> This is intend to fixup the Layerscape platforms which aer interrupt
> was not MSI/MSI-X/INTx, but using interrupt line independently.
> 
> Signed-off-by: Po Liu <po.liu@nxp.com>
> ---
> changes for V4:
> 	- Add comments explain why to add this patch
> 	- Move the binding changes to pci code patch
> 
>  arch/arm/boot/dts/ls1021a.dtsi                 |  6 ++++--
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +++++++++---------
>  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 ++++++++--------

Do not mix up arm dts changes with arm64 ones.  Use separate patch
please.

Shawn

RE: [PATCH v4 2/2] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Po Liu]

Hi Rob,


Best regards,
Liu Po

>  -----Original Message-----
>  From: Rob Herring [mailto:robh@kernel.org]
>  Sent: Friday, September 02, 2016 11:17 PM
>  To: Po Liu
>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Bjorn Helgaas;
>  Shawn Guo; Marc Zyngier; Roy Zang; Mingkai Hu; Stuart Yoder; Yang-Leo Li;
>  Arnd Bergmann; Minghuan Lian; Murali Karicheri
>  Subject: Re: [PATCH v4 2/2] pci:aer: add support aer interrupt with none
>  MSI/MSI-X/INTx mode
>  
>  On Wed, Aug 31, 2016 at 02:37:22PM +0800, Po Liu wrote:
>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
>  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
>  > maybe there is interrupt line for aer pme etc. Search the interrupt
>  > number in the fdt file. Then fixup the dev->irq with it.
>  >
>  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  > ---
>  > Changes for v4:
>  > 	- re-use the patch changes in the root port driver;
>  > 	- add binding information;
>  >
>  >  .../devicetree/bindings/pci/layerscape-pci.txt     |  4 +--
>  >  drivers/pci/pcie/portdrv_core.c                    | 31
>  +++++++++++++++++++---
>  >  2 files changed, 30 insertions(+), 5 deletions(-)
>  >
>  > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > index 41e9f55..1dfb1da 100644
>  > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > @@ -19,7 +19,7 @@ Required properties:
>  >  - interrupts: A list of interrupt outputs of the controller. Must
>  contain an
>  >    entry for each entry in the interrupt-names property.
>  >  - interrupt-names: Must include the following entries:
>  > -  "intr": The interrupt that is asserted for controller interrupts
>  > +  "aer": The interrupt that is asserted for aer interrupts
>  
>  You can't just change this. That breaks compatibility with old dts files.
>  Plus, it is just a name. Why does it even matter? Not to mention having
>  the name for a single irq is a bit pointless.
Sorry, this binding comments maybe not clear. 
"aer" is just one of the interrupt names from host controller. There are "aer" "pme" and so on for further applications. 
This patch is to fix the Layerscape owning independent aer irq issue. So the 'aer' is used for this patch. The 'intr' will never be used, so removed.
I may remove the 'must include' for mis-understanding.

Thanks!

Po Liu

>  
>  Rob

Re: [PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts

[Bjorn Helgaas]

On Wed, Aug 31, 2016 at 02:37:21PM +0800, Po Liu wrote:
> NXP some platforms aer interrupt was not MSI/MSI-X/INTx
> but using interrupt line independently. This patch add a "aer"
> interrupt-names for aer interrupt.
> With the interrupt-names "aer", code could probe aer interrupt
> line for pcie root port, replace the aer interrupt service irq.
> This is intend to fixup the Layerscape platforms which aer interrupt
> was not MSI/MSI-X/INTx, but using interrupt line independently.
> 
> Signed-off-by: Po Liu <po.liu-3arQi8VN3Tc@public.gmane.org>

Rob and Shawn had comments here, and I'm not sure they ever got resolved.

> ---
> changes for V4:
> 	- Add comments explain why to add this patch
> 	- Move the binding changes to pci code patch
> 
>  arch/arm/boot/dts/ls1021a.dtsi                 |  6 ++++--
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +++++++++---------
>  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 ++++++++--------
>  3 files changed, 21 insertions(+), 19 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 368e219..443e50b 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -634,7 +634,8 @@
>  			reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
>  			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> +			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
> +			interrupt-names = "aer";
>  			fsl,pcie-scfg = <&scfg 0>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
> @@ -657,7 +658,8 @@
>  			reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
>  			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
> +			interrupt-names = "aer";
>  			fsl,pcie-scfg = <&scfg 1>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> index e669fbd..654071d 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> @@ -527,9 +527,9 @@
>  			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
>  			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 118 0x4>, /* controller interrupt */
> -				     <0 117 0x4>; /* PME interrupt */
> -			interrupt-names = "intr", "pme";
> +			interrupts = <0 117 0x4>, /* PME interrupt */
> +					 <0 118 0x4>; /* aer interrupt */
> +			interrupt-names = "pme", "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> @@ -552,9 +552,9 @@
>  			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
>  			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 128 0x4>,
> -				     <0 127 0x4>;
> -			interrupt-names = "intr", "pme";
> +			interrupts = <0 127 0x4>,
> +					 <0 128 0x4>;
> +			interrupt-names = "pme", "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> @@ -577,9 +577,9 @@
>  			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
>  			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 162 0x4>,
> -				     <0 161 0x4>;
> -			interrupt-names = "intr", "pme";
> +			interrupts = <0 161 0x4>,
> +					 <0 162 0x4>;
> +			interrupt-names = "pme", "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> index 21023a3..58844e8 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> @@ -583,8 +583,8 @@
>  			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
>  			       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 108 0x4>; /* Level high type */
> -			interrupt-names = "intr";
> +			interrupts = <0 108 0x4>; /* aer interrupt */
> +			interrupt-names = "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> @@ -607,8 +607,8 @@
>  			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
>  			       0x12 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 113 0x4>; /* Level high type */
> -			interrupt-names = "intr";
> +			interrupts = <0 113 0x4>; /* aer interrupt */
> +			interrupt-names = "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> @@ -631,8 +631,8 @@
>  			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
>  			       0x14 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 118 0x4>; /* Level high type */
> -			interrupt-names = "intr";
> +			interrupts = <0 118 0x4>; /* aer interrupt */
> +			interrupt-names = "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> @@ -655,8 +655,8 @@
>  			reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
>  			       0x16 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 123 0x4>; /* Level high type */
> -			interrupt-names = "intr";
> +			interrupts = <0 123 0x4>; /* aer interrupt */
> +			interrupt-names = "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> -- 
> 2.1.0.27.g96db324
> 
> --
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RE: [PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts

[Po Liu]

Hi Bjorn, Shawn, Rob,

Thanks for reply. I'll upload new patches:
 - separate the patches with arm and arm64 dts for new version.
 - Modify the binding comments to make it clear for explain the 'aer' property.

Best regards,
Liu Po

-----Original Message-----
From: Bjorn Helgaas [mailto:helgaas@kernel.org] 
Sent: Tuesday, September 13, 2016 6:14 AM
To: Po Liu
Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Bjorn Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang; Vincent Hu; Stuart Yoder; Leo Li; Arnd Bergmann; M.H. Lian; Murali Karicheri
Subject: Re: [PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts

On Wed, Aug 31, 2016 at 02:37:21PM +0800, Po Liu wrote:
> NXP some platforms aer interrupt was not MSI/MSI-X/INTx but using 
> interrupt line independently. This patch add a "aer"
> interrupt-names for aer interrupt.
> With the interrupt-names "aer", code could probe aer interrupt line 
> for pcie root port, replace the aer interrupt service irq.
> This is intend to fixup the Layerscape platforms which aer interrupt 
> was not MSI/MSI-X/INTx, but using interrupt line independently.
> 
> Signed-off-by: Po Liu <po.liu@nxp.com>

Rob and Shawn had comments here, and I'm not sure they ever got resolved.

> ---
> changes for V4:
> 	- Add comments explain why to add this patch
> 	- Move the binding changes to pci code patch
> 
>  arch/arm/boot/dts/ls1021a.dtsi                 |  6 ++++--
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 
> +++++++++---------  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 
> 16 ++++++++--------
>  3 files changed, 21 insertions(+), 19 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi 
> b/arch/arm/boot/dts/ls1021a.dtsi index 368e219..443e50b 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -634,7 +634,8 @@
>  			reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
>  			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> +			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
> +			interrupt-names = "aer";
>  			fsl,pcie-scfg = <&scfg 0>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
> @@ -657,7 +658,8 @@
>  			reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
>  			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
> +			interrupt-names = "aer";
>  			fsl,pcie-scfg = <&scfg 1>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
> b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> index e669fbd..654071d 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> @@ -527,9 +527,9 @@
>  			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
>  			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 118 0x4>, /* controller interrupt */
> -				     <0 117 0x4>; /* PME interrupt */
> -			interrupt-names = "intr", "pme";
> +			interrupts = <0 117 0x4>, /* PME interrupt */
> +					 <0 118 0x4>; /* aer interrupt */
> +			interrupt-names = "pme", "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> @@ -552,9 +552,9 @@
>  			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
>  			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 128 0x4>,
> -				     <0 127 0x4>;
> -			interrupt-names = "intr", "pme";
> +			interrupts = <0 127 0x4>,
> +					 <0 128 0x4>;
> +			interrupt-names = "pme", "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> @@ -577,9 +577,9 @@
>  			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
>  			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 162 0x4>,
> -				     <0 161 0x4>;
> -			interrupt-names = "intr", "pme";
> +			interrupts = <0 161 0x4>,
> +					 <0 162 0x4>;
> +			interrupt-names = "pme", "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
> b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> index 21023a3..58844e8 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> @@ -583,8 +583,8 @@
>  			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
>  			       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 108 0x4>; /* Level high type */
> -			interrupt-names = "intr";
> +			interrupts = <0 108 0x4>; /* aer interrupt */
> +			interrupt-names = "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> @@ -607,8 +607,8 @@
>  			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
>  			       0x12 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 113 0x4>; /* Level high type */
> -			interrupt-names = "intr";
> +			interrupts = <0 113 0x4>; /* aer interrupt */
> +			interrupt-names = "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> @@ -631,8 +631,8 @@
>  			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
>  			       0x14 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 118 0x4>; /* Level high type */
> -			interrupt-names = "intr";
> +			interrupts = <0 118 0x4>; /* aer interrupt */
> +			interrupt-names = "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> @@ -655,8 +655,8 @@
>  			reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
>  			       0x16 0x00000000 0x0 0x00002000>; /* configuration space */
>  			reg-names = "regs", "config";
> -			interrupts = <0 123 0x4>; /* Level high type */
> -			interrupt-names = "intr";
> +			interrupts = <0 123 0x4>; /* aer interrupt */
> +			interrupt-names = "aer";
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> --
> 2.1.0.27.g96db324
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" 
> in the body of a message to majordomo@vger.kernel.org More majordomo 
> info at  http://vger.kernel.org/majordomo-info.html

[PATCH v5 1/3] arm/dts: add pcie aer interrupt-name property in the dts

[Po Liu]

NXP arm aer interrupt was not MSI/MSI-X/INTx but using interrupt
line independently. This patch add a "aer" interrupt-names for
aer interrupt.

With the interrupt-names "aer", code could probe aer interrupt line
for pcie root port, replace the aer interrupt service irq.

This patch is intend to fixup the Layerscape platforms which aer
interrupt was not MSI/MSI-X/INTx, but using interrupt line independently.

Signed-off-by: Po Liu <po.liu@nxp.com>
---
changes for v5:
	- Seperate arm arm64 dts changes

 arch/arm/boot/dts/ls1021a.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..443e50b 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -634,7 +634,8 @@
 			reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
 			fsl,pcie-scfg = <&scfg 0>;
 			#address-cells = <3>;
 			#size-cells = <2>;
@@ -657,7 +658,8 @@
 			reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
 			fsl,pcie-scfg = <&scfg 1>;
 			#address-cells = <3>;
 			#size-cells = <2>;
-- 
2.1.0.27.g96db324

[PATCH v5 2/3] arm64/dts: add pcie aer interrupt-name property in the dts

[Po Liu]

Some platforms(NXP Layerscape for example) aer interrupt was not
MSI/MSI-X/INTx but using interrupt line independently. This patch
add a "aer" interrupt-names for aer interrupt.

With the interrupt-names "aer", code could probe aer interrupt line
for pcie root port, replace the aer interrupt service irq.

This is intend to fixup the Layerscape platforms which aer interrupt
was not MSI/MSI-X/INTx, but using interrupt line independently.

Signed-off-by: Po Liu <po.liu@nxp.com>
---
changes for v5:
	- Seperate arm and arm64 dts modification into two patches

 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +++++++++---------
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 ++++++++--------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index e669fbd..654071d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -527,9 +527,9 @@
 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 118 0x4>, /* controller interrupt */
-				     <0 117 0x4>; /* PME interrupt */
-			interrupt-names = "intr", "pme";
+			interrupts = <0 117 0x4>, /* PME interrupt */
+					 <0 118 0x4>; /* aer interrupt */
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -552,9 +552,9 @@
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 128 0x4>,
-				     <0 127 0x4>;
-			interrupt-names = "intr", "pme";
+			interrupts = <0 127 0x4>,
+					 <0 128 0x4>;
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -577,9 +577,9 @@
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 162 0x4>,
-				     <0 161 0x4>;
-			interrupt-names = "intr", "pme";
+			interrupts = <0 161 0x4>,
+					 <0 162 0x4>;
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 21023a3..58844e8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -583,8 +583,8 @@
 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 			       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 108 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 108 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -607,8 +607,8 @@
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 			       0x12 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 113 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 113 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -631,8 +631,8 @@
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 			       0x14 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 118 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 118 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -655,8 +655,8 @@
 			reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
 			       0x16 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 123 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 123 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-- 
2.1.0.27.g96db324

[PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Po Liu]

On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.

Signed-off-by: Po Liu <po.liu@nxp.com>
---
changes for v5:
	- Add clear 'aer' interrup-names description

 .../devicetree/bindings/pci/layerscape-pci.txt     | 11 +++++---
 drivers/pci/pcie/portdrv_core.c                    | 31 +++++++++++++++++++---
 2 files changed, 35 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 41e9f55..101d0a7 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -18,8 +18,10 @@ Required properties:
 - reg: base addresses and lengths of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
-- interrupt-names: Must include the following entries:
-  "intr": The interrupt that is asserted for controller interrupts
+- interrupt-names: It may be include the following entries:
+  "aer": The interrupt that is asserted for aer interrupt
+  "pme": The interrupt that is asserted for pme interrupt
+  ......
 - fsl,pcie-scfg: Must include two entries.
   The first entry must be a link to the SCFG device node
   The second entry must be '0' or '1' based on physical PCIe controller index.
@@ -35,8 +37,9 @@ Example:
 		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 		reg-names = "regs", "config";
-		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-		interrupt-names = "intr";
+		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */
+			<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
+		interrupt-names = "aer", "pme";
 		fsl,pcie-scfg = <&scfg 0>;
 		#address-cells = <3>;
 		#size-cells = <2>;
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index e9270b4..7c4943d 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -16,6 +16,7 @@
 #include <linux/slab.h>
 #include <linux/pcieport_if.h>
 #include <linux/aer.h>
+#include <linux/of_irq.h>
 
 #include "../pci.h"
 #include "portdrv.h"
@@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
 static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
 {
 	int i, irq = -1;
+	int ret;
+	struct device_node *np = NULL;
+
+	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
+		irqs[i] = 0;
+
+	if (dev->bus->dev.of_node)
+		np = dev->bus->dev.of_node;
+
+	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+	 * request irq for aer
+	 */
+	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
+			(mask & PCIE_PORT_SERVICE_PME)) {
+		ret = of_irq_get_byname(np, "aer");
+		if (ret > 0) {
+			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
+			if (dev->irq)
+				irq = dev->irq;
+			goto no_msi;
+		}
+	}
 
 	/*
 	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
@@ -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
 		irq = dev->irq;
 
  no_msi:
-	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
-		irqs[i] = irq;
+	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
+		if (!irqs[i])
+			irqs[i] = irq;
+	}
 	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
 
-	if (irq < 0)
+	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
 		return -ENODEV;
 	return 0;
 }
-- 
2.1.0.27.g96db324

Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Shawn Guo]

On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
> On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> maybe there is interrupt line for aer pme etc. Search the interrupt
> number in the fdt file. Then fixup the dev->irq with it.
> 
> Signed-off-by: Po Liu <po.liu-3arQi8VN3Tc@public.gmane.org>

Will the new kernel work with existing/old DTB?  I'm trying to
understand the dependency between driver and DTS changes.

Shawn

> ---
> changes for v5:
> 	- Add clear 'aer' interrup-names description
> 
>  .../devicetree/bindings/pci/layerscape-pci.txt     | 11 +++++---
>  drivers/pci/pcie/portdrv_core.c                    | 31 +++++++++++++++++++---
>  2 files changed, 35 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 41e9f55..101d0a7 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -18,8 +18,10 @@ Required properties:
>  - reg: base addresses and lengths of the PCIe controller
>  - interrupts: A list of interrupt outputs of the controller. Must contain an
>    entry for each entry in the interrupt-names property.
> -- interrupt-names: Must include the following entries:
> -  "intr": The interrupt that is asserted for controller interrupts
> +- interrupt-names: It may be include the following entries:
> +  "aer": The interrupt that is asserted for aer interrupt
> +  "pme": The interrupt that is asserted for pme interrupt
> +  ......
>  - fsl,pcie-scfg: Must include two entries.
>    The first entry must be a link to the SCFG device node
>    The second entry must be '0' or '1' based on physical PCIe controller index.
> @@ -35,8 +37,9 @@ Example:
>  		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
>  		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
>  		reg-names = "regs", "config";
> -		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> -		interrupt-names = "intr";
> +		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */
> +			<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
> +		interrupt-names = "aer", "pme";
>  		fsl,pcie-scfg = <&scfg 0>;
>  		#address-cells = <3>;
>  		#size-cells = <2>;
> diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
> index e9270b4..7c4943d 100644
> --- a/drivers/pci/pcie/portdrv_core.c
> +++ b/drivers/pci/pcie/portdrv_core.c
> @@ -16,6 +16,7 @@
>  #include <linux/slab.h>
>  #include <linux/pcieport_if.h>
>  #include <linux/aer.h>
> +#include <linux/of_irq.h>
>  
>  #include "../pci.h"
>  #include "portdrv.h"
> @@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
>  static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
>  {
>  	int i, irq = -1;
> +	int ret;
> +	struct device_node *np = NULL;
> +
> +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> +		irqs[i] = 0;
> +
> +	if (dev->bus->dev.of_node)
> +		np = dev->bus->dev.of_node;
> +
> +	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> +	 * request irq for aer
> +	 */
> +	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
> +			(mask & PCIE_PORT_SERVICE_PME)) {
> +		ret = of_irq_get_byname(np, "aer");
> +		if (ret > 0) {
> +			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
> +			if (dev->irq)
> +				irq = dev->irq;
> +			goto no_msi;
> +		}
> +	}
>  
>  	/*
>  	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
> @@ -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
>  		irq = dev->irq;
>  
>   no_msi:
> -	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> -		irqs[i] = irq;
> +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
> +		if (!irqs[i])
> +			irqs[i] = irq;
> +	}
>  	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
>  
> -	if (irq < 0)
> +	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
>  		return -ENODEV;
>  	return 0;
>  }
> -- 
> 2.1.0.27.g96db324
> 
> 
> _______________________________________________
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> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Po Liu]

Hi Shawn,


>  -----Original Message-----
>  From: Shawn Guo [mailto:shawnguo@kernel.org]
>  Sent: Sunday, September 18, 2016 8:52 AM
>  To: Po Liu
>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang; Arnd
>  Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali
>  Karicheri; Bjorn Helgaas; Mingkai Hu
>  Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none
>  MSI/MSI-X/INTx mode
>  
>  On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
>  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
>  > maybe there is interrupt line for aer pme etc. Search the interrupt
>  > number in the fdt file. Then fixup the dev->irq with it.
>  >
>  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  
>  Will the new kernel work with existing/old DTB?  I'm trying to
>  understand the dependency between driver and DTS changes.

Yes, We've never use name 'intr' before. So we remove it is ok. 
'aer' is a dts name for researching it's true interrupt number by kernel. This patch is first time to use name 'aer'. So it must be compatible with existing/old DTB.

>  
>  Shawn
>  
>  > ---
>  > changes for v5:
>  > 	- Add clear 'aer' interrup-names description
>  >
>  >  .../devicetree/bindings/pci/layerscape-pci.txt     | 11 +++++---
>  >  drivers/pci/pcie/portdrv_core.c                    | 31
>  +++++++++++++++++++---
>  >  2 files changed, 35 insertions(+), 7 deletions(-)
>  >
>  > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > index 41e9f55..101d0a7 100644
>  > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > @@ -18,8 +18,10 @@ Required properties:
>  >  - reg: base addresses and lengths of the PCIe controller
>  >  - interrupts: A list of interrupt outputs of the controller. Must
>  contain an
>  >    entry for each entry in the interrupt-names property.
>  > -- interrupt-names: Must include the following entries:
>  > -  "intr": The interrupt that is asserted for controller interrupts
>  > +- interrupt-names: It may be include the following entries:
>  > +  "aer": The interrupt that is asserted for aer interrupt
>  > +  "pme": The interrupt that is asserted for pme interrupt
>  > +  ......
>  >  - fsl,pcie-scfg: Must include two entries.
>  >    The first entry must be a link to the SCFG device node
>  >    The second entry must be '0' or '1' based on physical PCIe
>  controller index.
>  > @@ -35,8 +37,9 @@ Example:
>  >  		reg = <0x00 0x03400000 0x0 0x00010000   /* controller
>  registers */
>  >  		       0x40 0x00000000 0x0 0x00002000>; /* configuration
>  space */
>  >  		reg-names = "regs", "config";
>  > -		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /*
>  controller interrupt */
>  > -		interrupt-names = "intr";
>  > +		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer
>  interrupt */
>  > +			<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
>  > +		interrupt-names = "aer", "pme";
>  >  		fsl,pcie-scfg = <&scfg 0>;
>  >  		#address-cells = <3>;
>  >  		#size-cells = <2>;
>  > diff --git a/drivers/pci/pcie/portdrv_core.c
>  > b/drivers/pci/pcie/portdrv_core.c index e9270b4..7c4943d 100644
>  > --- a/drivers/pci/pcie/portdrv_core.c
>  > +++ b/drivers/pci/pcie/portdrv_core.c
>  > @@ -16,6 +16,7 @@
>  >  #include <linux/slab.h>
>  >  #include <linux/pcieport_if.h>
>  >  #include <linux/aer.h>
>  > +#include <linux/of_irq.h>
>  >
>  >  #include "../pci.h"
>  >  #include "portdrv.h"
>  > @@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev
>  > *dev, int *vectors, int mask)  static int init_service_irqs(struct
>  > pci_dev *dev, int *irqs, int mask)  {
>  >  	int i, irq = -1;
>  > +	int ret;
>  > +	struct device_node *np = NULL;
>  > +
>  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
>  > +		irqs[i] = 0;
>  > +
>  > +	if (dev->bus->dev.of_node)
>  > +		np = dev->bus->dev.of_node;
>  > +
>  > +	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
>  > +	 * request irq for aer
>  > +	 */
>  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
>  > +			(mask & PCIE_PORT_SERVICE_PME)) {
>  > +		ret = of_irq_get_byname(np, "aer");
>  > +		if (ret > 0) {
>  > +			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
>  > +			if (dev->irq)
>  > +				irq = dev->irq;
>  > +			goto no_msi;
>  > +		}
>  > +	}
>  >
>  >  	/*
>  >  	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
>  @@
>  > -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev,
>  int *irqs, int mask)
>  >  		irq = dev->irq;
>  >
>  >   no_msi:
>  > -	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
>  > -		irqs[i] = irq;
>  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
>  > +		if (!irqs[i])
>  > +			irqs[i] = irq;
>  > +	}
>  >  	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
>  >
>  > -	if (irq < 0)
>  > +	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
>  >  		return -ENODEV;
>  >  	return 0;
>  >  }
>  > --
>  > 2.1.0.27.g96db324
>  >
>  >
>  > _______________________________________________
>  > linux-arm-kernel mailing list
>  > linux-arm-kernel@lists.infradead.org
>  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Shawn Guo]

On Sun, Sep 18, 2016 at 03:37:27AM +0000, Po Liu wrote:
> Hi Shawn,
> 
> 
> >  -----Original Message-----
> >  From: Shawn Guo [mailto:shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> >  Sent: Sunday, September 18, 2016 8:52 AM
> >  To: Po Liu
> >  Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org;
> >  linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Roy Zang; Arnd
> >  Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali
> >  Karicheri; Bjorn Helgaas; Mingkai Hu
> >  Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none
> >  MSI/MSI-X/INTx mode
> >  
> >  On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
> >  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> >  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> >  > maybe there is interrupt line for aer pme etc. Search the interrupt
> >  > number in the fdt file. Then fixup the dev->irq with it.
> >  >
> >  > Signed-off-by: Po Liu <po.liu-3arQi8VN3Tc@public.gmane.org>
> >  
> >  Will the new kernel work with existing/old DTB?  I'm trying to
> >  understand the dependency between driver and DTS changes.
> 
> Yes, We've never use name 'intr' before. So we remove it is ok. 
> 'aer' is a dts name for researching it's true interrupt number by kernel. This patch is first time to use name 'aer'. So it must be compatible with existing/old DTB.

Does that mean driver and DTS changes can go through separate trees,
i.e. PCI and arm-soc, without introducing regressions on either tree?
Or does the patch series needs to go in as a whole?

Shawn
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Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Bjorn Helgaas]

On Mon, Aug 22, 2016 at 10:09:18AM +0000, Po Liu wrote:
> Hi Bjorn,
> 
> Sorry for late reply.
> 
> I checked the updated kernel with Dongdong mentioned ACPI patch which was truly affected my quirk patch uploaded. So I suppose the quirk patch is not qualify to fix the bug.

I don't understand what you're saying here.  

The quirk worked on your machine.  It apparently didn't work on
Dongdong's machine because of_irq_parse_and_map_pci() is run after the
quirk in this path:

  pci_device_probe
    pcibios_alloc_irq                 # arm64
      dev->irq = of_irq_parse_and_map_pci

and of_irq_parse_and_map_pci() returned zero, probably because
of_irq_parse_pci() failed.  My guess is that the reason it works on
your machine but not Dongdong's is that your DTs are different such
that of_irq_parse_pci() works for you but not for Dongdong.

I think the idea of of_irq_parse_and_map_pci() is to set up a device's
INTx line.  But that doesn't quite apply here because your device
doesn't actually *use* INTx.  So I don't know why of_irq_parse_pci()
works for you.  Maybe that's a symptom of a problem in your DT.

Or maybe you're saying that the quirk *didn't* work on your machine
when you tested it in a kernel that included d8ed75d59332 ("ARM64:
PCI: ACPI support for legacy IRQs parsing and consolidation with DT
code").   But that doesn't make sense either, because prior to
d8ed75d59332, we *always* set

  dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);

and after the patch we only do it if "acpi_disabled".  I guess I just
don't understand what you're saying.

> I were keep thinking what your "explicitly checking for a root port device" meaning. Do you mean I should upload again the first version patch which fix it in the portdrv_core.c ? I would upload again if yes. 

No, I did not mean you should go back to the first version of the
patch.  If we *can* do this in a quirk, I think that would be much
better than doing it in the PCIe port driver.  I meant that Dongdong's
suggestion of adding this:

  if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
    return;

to your quirk made sense to me.

> >  -----Original Message-----
> >  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
> >  Sent: Saturday, July 30, 2016 6:42 AM
> >  To: Po Liu
> >  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> >  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang; Arnd
> >  Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Murali
> >  Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
> >  Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
> >  
> >  On Tue, Jun 14, 2016 at 04:24:05PM +0800, Po Liu wrote:
> >  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> >  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> >  > maybe there is interrupt line for aer pme etc. Search the interrupt
> >  > number in the fdt file. Then fixup the dev->irq with it.
> >  >
> >  > Signed-off-by: Po Liu <po.liu@nxp.com>
> >  
> >  I'm not sure where we're at with this.  Dongdong had some issue
> >  (possibly with a version of the quirk on a different platform?), and I
> >  think the suggestion of explicitly checking for a root port device was a
> >  good one.
> >  
> >  So please update and repost this for next cycle.
> >  
> >  > ---
> >  > changes for V3:
> >  > 	- Move to quirk;
> >  > 	- Only correct the irq in RC mode;
> >  >
> >  >  drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++
> >  >  1 file changed, 29 insertions(+)
> >  >
> >  > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> >  > ee72ebe..8b39cce 100644
> >  > --- a/drivers/pci/quirks.c
> >  > +++ b/drivers/pci/quirks.c
> >  > @@ -25,6 +25,7 @@
> >  >  #include <linux/sched.h>
> >  >  #include <linux/ktime.h>
> >  >  #include <linux/mm.h>
> >  > +#include <linux/of_irq.h>
> >  >  #include <asm/dma.h>	/* isa_dma_bridge_buggy */
> >  >  #include "pci.h"
> >  >
> >  > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
> >  pci_dev *pdev)
> >  >  	}
> >  >  }
> >  >  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
> >  > quirk_intel_qat_vf_cap);
> >  > +
> >  > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> >  > + * but use standalone irq. Read the device tree for the aer
> >  > + * interrupt number.
> >  > + */
> >  > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> >  > +	int ret;
> >  > +	u8 header_type;
> >  > +	struct device_node *np = NULL;
> >  > +
> >  > +	/* Only for the RC mode device */
> >  > +	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
> >  > +	if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> >  > +		return;
> >  > +
> >  > +	if (dev->bus->dev.of_node)
> >  > +		np = dev->bus->dev.of_node;
> >  > +
> >  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> >  > +		ret = of_irq_get_byname(np, "aer");
> >  > +		if (ret > 0) {
> >  > +			dev->no_msi = 1;
> >  > +			dev->irq = ret;
> >  > +		}
> >  > +	}
> >  > +}
> >  > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
> >  > +quirk_aer_interrupt);
> >  > --
> >  > 2.1.0.27.g96db324
> >  >
> >  >
> >  > _______________________________________________
> >  > linux-arm-kernel mailing list
> >  > linux-arm-kernel@lists.infradead.org
> >  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

RE: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Po Liu]

Hi Bjorn,

>  -----Original Message-----
>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>  Sent: Wednesday, September 21, 2016 4:47 AM
>  To: Po Liu
>  Cc: Roy Zang; Arnd Bergmann; devicetree@vger.kernel.org; Marc Zyngier;
>  linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org; Stuart Yoder;
>  M.H. Lian; Murali Karicheri; Mingkai Hu; Bjorn Helgaas; Leo Li; Shawn
>  Guo; linux-arm-kernel@lists.infradead.org
>  Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>  
>  On Mon, Aug 22, 2016 at 10:09:18AM +0000, Po Liu wrote:
>  > Hi Bjorn,
>  >
>  > Sorry for late reply.
>  >
>  > I checked the updated kernel with Dongdong mentioned ACPI patch which
>  was truly affected my quirk patch uploaded. So I suppose the quirk patch
>  is not qualify to fix the bug.
>  
>  I don't understand what you're saying here.
>  
>  The quirk worked on your machine.  It apparently didn't work on
>  Dongdong's machine because of_irq_parse_and_map_pci() is run after the
>  quirk in this path:
>  
>    pci_device_probe
>      pcibios_alloc_irq                 # arm64
>        dev->irq = of_irq_parse_and_map_pci
>  
>  and of_irq_parse_and_map_pci() returned zero, probably because
>  of_irq_parse_pci() failed.  My guess is that the reason it works on your
>  machine but not Dongdong's is that your DTs are different such that
>  of_irq_parse_pci() works for you but not for Dongdong.
>  
>  I think the idea of of_irq_parse_and_map_pci() is to set up a device's
>  INTx line.  But that doesn't quite apply here because your device
>  doesn't actually *use* INTx.  So I don't know why of_irq_parse_pci()
>  works for you.  Maybe that's a symptom of a problem in your DT.
>  
>  Or maybe you're saying that the quirk *didn't* work on your machine when
>  you tested it in a kernel that included d8ed75d59332 ("ARM64:
>  PCI: ACPI support for legacy IRQs parsing and consolidation with DT
>  code"). 

Yes, this point is what I mean. After this patch my quirk patch would not work. 
Since I discussed with Dongdong, the patches d8ed75d59332 ACPI related were not be merged yet.


>  But that doesn't make sense either, because prior to
>  d8ed75d59332, we *always* set
>  
>    dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
>  
>  and after the patch we only do it if "acpi_disabled".  I guess I just
>  don't understand what you're saying.

Before the patch merged. pcibios_add_device()(which run the ->irq = of_irq_parse_and_map_pci(dev, 0, 0);) was loaded before the pci_fixup_device(pci_fixup_final). 
But after the patch d8ed75d59332("ARM64: PCI: ACPI support for legacy IRQs parsing and consolidation with DT code") merged, the pci_fixup_device(pci_fixup_final) run BEFORE the pcibios_alloc_irq()(which run the ->irq = of_irq_parse_and_map_pci(dev, 0, 0);). So the dev->irq were overwhelm by the pcibios_alloc_irq().

When I test, the acpi_disabled is '1' although my kernel config default is CONFIG_ACPI=y. And no setting in the uboot with apci=xxx. But this is another issue, I didn't deep to check it. 

>  
>  > I were keep thinking what your "explicitly checking for a root port
>  device" meaning. Do you mean I should upload again the first version
>  patch which fix it in the portdrv_core.c ? I would upload again if yes.
>  
>  No, I did not mean you should go back to the first version of the patch.
>  If we *can* do this in a quirk, I think that would be much better than
>  doing it in the PCIe port driver.  I meant that Dongdong's suggestion of
>  adding this:
>  
>    if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
>      return;
>  
>  to your quirk made sense to me.

If the quirk patch could make workaround. It should be the better way.

Po Liu

>  
>  > >  -----Original Message-----
>  > >  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>  > >  Sent: Saturday, July 30, 2016 6:42 AM
>  > >  To: Po Liu
>  > >  Cc: linux-pci@vger.kernel.org;
>  > > linux-arm-kernel@lists.infradead.org;
>  > >  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang;
>  > > Arnd  Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan
>  > > Lian; Murali  Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
>  > >  Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>  > >
>  > >  On Tue, Jun 14, 2016 at 04:24:05PM +0800, Po Liu wrote:
>  > >  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC
>  mode.
>  > >  > When chip support the aer interrupt with none MSI/MSI-X/INTx
>  > > mode,  > maybe there is interrupt line for aer pme etc. Search the
>  > > interrupt  > number in the fdt file. Then fixup the dev->irq with it.
>  > >  >
>  > >  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  > >
>  > >  I'm not sure where we're at with this.  Dongdong had some issue
>  > > (possibly with a version of the quirk on a different platform?), and
>  > > I  think the suggestion of explicitly checking for a root port
>  > > device was a  good one.
>  > >
>  > >  So please update and repost this for next cycle.
>  > >
>  > >  > ---
>  > >  > changes for V3:
>  > >  > 	- Move to quirk;
>  > >  > 	- Only correct the irq in RC mode;
>  > >  >
>  > >  >  drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++  >  1
>  > > file changed, 29 insertions(+)  >  > diff --git
>  > > a/drivers/pci/quirks.c b/drivers/pci/quirks.c index  >
>  > > ee72ebe..8b39cce 100644  > --- a/drivers/pci/quirks.c  > +++
>  > > b/drivers/pci/quirks.c  > @@ -25,6 +25,7 @@  >  #include
>  > > <linux/sched.h>  >  #include <linux/ktime.h>  >  #include
>  > > <linux/mm.h>  > +#include <linux/of_irq.h>
>  > >  >  #include <asm/dma.h>	/* isa_dma_bridge_buggy */
>  > >  >  #include "pci.h"
>  > >  >
>  > >  > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
>  > > pci_dev *pdev)
>  > >  >  	}
>  > >  >  }
>  > >  >  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,  >
>  > > quirk_intel_qat_vf_cap);  > +  > +/* If root port doesn't support
>  > > MSI/MSI-X/INTx in RC mode,  > + * but use standalone irq. Read the
>  > > device tree for the aer  > + * interrupt number.
>  > >  > + */
>  > >  > +static void quirk_aer_interrupt(struct pci_dev *dev) {
>  > >  > +	int ret;
>  > >  > +	u8 header_type;
>  > >  > +	struct device_node *np = NULL;
>  > >  > +
>  > >  > +	/* Only for the RC mode device */
>  > >  > +	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
>  > >  > +	if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
>  > >  > +		return;
>  > >  > +
>  > >  > +	if (dev->bus->dev.of_node)
>  > >  > +		np = dev->bus->dev.of_node;
>  > >  > +
>  > >  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
>  > >  > +		ret = of_irq_get_byname(np, "aer");
>  > >  > +		if (ret > 0) {
>  > >  > +			dev->no_msi = 1;
>  > >  > +			dev->irq = ret;
>  > >  > +		}
>  > >  > +	}
>  > >  > +}
>  > >  > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,  >
>  > > +quirk_aer_interrupt);  > --  > 2.1.0.27.g96db324  >  >  >
>  > > _______________________________________________
>  > >  > linux-arm-kernel mailing list
>  > >  > linux-arm-kernel@lists.infradead.org
>  > >  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>  > _______________________________________________
>  > linux-arm-kernel mailing list
>  > linux-arm-kernel@lists.infradead.org
>  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Po Liu]

Hi Shawn,


>  -----Original Message-----
>  From: Shawn Guo [mailto:shawnguo@kernel.org]
>  Sent: Tuesday, September 20, 2016 8:39 PM
>  To: Po Liu
>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang; Arnd
>  Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali
>  Karicheri; Bjorn Helgaas; Mingkai Hu
>  Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none
>  MSI/MSI-X/INTx mode
>  
>  On Sun, Sep 18, 2016 at 03:37:27AM +0000, Po Liu wrote:
>  > Hi Shawn,
>  >
>  >
>  > >  -----Original Message-----
>  > >  From: Shawn Guo [mailto:shawnguo@kernel.org]
>  > >  Sent: Sunday, September 18, 2016 8:52 AM
>  > >  To: Po Liu
>  > >  Cc: linux-pci@vger.kernel.org;
>  > > linux-arm-kernel@lists.infradead.org;
>  > >  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang;
>  > > Arnd  Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian;
>  > > Murali  Karicheri; Bjorn Helgaas; Mingkai Hu
>  > >  Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with
>  > > none  MSI/MSI-X/INTx mode
>  > >
>  > >  On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
>  > >  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC
>  mode.
>  > >  > When chip support the aer interrupt with none MSI/MSI-X/INTx
>  > > mode,  > maybe there is interrupt line for aer pme etc. Search the
>  > > interrupt  > number in the fdt file. Then fixup the dev->irq with it.
>  > >  >
>  > >  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  > >
>  > >  Will the new kernel work with existing/old DTB?  I'm trying to
>  > > understand the dependency between driver and DTS changes.
>  >
>  > Yes, We've never use name 'intr' before. So we remove it is ok.
>  > 'aer' is a dts name for researching it's true interrupt number by
>  kernel. This patch is first time to use name 'aer'. So it must be
>  compatible with existing/old DTB.
>  
>  Does that mean driver and DTS changes can go through separate trees, i.e.
>  PCI and arm-soc, without introducing regressions on either tree?
>  Or does the patch series needs to go in as a whole?

Should be as a whole. The driver base on the dts. Or else, the driver would not found the 'aer' point.
Thanks!

Po

>  
>  Shawn

Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Bjorn Helgaas]

On Wed, Sep 21, 2016 at 06:51:55AM +0000, Po Liu wrote:
> Hi Bjorn,
> 
> >  -----Original Message-----
> >  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
> >  Sent: Wednesday, September 21, 2016 4:47 AM
> >  To: Po Liu
> >  Cc: Roy Zang; Arnd Bergmann; devicetree@vger.kernel.org; Marc Zyngier;
> >  linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org; Stuart Yoder;
> >  M.H. Lian; Murali Karicheri; Mingkai Hu; Bjorn Helgaas; Leo Li; Shawn
> >  Guo; linux-arm-kernel@lists.infradead.org
> >  Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
> >  
> >  On Mon, Aug 22, 2016 at 10:09:18AM +0000, Po Liu wrote:
> >  > Hi Bjorn,
> >  >
> >  > Sorry for late reply.
> >  >
> >  > I checked the updated kernel with Dongdong mentioned ACPI patch which
> >  was truly affected my quirk patch uploaded. So I suppose the quirk patch
> >  is not qualify to fix the bug.
> >  
> >  I don't understand what you're saying here.
> >  
> >  The quirk worked on your machine.  It apparently didn't work on
> >  Dongdong's machine because of_irq_parse_and_map_pci() is run after the
> >  quirk in this path:
> >  
> >    pci_device_probe
> >      pcibios_alloc_irq                 # arm64
> >        dev->irq = of_irq_parse_and_map_pci
> >  
> >  and of_irq_parse_and_map_pci() returned zero, probably because
> >  of_irq_parse_pci() failed.  My guess is that the reason it works on your
> >  machine but not Dongdong's is that your DTs are different such that
> >  of_irq_parse_pci() works for you but not for Dongdong.
> >  
> >  I think the idea of of_irq_parse_and_map_pci() is to set up a device's
> >  INTx line.  But that doesn't quite apply here because your device
> >  doesn't actually *use* INTx.  So I don't know why of_irq_parse_pci()
> >  works for you.  Maybe that's a symptom of a problem in your DT.
> >  
> >  Or maybe you're saying that the quirk *didn't* work on your machine when
> >  you tested it in a kernel that included d8ed75d59332 ("ARM64:
> >  PCI: ACPI support for legacy IRQs parsing and consolidation with DT
> >  code"). 
> 
> Yes, this point is what I mean. After this patch my quirk patch would not work. 
> Since I discussed with Dongdong, the patches d8ed75d59332 ACPI related were not be merged yet.
> 
> 
> >  But that doesn't make sense either, because prior to
> >  d8ed75d59332, we *always* set
> >  
> >    dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> >  
> >  and after the patch we only do it if "acpi_disabled".  I guess I just
> >  don't understand what you're saying.
> 
> Before the patch merged. pcibios_add_device()(which run the ->irq =
> of_irq_parse_and_map_pci(dev, 0, 0);) was loaded before the
> pci_fixup_device(pci_fixup_final).  But after the patch
> d8ed75d59332("ARM64: PCI: ACPI support for legacy IRQs parsing and
> consolidation with DT code") merged, the
> pci_fixup_device(pci_fixup_final) run BEFORE the
> pcibios_alloc_irq()(which run the ->irq =
> of_irq_parse_and_map_pci(dev, 0, 0);). So the dev->irq were
> overwhelm by the pcibios_alloc_irq().

OK.  Prior to d8ed75d59332, arm64 overrode the default empty
pcibios_add_device() implementation, and called
of_irq_parse_and_map_pci() there.  d8ed75d59332 changed that function
to pcibios_alloc_irq(), which is called later, in the driver probe
path.

> When I test, the acpi_disabled is '1' although my kernel config
> default is CONFIG_ACPI=y. And no setting in the uboot with apci=xxx.
> But this is another issue, I didn't deep to check it. 

Likely your platform just doesn't have ACPI or something's wrong in
the initial ACPI setup.

> >  > I were keep thinking what your "explicitly checking for a root port
> >  device" meaning. Do you mean I should upload again the first version
> >  patch which fix it in the portdrv_core.c ? I would upload again if yes.
> >  
> >  No, I did not mean you should go back to the first version of the patch.
> >  If we *can* do this in a quirk, I think that would be much better than
> >  doing it in the PCIe port driver.  I meant that Dongdong's suggestion of
> >  adding this:
> >  
> >    if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
> >      return;
> >  
> >  to your quirk made sense to me.
> 
> If the quirk patch could make workaround. It should be the better way.

It doesn't sound like a quirk is going to work because all the quirks
run too early.  I'll respond to the patch itself with more ideas.

> >  > >  -----Original Message-----
> >  > >  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
> >  > >  Sent: Saturday, July 30, 2016 6:42 AM
> >  > >  To: Po Liu
> >  > >  Cc: linux-pci@vger.kernel.org;
> >  > > linux-arm-kernel@lists.infradead.org;
> >  > >  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang;
> >  > > Arnd  Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan
> >  > > Lian; Murali  Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
> >  > >  Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
> >  > >
> >  > >  On Tue, Jun 14, 2016 at 04:24:05PM +0800, Po Liu wrote:
> >  > >  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC
> >  mode.
> >  > >  > When chip support the aer interrupt with none MSI/MSI-X/INTx
> >  > > mode,  > maybe there is interrupt line for aer pme etc. Search the
> >  > > interrupt  > number in the fdt file. Then fixup the dev->irq with it.
> >  > >  >
> >  > >  > Signed-off-by: Po Liu <po.liu@nxp.com>
> >  > >
> >  > >  I'm not sure where we're at with this.  Dongdong had some issue
> >  > > (possibly with a version of the quirk on a different platform?), and
> >  > > I  think the suggestion of explicitly checking for a root port
> >  > > device was a  good one.
> >  > >
> >  > >  So please update and repost this for next cycle.
> >  > >
> >  > >  > ---
> >  > >  > changes for V3:
> >  > >  > 	- Move to quirk;
> >  > >  > 	- Only correct the irq in RC mode;
> >  > >  >
> >  > >  >  drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++  >  1
> >  > > file changed, 29 insertions(+)  >  > diff --git
> >  > > a/drivers/pci/quirks.c b/drivers/pci/quirks.c index  >
> >  > > ee72ebe..8b39cce 100644  > --- a/drivers/pci/quirks.c  > +++
> >  > > b/drivers/pci/quirks.c  > @@ -25,6 +25,7 @@  >  #include
> >  > > <linux/sched.h>  >  #include <linux/ktime.h>  >  #include
> >  > > <linux/mm.h>  > +#include <linux/of_irq.h>
> >  > >  >  #include <asm/dma.h>	/* isa_dma_bridge_buggy */
> >  > >  >  #include "pci.h"
> >  > >  >
> >  > >  > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
> >  > > pci_dev *pdev)
> >  > >  >  	}
> >  > >  >  }
> >  > >  >  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,  >
> >  > > quirk_intel_qat_vf_cap);  > +  > +/* If root port doesn't support
> >  > > MSI/MSI-X/INTx in RC mode,  > + * but use standalone irq. Read the
> >  > > device tree for the aer  > + * interrupt number.
> >  > >  > + */
> >  > >  > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> >  > >  > +	int ret;
> >  > >  > +	u8 header_type;
> >  > >  > +	struct device_node *np = NULL;
> >  > >  > +
> >  > >  > +	/* Only for the RC mode device */
> >  > >  > +	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
> >  > >  > +	if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> >  > >  > +		return;
> >  > >  > +
> >  > >  > +	if (dev->bus->dev.of_node)
> >  > >  > +		np = dev->bus->dev.of_node;
> >  > >  > +
> >  > >  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> >  > >  > +		ret = of_irq_get_byname(np, "aer");
> >  > >  > +		if (ret > 0) {
> >  > >  > +			dev->no_msi = 1;
> >  > >  > +			dev->irq = ret;
> >  > >  > +		}
> >  > >  > +	}
> >  > >  > +}
> >  > >  > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,  >
> >  > > +quirk_aer_interrupt);  > --  > 2.1.0.27.g96db324  >  >  >
> >  > > _______________________________________________
> >  > >  > linux-arm-kernel mailing list
> >  > >  > linux-arm-kernel@lists.infradead.org
> >  > >  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >  > _______________________________________________
> >  > linux-arm-kernel mailing list
> >  > linux-arm-kernel@lists.infradead.org
> >  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Bjorn Helgaas]

On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
> On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> maybe there is interrupt line for aer pme etc. Search the interrupt
> number in the fdt file. Then fixup the dev->irq with it.
> 
> Signed-off-by: Po Liu <po.liu-3arQi8VN3Tc@public.gmane.org>
> ---
> changes for v5:
> 	- Add clear 'aer' interrup-names description
> 
>  .../devicetree/bindings/pci/layerscape-pci.txt     | 11 +++++---
>  drivers/pci/pcie/portdrv_core.c                    | 31 +++++++++++++++++++---
>  2 files changed, 35 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 41e9f55..101d0a7 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -18,8 +18,10 @@ Required properties:
>  - reg: base addresses and lengths of the PCIe controller
>  - interrupts: A list of interrupt outputs of the controller. Must contain an
>    entry for each entry in the interrupt-names property.
> -- interrupt-names: Must include the following entries:
> -  "intr": The interrupt that is asserted for controller interrupts
> +- interrupt-names: It may be include the following entries:
> +  "aer": The interrupt that is asserted for aer interrupt
> +  "pme": The interrupt that is asserted for pme interrupt
> +  ......
>  - fsl,pcie-scfg: Must include two entries.
>    The first entry must be a link to the SCFG device node
>    The second entry must be '0' or '1' based on physical PCIe controller index.
> @@ -35,8 +37,9 @@ Example:
>  		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
>  		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
>  		reg-names = "regs", "config";
> -		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> -		interrupt-names = "intr";
> +		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */
> +			<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
> +		interrupt-names = "aer", "pme";
>  		fsl,pcie-scfg = <&scfg 0>;
>  		#address-cells = <3>;
>  		#size-cells = <2>;
> diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
> index e9270b4..7c4943d 100644
> --- a/drivers/pci/pcie/portdrv_core.c
> +++ b/drivers/pci/pcie/portdrv_core.c
> @@ -16,6 +16,7 @@
>  #include <linux/slab.h>
>  #include <linux/pcieport_if.h>
>  #include <linux/aer.h>
> +#include <linux/of_irq.h>
>  
>  #include "../pci.h"
>  #include "portdrv.h"
> @@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
>  static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
>  {
>  	int i, irq = -1;
> +	int ret;
> +	struct device_node *np = NULL;
> +
> +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> +		irqs[i] = 0;
> +
> +	if (dev->bus->dev.of_node)
> +		np = dev->bus->dev.of_node;
> +
> +	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> +	 * request irq for aer
> +	 */
> +	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
> +			(mask & PCIE_PORT_SERVICE_PME)) {
> +		ret = of_irq_get_byname(np, "aer");
> +		if (ret > 0) {
> +			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
> +			if (dev->irq)
> +				irq = dev->irq;
> +			goto no_msi;
> +		}
> +	}

We definitely need to solve this somehow.  But this approach doesn't
feel quite right because it's hard to map this code back to anything
in the spec, and it uses a completely platform-dependent name
("interrupt-names aer") in code that is supposedly generic.

What if we added some sort of hook that would return the IRQ?  Maybe a
pcibios_*() hook right now, with the idea of making it a
pci_host_bridge function pointer someday?

I know the body of the hook would look a lot like what you have here,
but at least it would be more obvious that it's platform-specific
code.

I think your platform supports PME interrupts as well as AER, and
they're different IRQs.  So you'd probably have to do something
similar to the pcie_port_enable_msix() interface, so you can fill in
both IRQs.

>  	/*
>  	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
> @@ -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
>  		irq = dev->irq;
>  
>   no_msi:
> -	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> -		irqs[i] = irq;
> +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
> +		if (!irqs[i])
> +			irqs[i] = irq;
> +	}
>  	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
>  
> -	if (irq < 0)
> +	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
>  		return -ENODEV;
>  	return 0;
>  }
> -- 
> 2.1.0.27.g96db324
> 
> 
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RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Po Liu]

Hi Bjorn,

>  -----Original Message-----
>  From: Bjorn Helgaas [mailto:helgaas@kernel.org]
>  Sent: Thursday, September 22, 2016 6:38 AM
>  To: Po Liu
>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang; Arnd
>  Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali
>  Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
>  Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none
>  MSI/MSI-X/INTx mode
>  
>  On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
>  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
>  > maybe there is interrupt line for aer pme etc. Search the interrupt
>  > number in the fdt file. Then fixup the dev->irq with it.
>  >
>  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  > ---
>  > changes for v5:
>  > 	- Add clear 'aer' interrup-names description
>  >
>  >  .../devicetree/bindings/pci/layerscape-pci.txt     | 11 +++++---
>  >  drivers/pci/pcie/portdrv_core.c                    | 31
>  +++++++++++++++++++---
>  >  2 files changed, 35 insertions(+), 7 deletions(-)
>  >
>  > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > index 41e9f55..101d0a7 100644
>  > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > @@ -18,8 +18,10 @@ Required properties:
>  >  - reg: base addresses and lengths of the PCIe controller
>  >  - interrupts: A list of interrupt outputs of the controller. Must
>  contain an
>  >    entry for each entry in the interrupt-names property.
>  > -- interrupt-names: Must include the following entries:
>  > -  "intr": The interrupt that is asserted for controller interrupts
>  > +- interrupt-names: It may be include the following entries:
>  > +  "aer": The interrupt that is asserted for aer interrupt
>  > +  "pme": The interrupt that is asserted for pme interrupt
>  > +  ......
>  >  - fsl,pcie-scfg: Must include two entries.
>  >    The first entry must be a link to the SCFG device node
>  >    The second entry must be '0' or '1' based on physical PCIe
>  controller index.
>  > @@ -35,8 +37,9 @@ Example:
>  >  		reg = <0x00 0x03400000 0x0 0x00010000   /* controller
>  registers */
>  >  		       0x40 0x00000000 0x0 0x00002000>; /* configuration
>  space */
>  >  		reg-names = "regs", "config";
>  > -		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /*
>  controller interrupt */
>  > -		interrupt-names = "intr";
>  > +		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer
>  interrupt */
>  > +			<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
>  > +		interrupt-names = "aer", "pme";
>  >  		fsl,pcie-scfg = <&scfg 0>;
>  >  		#address-cells = <3>;
>  >  		#size-cells = <2>;
>  > diff --git a/drivers/pci/pcie/portdrv_core.c
>  > b/drivers/pci/pcie/portdrv_core.c index e9270b4..7c4943d 100644
>  > --- a/drivers/pci/pcie/portdrv_core.c
>  > +++ b/drivers/pci/pcie/portdrv_core.c
>  > @@ -16,6 +16,7 @@
>  >  #include <linux/slab.h>
>  >  #include <linux/pcieport_if.h>
>  >  #include <linux/aer.h>
>  > +#include <linux/of_irq.h>
>  >
>  >  #include "../pci.h"
>  >  #include "portdrv.h"
>  > @@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev
>  > *dev, int *vectors, int mask)  static int init_service_irqs(struct
>  > pci_dev *dev, int *irqs, int mask)  {
>  >  	int i, irq = -1;
>  > +	int ret;
>  > +	struct device_node *np = NULL;
>  > +
>  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
>  > +		irqs[i] = 0;
>  > +
>  > +	if (dev->bus->dev.of_node)
>  > +		np = dev->bus->dev.of_node;
>  > +
>  > +	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
>  > +	 * request irq for aer
>  > +	 */
>  > +	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
>  > +			(mask & PCIE_PORT_SERVICE_PME)) {
>  > +		ret = of_irq_get_byname(np, "aer");
>  > +		if (ret > 0) {
>  > +			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
>  > +			if (dev->irq)
>  > +				irq = dev->irq;
>  > +			goto no_msi;
>  > +		}
>  > +	}
>  
>  We definitely need to solve this somehow.  But this approach doesn't
>  feel quite right because it's hard to map this code back to anything in
>  the spec, and it uses a completely platform-dependent name ("interrupt-
>  names aer") in code that is supposedly generic.

Very agree.

>  
>  What if we added some sort of hook that would return the IRQ?  Maybe a
>  pcibios_*() hook right now, with the idea of making it a pci_host_bridge
>  function pointer someday?

Good idea. I'll try one version patch soon.

>  
>  I know the body of the hook would look a lot like what you have here,
>  but at least it would be more obvious that it's platform-specific code.
>  
Not agree more.

>  I think your platform supports PME interrupts as well as AER, and
>  they're different IRQs.  So you'd probably have to do something similar
>  to the pcie_port_enable_msix() interface, so you can fill in both IRQs.
> 

Ok, understand.

Po
 
>  >  	/*
>  >  	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
>  @@
>  > -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev,
>  int *irqs, int mask)
>  >  		irq = dev->irq;
>  >
>  >   no_msi:
>  > -	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
>  > -		irqs[i] = irq;
>  > +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
>  > +		if (!irqs[i])
>  > +			irqs[i] = irq;
>  > +	}
>  >  	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
>  >
>  > -	if (irq < 0)
>  > +	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
>  >  		return -ENODEV;
>  >  	return 0;
>  >  }
>  > --
>  > 2.1.0.27.g96db324
>  >
>  >
>  > _______________________________________________
>  > linux-arm-kernel mailing list
>  > linux-arm-kernel@lists.infradead.org
>  > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Rob Herring]

On Sun, Sep 18, 2016 at 03:37:27AM +0000, Po Liu wrote:
> Hi Shawn,
> 
> 
> >  -----Original Message-----
> >  From: Shawn Guo [mailto:shawnguo@kernel.org]
> >  Sent: Sunday, September 18, 2016 8:52 AM
> >  To: Po Liu
> >  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> >  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang; Arnd
> >  Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali
> >  Karicheri; Bjorn Helgaas; Mingkai Hu
> >  Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none
> >  MSI/MSI-X/INTx mode
> >  
> >  On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
> >  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> >  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> >  > maybe there is interrupt line for aer pme etc. Search the interrupt
> >  > number in the fdt file. Then fixup the dev->irq with it.
> >  >
> >  > Signed-off-by: Po Liu <po.liu@nxp.com>
> >  
> >  Will the new kernel work with existing/old DTB?  I'm trying to
> >  understand the dependency between driver and DTS changes.
> 
> Yes, We've never use name 'intr' before. So we remove it is ok. 
> 'aer' is a dts name for researching it's true interrupt number by 
> kernel. This patch is first time to use name 'aer'. So it must be 
> compatible with existing/old DTB.

Please explain why you are not breaking compatibility in the commit 
message. I asked for this on v2.

> >  > ---
> >  > changes for v5:
> >  > 	- Add clear 'aer' interrup-names description
> >  >
> >  >  .../devicetree/bindings/pci/layerscape-pci.txt     | 11 +++++---
> >  >  drivers/pci/pcie/portdrv_core.c                    | 31
> >  +++++++++++++++++++---
> >  >  2 files changed, 35 insertions(+), 7 deletions(-)
> >  >
> >  > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> >  > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> >  > index 41e9f55..101d0a7 100644
> >  > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> >  > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> >  > @@ -18,8 +18,10 @@ Required properties:
> >  >  - reg: base addresses and lengths of the PCIe controller
> >  >  - interrupts: A list of interrupt outputs of the controller. Must
> >  contain an
> >  >    entry for each entry in the interrupt-names property.
> >  > -- interrupt-names: Must include the following entries:
> >  > -  "intr": The interrupt that is asserted for controller interrupts
> >  > +- interrupt-names: It may be include the following entries:

"may be" is not okay. It should be "must" or explain when an interrupt 
would not be present. Really, differences in interrupts means you need 
different compatible strings.

Rob

> >  > +  "aer": The interrupt that is asserted for aer interrupt
> >  > +  "pme": The interrupt that is asserted for pme interrupt
> >  > +  ......

RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Po Liu]

Hi Rob,

>  -----Original Message-----
>  From: Rob Herring [mailto:robh@kernel.org]
>  Sent: Friday, September 23, 2016 9:06 PM
>  To: Po Liu
>  Cc: Shawn Guo; linux-pci@vger.kernel.org; linux-arm-
>  kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
>  devicetree@vger.kernel.org; Roy Zang; Arnd Bergmann; Marc Zyngier;
>  Stuart Yoder; Leo Li; M.H. Lian; Murali Karicheri; Bjorn Helgaas;
>  Mingkai Hu
>  Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none
>  MSI/MSI-X/INTx mode
>  
>  On Sun, Sep 18, 2016 at 03:37:27AM +0000, Po Liu wrote:
>  > Hi Shawn,
>  >
>  >
>  > >  -----Original Message-----
>  > >  From: Shawn Guo [mailto:shawnguo@kernel.org]
>  > >  Sent: Sunday, September 18, 2016 8:52 AM
>  > >  To: Po Liu
>  > >  Cc: linux-pci@vger.kernel.org;
>  > > linux-arm-kernel@lists.infradead.org;
>  > >  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang;
>  > > Arnd  Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian;
>  > > Murali  Karicheri; Bjorn Helgaas; Mingkai Hu
>  > >  Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with
>  > > none  MSI/MSI-X/INTx mode
>  > >
>  > >  On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
>  > >  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC
>  mode.
>  > >  > When chip support the aer interrupt with none MSI/MSI-X/INTx
>  > > mode,  > maybe there is interrupt line for aer pme etc. Search the
>  > > interrupt  > number in the fdt file. Then fixup the dev->irq with it.
>  > >  >
>  > >  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  > >
>  > >  Will the new kernel work with existing/old DTB?  I'm trying to
>  > > understand the dependency between driver and DTS changes.
>  >
>  > Yes, We've never use name 'intr' before. So we remove it is ok.
>  > 'aer' is a dts name for researching it's true interrupt number by
>  > kernel. This patch is first time to use name 'aer'. So it must be
>  > compatible with existing/old DTB.
>  
>  Please explain why you are not breaking compatibility in the commit
>  message. I asked for this on v2.

Sorry, I didn't really catch what your means. Do you mean I should add why I remove the 'intr'?

>  
>  > >  > ---
>  > >  > changes for v5:
>  > >  > 	- Add clear 'aer' interrup-names description
>  > >  >
>  > >  >  .../devicetree/bindings/pci/layerscape-pci.txt     | 11 +++++---
>  > >  >  drivers/pci/pcie/portdrv_core.c                    | 31
>  > >  +++++++++++++++++++---
>  > >  >  2 files changed, 35 insertions(+), 7 deletions(-)  >  > diff
>  > > --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > >  > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > >  > index 41e9f55..101d0a7 100644
>  > >  > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > >  > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > >  > @@ -18,8 +18,10 @@ Required properties:
>  > >  >  - reg: base addresses and lengths of the PCIe controller  >  -
>  > > interrupts: A list of interrupt outputs of the controller. Must
>  > > contain an
>  > >  >    entry for each entry in the interrupt-names property.
>  > >  > -- interrupt-names: Must include the following entries:
>  > >  > -  "intr": The interrupt that is asserted for controller
>  > > interrupts  > +- interrupt-names: It may be include the following
>  entries:
>  
>  "may be" is not okay. It should be "must" or explain when an interrupt
>  would not be present. Really, differences in interrupts means you need
>  different compatible strings.

How about changing "must" to "should" or "could" and also add when to add after "aer": to explain when to add it?

Thanks!

>  
>  Rob
>  
>  > >  > +  "aer": The interrupt that is asserted for aer interrupt  > +
>  > > "pme": The interrupt that is asserted for pme interrupt  > +  ......

[PATCH v6 1/3] arm/dts-ls1021: add pcie aer/pme interrupt-name property in the dts

[Po Liu]

NXP arm aer/pme interrupts was not MSI/MSI-X/INTx but using interrupt
line independently. This patch add a "aer" "pme" interrupt-names for
aer/pme interrupts.

With the interrupt-names "aer","pme" code could probe aer/pme interrupt
line for pcie root port, replace the aer/pme interrupt service irqs.

This patch is intend to fixup the Layerscape platforms which aer/pme
interrupt was not MSI/MSI-X/INTx, but using interrupt line independently.

Since the interrupt-names "intr" never been used. Remove it.

Signed-off-by: Po Liu <po.liu-3arQi8VN3Tc@public.gmane.org>
---
changes for v6:
	- add remove "intr" reason;
	- add "pme" interrupt;

 arch/arm/boot/dts/ls1021a.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..9b3cb3b 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -634,7 +634,9 @@
 			reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+					   <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "pme", "aer";
 			fsl,pcie-scfg = <&scfg 0>;
 			#address-cells = <3>;
 			#size-cells = <2>;
@@ -657,7 +659,9 @@
 			reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+					   <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "pme", "aer";
 			fsl,pcie-scfg = <&scfg 1>;
 			#address-cells = <3>;
 			#size-cells = <2>;
-- 
2.1.0.27.g96db324

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[PATCH v6 2/3] arm64/dts-ls1043-ls2080: add pcie aer/pme interrupt-name property in the dts

[Po Liu]

Some platforms(NXP Layerscape for example) aer/pme interrupts was not
MSI/MSI-X/INTx but using interrupt line independently. This patch
add "aer", "pme" interrupt-names for aer/pme interrupt.

With the interrupt-names "aer", "pme" code could probe aer/pme interrupt
line for pcie root port, replace the aer/pme interrupt service irqs.

This is intend to fixup the Layerscape platforms which aer/pmes interrupts
was not MSI/MSI-X/INTx, but using interrupt line independently.

Since the interrupt-names "intr" never been used. Remove it.

Signed-off-by: Po Liu <po.liu@nxp.com>
---
changes for v6:
	- add remove "intr" interrupt reason.
	- add "pme" interrupt.

 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +++++++++---------
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 ++++++++--------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index e669fbd..654071d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -527,9 +527,9 @@
 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 118 0x4>, /* controller interrupt */
-				     <0 117 0x4>; /* PME interrupt */
-			interrupt-names = "intr", "pme";
+			interrupts = <0 117 0x4>, /* PME interrupt */
+					 <0 118 0x4>; /* aer interrupt */
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -552,9 +552,9 @@
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 128 0x4>,
-				     <0 127 0x4>;
-			interrupt-names = "intr", "pme";
+			interrupts = <0 127 0x4>,
+					 <0 128 0x4>;
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -577,9 +577,9 @@
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 162 0x4>,
-				     <0 161 0x4>;
-			interrupt-names = "intr", "pme";
+			interrupts = <0 161 0x4>,
+					 <0 162 0x4>;
+			interrupt-names = "pme", "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 21023a3..58844e8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -583,8 +583,8 @@
 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 			       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 108 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 108 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -607,8 +607,8 @@
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 			       0x12 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 113 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 113 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -631,8 +631,8 @@
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 			       0x14 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 118 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 118 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -655,8 +655,8 @@
 			reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
 			       0x16 0x00000000 0x0 0x00002000>; /* configuration space */
 			reg-names = "regs", "config";
-			interrupts = <0 123 0x4>; /* Level high type */
-			interrupt-names = "intr";
+			interrupts = <0 123 0x4>; /* aer interrupt */
+			interrupt-names = "aer";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-- 
2.1.0.27.g96db324

[PATCH v6 3/3] pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode

[Po Liu]

On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer/pme interrupts with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.

Signed-off-by: Po Liu <po.liu@nxp.com>
---
changes for v6:
	- modify bindings for "aer""pme";
	- changing to the hood method to implement the aer pme interrupt;
	- add pme interrupt in the same way;

 .../devicetree/bindings/pci/layerscape-pci.txt     | 13 +++++--
 arch/arm/kernel/bios32.c                           | 43 ++++++++++++++++++++++
 arch/arm64/kernel/pci.c                            | 43 ++++++++++++++++++++++
 drivers/pci/pcie/portdrv_core.c                    | 31 +++++++++++++++-
 include/linux/pci.h                                |  1 +
 5 files changed, 126 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 41e9f55..51ed49e 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -18,8 +18,12 @@ Required properties:
 - reg: base addresses and lengths of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
-- interrupt-names: Must include the following entries:
-  "intr": The interrupt that is asserted for controller interrupts
+- interrupt-names: It could include the following entries:
+  "aer": Asserted for aer interrupt when chip support the aer interrupt with
+		 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
+  "pme": Asserted for pme interrupt when chip support the pme interrupt with
+		 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
+  ......
 - fsl,pcie-scfg: Must include two entries.
   The first entry must be a link to the SCFG device node
   The second entry must be '0' or '1' based on physical PCIe controller index.
@@ -35,8 +39,9 @@ Example:
 		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 		reg-names = "regs", "config";
-		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-		interrupt-names = "intr";
+		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */
+			<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
+		interrupt-names = "aer", "pme";
 		fsl,pcie-scfg = <&scfg 0>;
 		#address-cells = <3>;
 		#size-cells = <2>;
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 2f0e077..d2f4869 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -11,6 +11,8 @@
 #include <linux/slab.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/of_irq.h>
+#include <linux/pcieport_if.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -64,6 +66,47 @@ void pcibios_report_status(u_int status_mask, int warn)
 }
 
 /*
+ * Check device tree if the service interrupts are there
+ */
+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
+{
+	int ret, count = 0;
+	struct device_node *np = NULL;
+
+	if (dev->bus->dev.of_node)
+		np = dev->bus->dev.of_node;
+
+	if (np == NULL)
+		return 0;
+
+	if (!IS_ENABLED(CONFIG_OF_IRQ))
+		return 0;
+
+	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+	 * request irq for aer
+	 */
+	if (mask & PCIE_PORT_SERVICE_AER) {
+		ret = of_irq_get_byname(np, "aer");
+		if (ret > 0) {
+			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
+			count++;
+		}
+	}
+
+	if (mask & PCIE_PORT_SERVICE_PME) {
+		ret = of_irq_get_byname(np, "pme");
+		if (ret > 0) {
+			irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
+			count++;
+		}
+	}
+
+	/* TODO: add more service interrupts if there it is in the device tree*/
+
+	return count;
+}
+
+/*
  * We don't use this to fix the device, but initialisation of it.
  * It's not the correct use for this, but it works.
  * Note that the arbiter/ISA bridge appears to be buggy, specifically in
diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
index acf3872..4a3c61a 100644
--- a/arch/arm64/kernel/pci.c
+++ b/arch/arm64/kernel/pci.c
@@ -17,6 +17,8 @@
 #include <linux/mm.h>
 #include <linux/of_pci.h>
 #include <linux/of_platform.h>
+#include <linux/of_irq.h>
+#include <linux/pcieport_if.h>
 #include <linux/pci.h>
 #include <linux/pci-acpi.h>
 #include <linux/pci-ecam.h>
@@ -55,6 +57,47 @@ int pcibios_alloc_irq(struct pci_dev *dev)
 }
 
 /*
+ * Check device tree if the service interrupts are there
+ */
+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
+{
+	int ret, count = 0;
+	struct device_node *np = NULL;
+
+	if (dev->bus->dev.of_node)
+		np = dev->bus->dev.of_node;
+
+	if (np == NULL)
+		return 0;
+
+	if (!IS_ENABLED(CONFIG_OF_IRQ))
+		return 0;
+
+	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+	 * request irq for aer
+	 */
+	if (mask & PCIE_PORT_SERVICE_AER) {
+		ret = of_irq_get_byname(np, "aer");
+		if (ret > 0) {
+			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
+			count++;
+		}
+	}
+
+	if (mask & PCIE_PORT_SERVICE_PME) {
+		ret = of_irq_get_byname(np, "pme");
+		if (ret > 0) {
+			irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
+			count++;
+		}
+	}
+
+	/* TODO: add more service interrupts if there it is in the device tree*/
+
+	return count;
+}
+
+/*
  * raw_pci_read/write - Platform-specific PCI config space access.
  */
 int raw_pci_read(unsigned int domain, unsigned int bus,
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index e9270b4..34b6dae 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -44,6 +44,19 @@ static void release_pcie_device(struct device *dev)
 }
 
 /**
+ * pcibios_check_service_irqs - check irqs in the device tree
+ * @dev: PCI Express port to handle
+ * @irqs: Array of irqs to populate
+ * @mask: Bitmask of port capabilities returned by get_port_device_capability()
+ *
+ * Return value: 0 means no service irqs in the device tree
+ *
+ */
+int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
+{
+	return 0;
+}
+/**
  * pcie_port_msix_add_entry - add entry to given array of MSI-X entries
  * @entries: Array of MSI-X entries
  * @new_entry: Index of the entry to add to the array
@@ -200,6 +213,21 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
 static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
 {
 	int i, irq = -1;
+	int ret;
+
+	/* Check if some platforms owns independent irq pins for AER/PME etc.
+	 * Some platforms may own independent AER/PME interrupts and set
+	 * them in the device tree file.
+	 */
+	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
+			irqs[i] = -1;
+
+	ret = pcibios_check_service_irqs(dev, irqs, mask);
+	if (ret) {
+		if (dev->irq)
+			irq = dev->irq;
+		goto no_msi;
+	}
 
 	/*
 	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
@@ -226,7 +254,8 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
 
  no_msi:
 	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
-		irqs[i] = irq;
+		if (irqs[i] == -1)
+			irqs[i] = irq;
 	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
 
 	if (irq < 0)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 2599a98..c80f2d0 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1793,6 +1793,7 @@ void pcibios_release_device(struct pci_dev *dev);
 void pcibios_penalize_isa_irq(int irq, int active);
 int pcibios_alloc_irq(struct pci_dev *dev);
 void pcibios_free_irq(struct pci_dev *dev);
+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
 
 #ifdef CONFIG_HIBERNATE_CALLBACKS
 extern struct dev_pm_ops pcibios_pm_ops;
-- 
2.1.0.27.g96db324

Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode

[Shawn Guo]

On Wed, Sep 21, 2016 at 06:54:59AM +0000, Po Liu wrote:
> >  > >  Will the new kernel work with existing/old DTB?  I'm trying to
> >  > > understand the dependency between driver and DTS changes.
> >  >
> >  > Yes, We've never use name 'intr' before. So we remove it is ok.
> >  > 'aer' is a dts name for researching it's true interrupt number by
> >  kernel. This patch is first time to use name 'aer'. So it must be
> >  compatible with existing/old DTB.
> >  
> >  Does that mean driver and DTS changes can go through separate trees, i.e.
> >  PCI and arm-soc, without introducing regressions on either tree?
> >  Or does the patch series needs to go in as a whole?
> 
> Should be as a whole. The driver base on the dts. Or else, the driver would not found the 'aer' point.

Let me try to understand this one more time.  So if the new kernel boots
with an existing DTB, the driver will fail to find 'aer' interrupt,
right?  My question is that in this case, the driver will just stop
working or keep working in the same way as old kernel.  The former case
is a regression which breaks old DTB support, and the latter is pretty
much like that we are adding a new support, and the DTS change can go
independently with driver part through different subsystem tree.

Hope I make my question clear this time.

Shawn

Re: [PATCH v6 3/3] pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode

[Rob Herring]

On Fri, Sep 30, 2016 at 05:11:37PM +0800, Po Liu wrote:
> On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> When chip support the aer/pme interrupts with none MSI/MSI-X/INTx mode,
> maybe there is interrupt line for aer pme etc. Search the interrupt
> number in the fdt file. Then fixup the dev->irq with it.

Again, explain why you are breaking compatibility. Will an old dtb using 
"intr" still work with this change? It should normally. There are some 
exceptions, but you need to say what they are.

> 
> Signed-off-by: Po Liu <po.liu-3arQi8VN3Tc@public.gmane.org>
> ---
> changes for v6:
> 	- modify bindings for "aer""pme";
> 	- changing to the hood method to implement the aer pme interrupt;
> 	- add pme interrupt in the same way;
> 
>  .../devicetree/bindings/pci/layerscape-pci.txt     | 13 +++++--
>  arch/arm/kernel/bios32.c                           | 43 ++++++++++++++++++++++
>  arch/arm64/kernel/pci.c                            | 43 ++++++++++++++++++++++
>  drivers/pci/pcie/portdrv_core.c                    | 31 +++++++++++++++-
>  include/linux/pci.h                                |  1 +
>  5 files changed, 126 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 41e9f55..51ed49e 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -18,8 +18,12 @@ Required properties:
>  - reg: base addresses and lengths of the PCIe controller
>  - interrupts: A list of interrupt outputs of the controller. Must contain an
>    entry for each entry in the interrupt-names property.
> -- interrupt-names: Must include the following entries:
> -  "intr": The interrupt that is asserted for controller interrupts
> +- interrupt-names: It could include the following entries:

"Could" is not strong enough. Every valid combination of interrupts 
should correspond to a specific compatible string. A given version of 
h/w either has these interrupts or not.

> +  "aer": Asserted for aer interrupt when chip support the aer interrupt with
> +		 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
> +  "pme": Asserted for pme interrupt when chip support the pme interrupt with
> +		 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
> +  ......
>  - fsl,pcie-scfg: Must include two entries.
>    The first entry must be a link to the SCFG device node
>    The second entry must be '0' or '1' based on physical PCIe controller index.
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RE: [PATCH v6 3/3] pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode

[Po Liu]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 3536 bytes --]

Hi Rob,

Best regards,
Liu Po

>  -----Original Message-----
>  From: Rob Herring [mailto:robh@kernel.org]
>  Sent: Sunday, October 09, 2016 4:50 AM
>  To: Po Liu
>  Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>  linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Bjorn Helgaas;
>  Shawn Guo; Marc Zyngier; Roy Zang; Mingkai Hu; Stuart Yoder; Leo Li;
>  Arnd Bergmann; M.H. Lian; Murali Karicheri
>  Subject: Re: [PATCH v6 3/3] pci:add support aer/pme interrupts with none
>  MSI/MSI-X/INTx mode
>  
>  On Fri, Sep 30, 2016 at 05:11:37PM +0800, Po Liu wrote:
>  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
>  > When chip support the aer/pme interrupts with none MSI/MSI-X/INTx
>  > mode, maybe there is interrupt line for aer pme etc. Search the
>  > interrupt number in the fdt file. Then fixup the dev->irq with it.
>  
>  Again, explain why you are breaking compatibility. Will an old dtb using
>  "intr" still work with this change? It should normally. There are some
>  exceptions, but you need to say what they are.
>  
Ok, understand.

>  >
>  > Signed-off-by: Po Liu <po.liu@nxp.com>
>  > ---
>  > changes for v6:
>  > 	- modify bindings for "aer""pme";
>  > 	- changing to the hood method to implement the aer pme interrupt;
>  > 	- add pme interrupt in the same way;
>  >
>  >  .../devicetree/bindings/pci/layerscape-pci.txt     | 13 +++++--
>  >  arch/arm/kernel/bios32.c                           | 43
>  ++++++++++++++++++++++
>  >  arch/arm64/kernel/pci.c                            | 43
>  ++++++++++++++++++++++
>  >  drivers/pci/pcie/portdrv_core.c                    | 31
>  +++++++++++++++-
>  >  include/linux/pci.h                                |  1 +
>  >  5 files changed, 126 insertions(+), 5 deletions(-)
>  >
>  > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > index 41e9f55..51ed49e 100644
>  > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
>  > @@ -18,8 +18,12 @@ Required properties:
>  >  - reg: base addresses and lengths of the PCIe controller
>  >  - interrupts: A list of interrupt outputs of the controller. Must
>  contain an
>  >    entry for each entry in the interrupt-names property.
>  > -- interrupt-names: Must include the following entries:
>  > -  "intr": The interrupt that is asserted for controller interrupts
>  > +- interrupt-names: It could include the following entries:
>  
>  "Could" is not strong enough. Every valid combination of interrupts
>  should correspond to a specific compatible string. A given version of
>  h/w either has these interrupts or not.

Ok, will change to 'must'.

>  
>  > +  "aer": Asserted for aer interrupt when chip support the aer
>  interrupt with
>  > +		 none MSI/MSI-X/INTx mode,but there is interrupt line for
>  aer.
>  > +  "pme": Asserted for pme interrupt when chip support the pme
>  interrupt with
>  > +		 none MSI/MSI-X/INTx mode,but there is interrupt line for
>  pme.
>  > +  ......
>  >  - fsl,pcie-scfg: Must include two entries.
>  >    The first entry must be a link to the SCFG device node
>  >    The second entry must be '0' or '1' based on physical PCIe
>  controller index.
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