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From: Archit Taneja <architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
	robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org,
	p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Archit Taneja <architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Subject: [PATCH v2 01/10] drm/msm/mdp5: Don't get source of MDP core clock
Date: Fri, 10 Jun 2016 16:16:31 +0530	[thread overview]
Message-ID: <1465555600-25742-2-git-send-email-architt@codeaurora.org> (raw)
In-Reply-To: <1465555600-25742-1-git-send-email-architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>

The driver expects DT to provide the parent to MDP core clock. The only
operation done to the parent clock is to set a rate. This can be
achieved by setting the rate on the core clock itsef. Don't try to
get the parent clock anymore.

Signed-off-by: Archit Taneja <architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 7 ++-----
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 -
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 1d840ae..b46961e 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -629,9 +629,6 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
 	ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true);
 	if (ret)
 		goto fail;
-	ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src", true);
-	if (ret)
-		goto fail;
 	ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true);
 	if (ret)
 		goto fail;
@@ -646,7 +643,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
 	 * rate first, then figure out hw revision, and then set a
 	 * more optimal rate:
 	 */
-	clk_set_rate(mdp5_kms->src_clk, 200000000);
+	clk_set_rate(mdp5_kms->core_clk, 200000000);
 
 	read_hw_revision(mdp5_kms, &major, &minor);
 
@@ -661,7 +658,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
 	mdp5_kms->caps = config->hw->mdp.caps;
 
 	/* TODO: compute core clock rate at runtime */
-	clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk);
+	clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);
 
 	/*
 	 * Some chipsets have a Shared Memory Pool (SMP), while others
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
index 9a25898..9cf5aa4 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
@@ -49,7 +49,6 @@ struct mdp5_kms {
 
 	struct clk *axi_clk;
 	struct clk *ahb_clk;
-	struct clk *src_clk;
 	struct clk *core_clk;
 	struct clk *lut_clk;
 	struct clk *vsync_clk;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

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  parent reply	other threads:[~2016-06-10 10:46 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-03 10:57 [PATCH 0/9] drm/msm: Fix issues with DT bindings Archit Taneja
2016-05-03 10:57 ` [PATCH 1/9] drm/msm: Get mdss components via parsing ports Archit Taneja
2016-05-03 10:57 ` [PATCH 2/9] drm/msm: Drop the gpu binding Archit Taneja
2016-05-03 12:42   ` Rob Herring
2016-05-04  6:45     ` Archit Taneja
2016-05-03 10:57 ` [PATCH 3/9] drm/msm/mdp: mdp4: Update LCDC/LVDS port parsing Archit Taneja
2016-05-03 13:50   ` Philipp Zabel
2016-05-03 10:57 ` [PATCH 4/9] dt-bindings: msm/mdp: Remove connector and gpu bindings Archit Taneja
2016-05-04 13:38   ` Rob Herring
2016-05-04 17:49     ` Archit Taneja
     [not found] ` <1462273081-5814-1-git-send-email-architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-05-03 10:57   ` [PATCH 5/9] dt-bindings: msm/dsi: Some binding doc cleanups Archit Taneja
2016-05-03 14:05     ` Philipp Zabel
2016-05-04  8:11       ` Archit Taneja
2016-05-03 10:58   ` [PATCH 8/9] dt-bindings: msm/dsi: Modify port and PHY bindings Archit Taneja
2016-05-03 14:02     ` Philipp Zabel
2016-05-04  8:09       ` Archit Taneja
2016-05-03 10:57 ` [PATCH 6/9] drm/msm/dsi: Modify port parsing Archit Taneja
2016-05-03 10:57 ` [PATCH 7/9] drm/msm/dsi: Use generic PHY bindings Archit Taneja
2016-05-03 10:58 ` [PATCH 9/9] dt-bindings: msm/dsi: Add assigned clocks bindings Archit Taneja
2016-05-04 13:44   ` Rob Herring
2016-05-04 18:04     ` Archit Taneja
     [not found]       ` <572A39B7.5020008-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-05-11 14:08         ` Rob Herring
2016-06-10 10:46 ` [PATCH v2 00/10] drm/msm: Fix issues with DT bindings Archit Taneja
     [not found]   ` <1465555600-25742-1-git-send-email-architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-06-10 10:46     ` Archit Taneja [this message]
2016-06-10 10:46     ` [PATCH v2 03/10] dt-bindings: msm/mdp: Fix up clock related bindings Archit Taneja
2016-06-13 19:03       ` Rob Herring
2016-06-16  5:08         ` Archit Taneja
2016-06-10 10:46     ` [PATCH v2 07/10] dt-bindings: msm/dsi: Use standard data lanes binding Archit Taneja
2016-06-13 19:53       ` Rob Herring
2016-06-10 10:46     ` [PATCH v2 10/10] dt-bindings: msm/dsi: Some binding doc cleanups Archit Taneja
2016-06-14 12:33       ` Rob Herring
2016-06-10 10:46   ` [PATCH v2 02/10] drm/msm/mdp4: Clean up some MDP4 clocks Archit Taneja
2016-06-10 10:46   ` [PATCH v2 04/10] drm/msm/dsi: Modify port parsing Archit Taneja
2016-06-10 10:46   ` [PATCH v2 05/10] drm/msm/dsi: Use generic PHY bindings Archit Taneja
2016-06-10 10:46   ` [PATCH v2 06/10] drm/msm/dsi: Use a standard DT binding for data lanes Archit Taneja
2016-06-10 10:46   ` [PATCH v2 08/10] dt-bindings: msm/dsi: Modify port and PHY bindings Archit Taneja
2016-06-14 12:31     ` Rob Herring
2016-06-10 10:46   ` [PATCH v2 09/10] dt-bindings: msm/dsi: Add assigned clocks bindings Archit Taneja

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