[v2 PATCH 0/4] Rockchip Type-C and DispplayPort driver

[v2 PATCH 0/4] Rockchip Type-C and DispplayPort driver

[Chris Zhong]

Hi all

This series patch is for rockchip Type-C phy and DisplayPort controller
driver.

The USB Type-C PHY is designed to support the USB3 and DP applications.
The PHY basically has two main components: USB3 and DisplyPort. USB3
operates in SuperSpeed mode and the DP can operate at RBR, HBR and HBR2
data rates. The Type-C cable orientation detection and Power Delivery
(PD) is accomplished using a PD PHY or a exernal PD chip.

The DP controller is compliant with DisplayPort Specification,
Version 1.3, This IP is compatible with the rockchip type-c PHY IP.
There is a uCPU in DP controller, it need a firmware to work, please
put the firmware file to /lib/firmware/cdn/dptx.bin. The uCPU in charge
of aux communication and link training, the host use mailbox to
communicate with the ucpu.

The PHY driver has register a notification with extcon API, to get the
alt mode from PD, the PD driver need call the devm_extcon_dev_allocate
to create a extcon device and use extcon_set_state to notify PHY and
DP controller.

About the DP audio, cdn-dp registered 2 DAIs: 0 is I2S, 1 is SPDIF.
We can reference them in simple-card.

This series is based on Mark Yao's branch:
https://github.com/markyzq/kernel-drm-rockchip/tree/drm-rockchip-next-2016-05-23

I test this patches on the rk3399-evb board, with a fusb302 driver,
this branch has no rk3399.dtsi, so the patch about dts is not included
in this series.


Changes in v2:
- add some registers description
- select RESET_CONTROLLER
- alphabetic order
- modify some spelling mistakes
- make mode cleaner
- use bool for enable/disable
- check all of the return value
- return a better err number
- use more readx_poll_timeout()
- clk_disable_unprepare(tcphy->clk_ref);
- remove unuse functions, rockchip_typec_phy_power_on/off
- remove unnecessary typecast from void *
- use dts node to distinguish between phys.
- Alphabetic order
- remove excess error message
- use define clk_rate
- check all return value
- remove dev_set_name(dp->dev, "cdn-dp");
- use schedule_delayed_work
- remove never-called functions
- remove some unnecessary ()

Changes in v1:
- add extcon node description
- move the registers in phy driver
- remove the suffix of reset
- update the licence note
- init core clock to 50MHz
- use extcon API
- remove unused global
- add some comments for magic num
- change usleep_range(1000, 2000) tousleep_range(1000, 1050)
- remove __func__ from dev_err
- return err number when get clk failed
- remove ADDR_ADJ define
- use devm_clk_get(&pdev->dev, "tcpdcore")
- add extcon node description
- add #sound-dai-cells description
- use extcon API
- use hdmi-codec for the DP Asoc
- do not initialize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line

Chris Zhong (4):
  Documentation: bindings: add dt doc for Rockchip USB Type-C PHY
  phy: Add USB Type-C PHY driver for rk3399
  Documentation: bindings: add dt documentation for cdn DP controller
  drm/rockchip: cdn-dp: add cdn DP support for rk3399

 .../bindings/display/rockchip/cdn-dp-rockchip.txt  |  62 ++
 .../devicetree/bindings/phy/phy-rockchip-typec.txt |  77 ++
 drivers/gpu/drm/rockchip/Kconfig                   |   9 +
 drivers/gpu/drm/rockchip/Makefile                  |   1 +
 drivers/gpu/drm/rockchip/cdn-dp-core.c             | 694 +++++++++++++++
 drivers/gpu/drm/rockchip/cdn-dp-core.h             | 108 +++
 drivers/gpu/drm/rockchip/cdn-dp-reg.c              | 717 ++++++++++++++++
 drivers/gpu/drm/rockchip/cdn-dp-reg.h              | 404 +++++++++
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c        |   6 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h        |   2 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c        |   2 +
 drivers/phy/Kconfig                                |   8 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-rockchip-typec.c                   | 952 +++++++++++++++++++++
 include/linux/phy/phy-rockchip-typec.h             |  20 +
 15 files changed, 3062 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
 create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.c
 create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.h
 create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.c
 create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.h
 create mode 100644 drivers/phy/phy-rockchip-typec.c
 create mode 100644 include/linux/phy/phy-rockchip-typec.h

-- 
2.6.3


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[v2 PATCH 1/4] Documentation: bindings: add dt doc for Rockchip USB Type-C PHY

[Chris Zhong]

This patch adds a binding that describes the Rockchip USB Type-C PHY
for rk3399

Signed-off-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

---

Changes in v2:
- add some registers description

Changes in v1:
- add extcon node description
- move the registers in phy driver
- remove the suffix of reset

 .../devicetree/bindings/phy/phy-rockchip-typec.txt | 77 ++++++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
new file mode 100644
index 0000000..430920c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
@@ -0,0 +1,77 @@
+* ROCKCHIP type-c PHY
+---------------------
+
+Required properties:
+ - compatible : should be "rockchip,rk3399-typec-phy0" or
+			 "rockchip,rk3399-typec-phy1"
+ - reg: Address and length of the usb phy control register set
+ - rockchip,grf : phandle to the syscon managing the "general
+   register files"
+ - clocks : phandle + clock specifier for the phy clocks
+ - clock-names : string, clock name, must be "tcpdcore", "tcpdphy_ref";
+ - resets : a list of phandle + reset specifier pairs
+ - reset-names : string reset name, must be:
+		 "tcphy", "tcphy_pipe", "uphy_tcphy"
+ - #phy-cells : Must be 0.  See ./phy-bindings.txt for details.
+ - extcon : extcon specifier for the Power Delivery
+
+Note, there are 2 type-c phys for RK3399, and they are almost identical, except
+these registers(description below), every register node contains 3 sections:
+offset, enable bit, write mask bit.
+ - rockchip,typec_conn_dir : the register of type-c connector direction,
+   for type-c phy0, it must be <0xe580 0 16>;
+   for type-c phy1, it must be <0xe58c 0 16>;
+ - rockchip,usb3tousb2_en : the register of type-c force usb3 to usb2 enable
+   control.
+   for type-c phy0, it must be <0xe580 3 19>;
+   for type-c phy1, it must be <0xe58c 3 19>;
+ - rockchip,external_psm : the register of type-c phy external psm clock
+   selection.
+   for type-c phy0, it must be <0xe588 14 30>;
+   for type-c phy1, it must be <0xe594 14 30>;
+ - rockchip,pipe_status : the register of type-c phy pipe status.
+   for type-c phy0, it must be <0xe5c0 0 0>;
+   for type-c phy1, it must be <0xe5c0 16 16>;
+ - rockchip,uphy_dp_sel : the register of type-c phy selection for DP
+   for type-c phy0, it must be <0x6268 19 19>;
+   for type-c phy1, it must be <0x6268 3 19>;
+
+Example:
+	tcphy0: phy@ff7c0000 {
+		compatible = "rockchip,rk3399-typec-phy0";
+		reg = <0x0 0xff7c0000 0x0 0x40000>;
+		#phy-cells = <0>;
+		extcon = <&fusb1>;
+		rockchip,grf = <&grf>;
+		clocks = <&cru SCLK_UPHY0_TCPDCORE>,
+			 <&cru SCLK_UPHY0_TCPDPHY_REF>;
+		clock-names = "tcpdcore", "tcpdphy_ref";
+		resets = <&cru SRST_UPHY0>,
+			 <&cru SRST_UPHY0_PIPE_L00>,
+			 <&cru SRST_P_UPHY0_TCPHY>;
+		reset-names = "tcphy", "tcphy_pipe", "uphy_tcphy";
+		rockchip,typec_conn_dir = <0xe580 0 16>;
+		rockchip,usb3tousb2_en = <0xe580 3 19>;
+		rockchip,external_psm = <0xe588 14 30>;
+		rockchip,pipe_status = <0xe5c0 0 0>;
+		rockchip,uphy_dp_sel = <0x6268 19 19>;
+	};
+
+	tcphy1: phy@ff800000 {
+		compatible = "rockchip,rk3399-typec-phy1";
+		reg = <0x0 0xff800000 0x0 0x40000>;
+		#phy-cells = <0>;
+		rockchip,grf = <&grf>;
+		clocks = <&cru SCLK_UPHY1_TCPDCORE>,
+			 <&cru SCLK_UPHY1_TCPDPHY_REF>;
+		clock-names = "tcpdcore", "tcpdphy_ref";
+		resets = <&cru SRST_UPHY1>,
+		         <&cru SRST_UPHY1_PIPE_L00>,
+			 <&cru SRST_P_UPHY1_TCPHY>;
+		reset-names = "tcphy", "tcphy_pipe", "uphy_tcphy";
+		rockchip,typec_conn_dir = <0xe58c 0 16>;
+		rockchip,usb3tousb2_en = <0xe58c 3 19>;
+		rockchip,external_psm = <0xe594 14 30>;
+		rockchip,pipe_status = <0xe5c0 16 16>;
+		rockchip,uphy_dp_sel = <0x6268 3 19>;
+	};
-- 
2.6.3

[v2 PATCH 3/4] Documentation: bindings: add dt documentation for cdn DP controller

[Chris Zhong]

This patch adds a binding that describes the cdn DP controller for
rk3399.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>

---

Changes in v2: None
Changes in v1:
- add extcon node description
- add #sound-dai-cells description

 .../bindings/display/rockchip/cdn-dp-rockchip.txt  | 62 ++++++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt

diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
new file mode 100644
index 0000000..4a66fc3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
@@ -0,0 +1,62 @@
+Rockchip RK3399 specific extensions to the cdn Display Port
+================================
+
+Required properties:
+- compatible: must be "rockchip,cdn-dp"
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+
+- clock-names: from common clock binding:
+	       Required elements: "core_clk" "pclk" "spdif"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port nodes with endpoint definitions as defined in
+	 Documentation/devicetree/bindings/media/video-interfaces.txt.
+	 contained 2 endpoints, connecting to the output of vop.
+
+- phys: from general PHY binding: the phandle for the PHY device.
+
+- extcon: extcon specifier for the Power Delivery
+
+- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
+
+-------------------------------------------------------------------------------
+
+Example:
+	cdn_dp: dp@fec00000 {
+		compatible = "rockchip,cdn-dp";
+		reg = <0x0 0xfec00000 0x0 0x100000>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
+			 <&cru SCLK_SPDIF_REC_DPTX>;
+		clock-names = "core_clk", "pclk", "spdif";
+		phys = <&tcphy0>;
+		extcon = <&fusb1>;
+		rockchip,grf = <&grf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#sound-dai-cells = <1>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			dp_in: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dp_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_dp>;
+				};
+
+				dp_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_dp>;
+				};
+			};
+		};
+	};
-- 
2.6.3


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Re: [v2 PATCH 1/4] Documentation: bindings: add dt doc for Rockchip USB Type-C PHY

[Rob Herring]

On Mon, Jun 13, 2016 at 05:39:46PM +0800, Chris Zhong wrote:
> This patch adds a binding that describes the Rockchip USB Type-C PHY
> for rk3399
> 
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> 
> ---
> 
> Changes in v2:
> - add some registers description
> 
> Changes in v1:
> - add extcon node description
> - move the registers in phy driver
> - remove the suffix of reset
> 
>  .../devicetree/bindings/phy/phy-rockchip-typec.txt | 77 ++++++++++++++++++++++
>  1 file changed, 77 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> new file mode 100644
> index 0000000..430920c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> @@ -0,0 +1,77 @@
> +* ROCKCHIP type-c PHY
> +---------------------
> +
> +Required properties:
> + - compatible : should be "rockchip,rk3399-typec-phy0" or
> +			 "rockchip,rk3399-typec-phy1"

Unless these blocks are different, these should be be same compat 
string.

> + - reg: Address and length of the usb phy control register set
> + - rockchip,grf : phandle to the syscon managing the "general
> +   register files"
> + - clocks : phandle + clock specifier for the phy clocks
> + - clock-names : string, clock name, must be "tcpdcore", "tcpdphy_ref";
> + - resets : a list of phandle + reset specifier pairs
> + - reset-names : string reset name, must be:
> +		 "tcphy", "tcphy_pipe", "uphy_tcphy"
> + - #phy-cells : Must be 0.  See ./phy-bindings.txt for details.
> + - extcon : extcon specifier for the Power Delivery
> +
> +Note, there are 2 type-c phys for RK3399, and they are almost identical, except
> +these registers(description below), every register node contains 3 sections:
> +offset, enable bit, write mask bit.
> + - rockchip,typec_conn_dir : the register of type-c connector direction,

Don't use underscores in property names.

> +   for type-c phy0, it must be <0xe580 0 16>;
> +   for type-c phy1, it must be <0xe58c 0 16>;
> + - rockchip,usb3tousb2_en : the register of type-c force usb3 to usb2 enable
> +   control.
> +   for type-c phy0, it must be <0xe580 3 19>;
> +   for type-c phy1, it must be <0xe58c 3 19>;
> + - rockchip,external_psm : the register of type-c phy external psm clock
> +   selection.
> +   for type-c phy0, it must be <0xe588 14 30>;
> +   for type-c phy1, it must be <0xe594 14 30>;
> + - rockchip,pipe_status : the register of type-c phy pipe status.
> +   for type-c phy0, it must be <0xe5c0 0 0>;
> +   for type-c phy1, it must be <0xe5c0 16 16>;
> + - rockchip,uphy_dp_sel : the register of type-c phy selection for DP
> +   for type-c phy0, it must be <0x6268 19 19>;
> +   for type-c phy1, it must be <0x6268 3 19>;

Re: [v2 PATCH 3/4] Documentation: bindings: add dt documentation for cdn DP controller

[Rob Herring]

On Mon, Jun 13, 2016 at 05:39:48PM +0800, Chris Zhong wrote:
> This patch adds a binding that describes the cdn DP controller for
> rk3399.
> 
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> 
> ---
> 
> Changes in v2: None
> Changes in v1:
> - add extcon node description
> - add #sound-dai-cells description
> 
>  .../bindings/display/rockchip/cdn-dp-rockchip.txt  | 62 ++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
> 
> diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
> new file mode 100644
> index 0000000..4a66fc3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
> @@ -0,0 +1,62 @@
> +Rockchip RK3399 specific extensions to the cdn Display Port
> +================================
> +
> +Required properties:
> +- compatible: must be "rockchip,cdn-dp"

SoC specific compatible string please.

> +
> +- reg: physical base address of the controller and length
> +
> +- clocks: from common clock binding: handle to dp clock.
> +
> +- clock-names: from common clock binding:
> +	       Required elements: "core_clk" "pclk" "spdif"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +
> +- ports: contain a port nodes with endpoint definitions as defined in
> +	 Documentation/devicetree/bindings/media/video-interfaces.txt.
> +	 contained 2 endpoints, connecting to the output of vop.
> +
> +- phys: from general PHY binding: the phandle for the PHY device.
> +
> +- extcon: extcon specifier for the Power Delivery
> +
> +- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
> +
> +-------------------------------------------------------------------------------
> +
> +Example:
> +	cdn_dp: dp@fec00000 {
> +		compatible = "rockchip,cdn-dp";
> +		reg = <0x0 0xfec00000 0x0 0x100000>;
> +		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
> +			 <&cru SCLK_SPDIF_REC_DPTX>;
> +		clock-names = "core_clk", "pclk", "spdif";
> +		phys = <&tcphy0>;
> +		extcon = <&fusb1>;
> +		rockchip,grf = <&grf>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		#sound-dai-cells = <1>;
> +
> +		ports {

> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <1>;

Don't need these with a single port.

> +
> +			dp_in: port {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dp_in_vopb: endpoint@0 {
> +					reg = <0>;
> +					remote-endpoint = <&vopb_out_dp>;
> +				};
> +
> +				dp_in_vopl: endpoint@1 {
> +					reg = <1>;
> +					remote-endpoint = <&vopl_out_dp>;
> +				};
> +			};
> +		};
> +	};
> -- 
> 2.6.3
> 
> 

Re: [v2 PATCH 1/4] Documentation: bindings: add dt doc for Rockchip USB Type-C PHY

[Heiko Stuebner]

Am Montag, 13. Juni 2016, 17:39:46 schrieb Chris Zhong:
> This patch adds a binding that describes the Rockchip USB Type-C PHY
> for rk3399
> 
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> 
> ---
> 
> Changes in v2:
> - add some registers description
> 
> Changes in v1:
> - add extcon node description
> - move the registers in phy driver
> - remove the suffix of reset
> 
>  .../devicetree/bindings/phy/phy-rockchip-typec.txt | 77
> ++++++++++++++++++++++ 1 file changed, 77 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt new file
> mode 100644
> index 0000000..430920c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> @@ -0,0 +1,77 @@
> +* ROCKCHIP type-c PHY
> +---------------------
> +
> +Required properties:
> + - compatible : should be "rockchip,rk3399-typec-phy0" or
> +			 "rockchip,rk3399-typec-phy1"
> + - reg: Address and length of the usb phy control register set
> + - rockchip,grf : phandle to the syscon managing the "general
> +   register files"
> + - clocks : phandle + clock specifier for the phy clocks
> + - clock-names : string, clock name, must be "tcpdcore", "tcpdphy_ref";
> + - resets : a list of phandle + reset specifier pairs
> + - reset-names : string reset name, must be:
> +		 "tcphy", "tcphy_pipe", "uphy_tcphy"
> + - #phy-cells : Must be 0.  See ./phy-bindings.txt for details.
> + - extcon : extcon specifier for the Power Delivery
> +
> +Note, there are 2 type-c phys for RK3399, and they are almost identical,
> except +these registers(description below), every register node contains
> 3 sections: +offset, enable bit, write mask bit.
> + - rockchip,typec_conn_dir : the register of type-c connector direction,
> +   for type-c phy0, it must be <0xe580 0 16>;
> +   for type-c phy1, it must be <0xe58c 0 16>;

I think I said this already, but these register-lists would be much happier 
being defined inside the driver - see how Frank managed this on his usb2phy 
please.

Heiko

Re: [v2 PATCH 1/4] Documentation: bindings: add dt doc for Rockchip USB Type-C PHY

[Chris Zhong]

Hi Heiko

On 06/16/2016 06:11 AM, Heiko Stuebner wrote:
> Am Montag, 13. Juni 2016, 17:39:46 schrieb Chris Zhong:
>> This patch adds a binding that describes the Rockchip USB Type-C PHY
>> for rk3399
>>
>> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
>>
>> ---
>>
>> Changes in v2:
>> - add some registers description
>>
>> Changes in v1:
>> - add extcon node description
>> - move the registers in phy driver
>> - remove the suffix of reset
>>
>>   .../devicetree/bindings/phy/phy-rockchip-typec.txt | 77
>> ++++++++++++++++++++++ 1 file changed, 77 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
>> b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt new file
>> mode 100644
>> index 0000000..430920c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
>> @@ -0,0 +1,77 @@
>> +* ROCKCHIP type-c PHY
>> +---------------------
>> +
>> +Required properties:
>> + - compatible : should be "rockchip,rk3399-typec-phy0" or
>> +			 "rockchip,rk3399-typec-phy1"
>> + - reg: Address and length of the usb phy control register set
>> + - rockchip,grf : phandle to the syscon managing the "general
>> +   register files"
>> + - clocks : phandle + clock specifier for the phy clocks
>> + - clock-names : string, clock name, must be "tcpdcore", "tcpdphy_ref";
>> + - resets : a list of phandle + reset specifier pairs
>> + - reset-names : string reset name, must be:
>> +		 "tcphy", "tcphy_pipe", "uphy_tcphy"
>> + - #phy-cells : Must be 0.  See ./phy-bindings.txt for details.
>> + - extcon : extcon specifier for the Power Delivery
>> +
>> +Note, there are 2 type-c phys for RK3399, and they are almost identical,
>> except +these registers(description below), every register node contains
>> 3 sections: +offset, enable bit, write mask bit.
>> + - rockchip,typec_conn_dir : the register of type-c connector direction,
>> +   for type-c phy0, it must be <0xe580 0 16>;
>> +   for type-c phy1, it must be <0xe58c 0 16>;
> I think I said this already, but these register-lists would be much happier
> being defined inside the driver - see how Frank managed this on his usb2phy
> please.
>
> Heiko
>
Yes, I move them into driver in v1 patch, but Rob Herring and Guenter 
Roeck recommend to put them back to dts.
These phy0 and phy1 are exactly the same, except these grf registers.



>

Re: [v2 PATCH 1/4] Documentation: bindings: add dt doc for Rockchip USB Type-C PHY

[Tomasz Figa]

On Thu, Jun 16, 2016 at 9:31 AM, Chris Zhong <zyw@rock-chips.com> wrote:
> Hi Heiko
>
>
> On 06/16/2016 06:11 AM, Heiko Stuebner wrote:
>>
>> Am Montag, 13. Juni 2016, 17:39:46 schrieb Chris Zhong:
>>>
>>> This patch adds a binding that describes the Rockchip USB Type-C PHY
>>> for rk3399
>>>
>>> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
>>>
>>> ---
>>>
>>> Changes in v2:
>>> - add some registers description
>>>
>>> Changes in v1:
>>> - add extcon node description
>>> - move the registers in phy driver
>>> - remove the suffix of reset
>>>
>>>   .../devicetree/bindings/phy/phy-rockchip-typec.txt | 77
>>> ++++++++++++++++++++++ 1 file changed, 77 insertions(+)
>>>   create mode 100644
>>> Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
>>> b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt new file
>>> mode 100644
>>> index 0000000..430920c
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
>>> @@ -0,0 +1,77 @@
>>> +* ROCKCHIP type-c PHY
>>> +---------------------
>>> +
>>> +Required properties:
>>> + - compatible : should be "rockchip,rk3399-typec-phy0" or
>>> +                        "rockchip,rk3399-typec-phy1"
>>> + - reg: Address and length of the usb phy control register set
>>> + - rockchip,grf : phandle to the syscon managing the "general
>>> +   register files"
>>> + - clocks : phandle + clock specifier for the phy clocks
>>> + - clock-names : string, clock name, must be "tcpdcore", "tcpdphy_ref";
>>> + - resets : a list of phandle + reset specifier pairs
>>> + - reset-names : string reset name, must be:
>>> +                "tcphy", "tcphy_pipe", "uphy_tcphy"
>>> + - #phy-cells : Must be 0.  See ./phy-bindings.txt for details.
>>> + - extcon : extcon specifier for the Power Delivery
>>> +
>>> +Note, there are 2 type-c phys for RK3399, and they are almost identical,
>>> except +these registers(description below), every register node contains
>>> 3 sections: +offset, enable bit, write mask bit.
>>> + - rockchip,typec_conn_dir : the register of type-c connector direction,
>>> +   for type-c phy0, it must be <0xe580 0 16>;
>>> +   for type-c phy1, it must be <0xe58c 0 16>;
>>
>> I think I said this already, but these register-lists would be much
>> happier
>> being defined inside the driver - see how Frank managed this on his
>> usb2phy
>> please.
>>
>> Heiko
>>
> Yes, I move them into driver in v1 patch, but Rob Herring and Guenter Roeck
> recommend to put them back to dts.
> These phy0 and phy1 are exactly the same, except these grf registers.

I think having the registers in dts isn't a bad idea. It might be
actually even useful to bring up this PHY on new SoCs, if they happen
to have the same PHY, just different plumbing.

But I suppose we don't need two separate compatible strings for phy0
and phy1 anymore as Rob pointed, just one "rockchip,rk3399-typec-phy".

After the above is fixed and underscores in property names are
replaced with dashes, feel free to add my Reviewed-by.

Best regards,
Tomasz

Re: [v2 PATCH 1/4] Documentation: bindings: add dt doc for Rockchip USB Type-C PHY

[Heiko Stübner]

Am Donnerstag, 16. Juni 2016, 16:49:42 schrieb Tomasz Figa:
> On Thu, Jun 16, 2016 at 9:31 AM, Chris Zhong <zyw@rock-chips.com> wrote:
> > Hi Heiko
> > 
> > On 06/16/2016 06:11 AM, Heiko Stuebner wrote:
> >> Am Montag, 13. Juni 2016, 17:39:46 schrieb Chris Zhong:
> >>> This patch adds a binding that describes the Rockchip USB Type-C PHY
> >>> for rk3399
> >>> 
> >>> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> >>> 
> >>> ---
> >>> 
> >>> Changes in v2:
> >>> - add some registers description
> >>> 
> >>> Changes in v1:
> >>> - add extcon node description
> >>> - move the registers in phy driver
> >>> - remove the suffix of reset
> >>> 
> >>>   .../devicetree/bindings/phy/phy-rockchip-typec.txt | 77
> >>> 
> >>> ++++++++++++++++++++++ 1 file changed, 77 insertions(+)
> >>> 
> >>>   create mode 100644
> >>> 
> >>> Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> >>> 
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> >>> b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt new file
> >>> mode 100644
> >>> index 0000000..430920c
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> >>> @@ -0,0 +1,77 @@
> >>> +* ROCKCHIP type-c PHY
> >>> +---------------------
> >>> +
> >>> +Required properties:
> >>> + - compatible : should be "rockchip,rk3399-typec-phy0" or
> >>> +                        "rockchip,rk3399-typec-phy1"
> >>> + - reg: Address and length of the usb phy control register set
> >>> + - rockchip,grf : phandle to the syscon managing the "general
> >>> +   register files"
> >>> + - clocks : phandle + clock specifier for the phy clocks
> >>> + - clock-names : string, clock name, must be "tcpdcore", "tcpdphy_ref";
> >>> + - resets : a list of phandle + reset specifier pairs
> >>> + - reset-names : string reset name, must be:
> >>> +                "tcphy", "tcphy_pipe", "uphy_tcphy"
> >>> + - #phy-cells : Must be 0.  See ./phy-bindings.txt for details.
> >>> + - extcon : extcon specifier for the Power Delivery
> >>> +
> >>> +Note, there are 2 type-c phys for RK3399, and they are almost
> >>> identical,
> >>> except +these registers(description below), every register node contains
> >>> 3 sections: +offset, enable bit, write mask bit.
> >>> + - rockchip,typec_conn_dir : the register of type-c connector
> >>> direction,
> >>> +   for type-c phy0, it must be <0xe580 0 16>;
> >>> +   for type-c phy1, it must be <0xe58c 0 16>;
> >> 
> >> I think I said this already, but these register-lists would be much
> >> happier
> >> being defined inside the driver - see how Frank managed this on his
> >> usb2phy
> >> please.
> >> 
> >> Heiko
> > 
> > Yes, I move them into driver in v1 patch, but Rob Herring and Guenter
> > Roeck
> > recommend to put them back to dts.
> > These phy0 and phy1 are exactly the same, except these grf registers.
> 
> I think having the registers in dts isn't a bad idea. It might be
> actually even useful to bring up this PHY on new SoCs, if they happen
> to have the same PHY, just different plumbing.
> 
> But I suppose we don't need two separate compatible strings for phy0
> and phy1 anymore as Rob pointed, just one "rockchip,rk3399-typec-phy".

That is true - so I guess I'm also ok with going that way.

Though with the GRF-based interfaces being as volatile as they are between soc 
types, I just fear that this might not hold up on future socs.
For example the usb2phy is used on rk3036, rk3228, rk3366, rk3368, rk3399 and 
the GRF-side differs a lot - even with some features not even supported.

> After the above is fixed and underscores in property names are
> replaced with dashes, feel free to add my Reviewed-by.

I guess the clock and reset-names could also use dashes instead of 
underscores.

Re: [v2 PATCH 1/4] Documentation: bindings: add dt doc for Rockchip USB Type-C PHY

[Kever Yang]

Hi Chris,

On 06/13/2016 05:39 PM, Chris Zhong wrote:
> This patch adds a binding that describes the Rockchip USB Type-C PHY
> for rk3399
>
> Signed-off-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>
> ---
>
> Changes in v2:
> - add some registers description
>
> Changes in v1:
> - add extcon node description
> - move the registers in phy driver
> - remove the suffix of reset
>
>   .../devicetree/bindings/phy/phy-rockchip-typec.txt | 77 ++++++++++++++++++++++
>   1 file changed, 77 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> new file mode 100644
> index 0000000..430920c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> @@ -0,0 +1,77 @@
> +* ROCKCHIP type-c PHY
> +---------------------
> +
> +Required properties:
> + - compatible : should be "rockchip,rk3399-typec-phy0" or
> +			 "rockchip,rk3399-typec-phy1"
should be "rockchip,rk3399-typec-phy"
> + - reg: Address and length of the usb phy control register set
> + - rockchip,grf : phandle to the syscon managing the "general
> +   register files"
> + - clocks : phandle + clock specifier for the phy clocks
> + - clock-names : string, clock name, must be "tcpdcore", "tcpdphy_ref";
> + - resets : a list of phandle + reset specifier pairs
> + - reset-names : string reset name, must be:
> +		 "tcphy", "tcphy_pipe", "uphy_tcphy"
> + - #phy-cells : Must be 0.  See ./phy-bindings.txt for details.
> + - extcon : extcon specifier for the Power Delivery
> +
> +Note, there are 2 type-c phys for RK3399, and they are almost identical, except
> +these registers(description below), every register node contains 3 sections:
> +offset, enable bit, write mask bit.
> + - rockchip,typec_conn_dir : the register of type-c connector direction,
> +   for type-c phy0, it must be <0xe580 0 16>;
> +   for type-c phy1, it must be <0xe58c 0 16>;
> + - rockchip,usb3tousb2_en : the register of type-c force usb3 to usb2 enable
> +   control.
> +   for type-c phy0, it must be <0xe580 3 19>;
> +   for type-c phy1, it must be <0xe58c 3 19>;
> + - rockchip,external_psm : the register of type-c phy external psm clock
> +   selection.
> +   for type-c phy0, it must be <0xe588 14 30>;
> +   for type-c phy1, it must be <0xe594 14 30>;
> + - rockchip,pipe_status : the register of type-c phy pipe status.
> +   for type-c phy0, it must be <0xe5c0 0 0>;
> +   for type-c phy1, it must be <0xe5c0 16 16>;
> + - rockchip,uphy_dp_sel : the register of type-c phy selection for DP
> +   for type-c phy0, it must be <0x6268 19 19>;
> +   for type-c phy1, it must be <0x6268 3 19>;
> +
> +Example:
> +	tcphy0: phy@ff7c0000 {
> +		compatible = "rockchip,rk3399-typec-phy0";
should be "rockchip,rk3399-typec-phy"
> +		reg = <0x0 0xff7c0000 0x0 0x40000>;
> +		#phy-cells = <0>;
> +		extcon = <&fusb1>;
> +		rockchip,grf = <&grf>;
> +		clocks = <&cru SCLK_UPHY0_TCPDCORE>,
> +			 <&cru SCLK_UPHY0_TCPDPHY_REF>;
> +		clock-names = "tcpdcore", "tcpdphy_ref";
> +		resets = <&cru SRST_UPHY0>,
> +			 <&cru SRST_UPHY0_PIPE_L00>,
> +			 <&cru SRST_P_UPHY0_TCPHY>;
> +		reset-names = "tcphy", "tcphy_pipe", "uphy_tcphy";
> +		rockchip,typec_conn_dir = <0xe580 0 16>;
> +		rockchip,usb3tousb2_en = <0xe580 3 19>;
> +		rockchip,external_psm = <0xe588 14 30>;
> +		rockchip,pipe_status = <0xe5c0 0 0>;
> +		rockchip,uphy_dp_sel = <0x6268 19 19>;
> +	};
> +
> +	tcphy1: phy@ff800000 {
> +		compatible = "rockchip,rk3399-typec-phy1";
should be "rockchip,rk3399-typec-phy"

Feel free to ad my Reviewed-by after these update.

Thanks,
- Kever
> +		reg = <0x0 0xff800000 0x0 0x40000>;
> +		#phy-cells = <0>;
> +		rockchip,grf = <&grf>;
> +		clocks = <&cru SCLK_UPHY1_TCPDCORE>,
> +			 <&cru SCLK_UPHY1_TCPDPHY_REF>;
> +		clock-names = "tcpdcore", "tcpdphy_ref";
> +		resets = <&cru SRST_UPHY1>,
> +		         <&cru SRST_UPHY1_PIPE_L00>,
> +			 <&cru SRST_P_UPHY1_TCPHY>;
> +		reset-names = "tcphy", "tcphy_pipe", "uphy_tcphy";
> +		rockchip,typec_conn_dir = <0xe58c 0 16>;
> +		rockchip,usb3tousb2_en = <0xe58c 3 19>;
> +		rockchip,external_psm = <0xe594 14 30>;
> +		rockchip,pipe_status = <0xe5c0 16 16>;
> +		rockchip,uphy_dp_sel = <0x6268 3 19>;
> +	};