From mboxrd@z Thu Jan 1 00:00:00 1970 From: Juri Lelli Subject: [PATCH v5 5/8] arm64, dts: add Juno cpu capacity-dmips-mhz information Date: Wed, 15 Jun 2016 11:17:54 +0100 Message-ID: <1465985877-18271-6-git-send-email-juri.lelli@arm.com> References: <1465985877-18271-1-git-send-email-juri.lelli@arm.com> Return-path: In-Reply-To: <1465985877-18271-1-git-send-email-juri.lelli@arm.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-kernel@vger.kernel.org Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, peterz@infradead.org, vincent.guittot@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, linux@arm.linux.org.uk, sudeep.holla@arm.com, lorenzo.pieralisi@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, morten.rasmussen@arm.com, dietmar.eggemann@arm.com, juri.lelli@arm.com, broonie@kernel.org, sgurrappadi@nvidia.com, Pawel Moll , Ian Campbell , Kumar Gala , Liviu Dudau , Arnd Bergmann , Jon Medhurst , Olof Johansson , Robin Murphy List-Id: devicetree@vger.kernel.org Add Juno cpu capacity-dmips-mhz bindings information. Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Catalin Marinas Cc: Will Deacon Cc: Liviu Dudau Cc: Sudeep Holla Cc: Arnd Bergmann Cc: Jon Medhurst Cc: Olof Johansson Cc: Robin Murphy Cc: devicetree@vger.kernel.org Signed-off-by: Juri Lelli --- Changes from v1: - capacity-scale removed Changes from v4: - binding changed to capacity-dmips-mhz --- arch/arm64/boot/dts/arm/juno.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index dcfcf15..ad07815 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -90,6 +90,7 @@ next-level-cache = <&A57_L2>; clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; }; A57_1: cpu@1 { @@ -100,6 +101,7 @@ next-level-cache = <&A57_L2>; clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; }; A53_0: cpu@100 { @@ -110,6 +112,7 @@ next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; }; A53_1: cpu@101 { @@ -120,6 +123,7 @@ next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; }; A53_2: cpu@102 { @@ -130,6 +134,7 @@ next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; }; A53_3: cpu@103 { @@ -140,6 +145,7 @@ next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; }; A57_L2: l2-cache0 { -- 2.7.0