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Subject: [PATCHv1] Add Intel Stratix10 service layer binding
Date: Tue, 23 Jan 2018 13:25:01 -0600	[thread overview]
Message-ID: <> (raw)

From: Richard Gong <>

Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
configured from HPS, there needs to be a way for HPS to notify SDM the
location and size of the configuration data. Then SDM will get the
configuration data from that location and perform the FPGA configuration.

To meet the whole system security needs and support virtual machine requesting
communication with SDM, only the secure world of software (EL3, Exception
Layer 3) can interface with SDM. All software entities running on other
exception layers must channel through the EL3 software whenever it needs
service from SDM.

Intel Stratix10 service layer driver, running at privileged exception level
(EL1, Exception Layer 1), interfaces with the service providers and provides
the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
driver also manages secure monitor call (SMC) to communicate with secure monitor
code running in EL3.

This patch adds a device tree binding for Intel Stratix10 service layer driver

Richard Gong (1):
  dt-bindings: misc: add Intel Stratix10 service layer binding

 .../devicetree/bindings/misc/intel-service.txt     | 56 ++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/intel-service.txt


             reply	other threads:[~2018-01-23 19:25 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-23 19:25 richard.gong [this message]
2018-01-23 19:25 ` [PATCHv1] dt-bindings: misc: add Intel Stratix10 service layer binding richard.gong
2018-01-30 16:57   ` Rob Herring
2018-02-01 16:26     ` Richard Gong

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