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Tue, 12 Nov 2019 05:17:14 -0800 Received: from xsj-pvapsmtp01 (maildrop.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id xACDH6lG022526; Tue, 12 Nov 2019 05:17:07 -0800 Received: from [172.19.2.91] (helo=xsjjollys50.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iUW2c-0004Ds-P0; Tue, 12 Nov 2019 05:17:06 -0800 From: Rajan Vaja To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com, m.tretter@pengutronix.de, jolly.shah@xilinx.com, dan.carpenter@oracle.com, gustavo@embeddedor.com, tejas.patel@xilinx.com, nava.manne@xilinx.com, ravi.patel@xilinx.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Radhey Shyam Pandey , Rajan Vaja Subject: [PATCH 6/7] clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag Date: Tue, 12 Nov 2019 05:16:19 -0800 Message-Id: <1573564580-9006-7-git-send-email-rajan.vaja@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573564580-9006-1-git-send-email-rajan.vaja@xilinx.com> References: <1573564580-9006-1-git-send-email-rajan.vaja@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(376002)(396003)(136003)(39860400002)(346002)(199004)(189003)(50226002)(81156014)(9786002)(50466002)(186003)(11346002)(446003)(2616005)(486006)(126002)(476003)(426003)(336012)(26005)(8936002)(81166006)(8676002)(48376002)(70586007)(36386004)(4326008)(70206006)(356004)(7696005)(6666004)(51416003)(36756003)(107886003)(106002)(76176011)(16586007)(316002)(6636002)(54906003)(478600001)(2906002)(7416002)(305945005)(44832011)(5660300002)(47776003)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR02MB5180;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;A:1;MX:1; MIME-Version: 1.0 Content-Type: text/plain X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 64ca7f2a-38db-4dde-4c72-08d76772a612 X-MS-TrafficTypeDiagnostic: DM6PR02MB5180: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:1186; X-Forefront-PRVS: 021975AE46 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +PG7LSlqBANqo0T68T1kDibIsVt5tyJTPGAjid3YRleze+uZj7MLcb+4dUgU3UF0XQwsjR3hIdCrYofHzPzpBR94OfMVZuDGUVr9pFwg7GaujHvuGN/XBZirALyTYhSzNIDcoNqGmc5RkEWxSyzIsl8/SmqGrAlBk5A3lYDASMAL51VCUW/Pyxq6kk5q9pti4/E3mA5P3wEkg1TOvkI4yxyeXNGIP4MmRUOTf+CRLsz12RxrHZ2M11xb3JjPGNgSPm/wIhzgQxNZm3uUbJ4UoQc9KcB+eIsW+r+1Rf8l20/5felEPZkKR24WjVomPpDwNzfROsk4oR/IS4OXxkA4148ve/d1VPw3jdS4HfqBEgETrH3BUCMhunAULh9Oa7hb/1xYOFMndEdvfY75aHMyx7ByzinHMFLVGzFN5veXbFmQwm7qdYnfyCjn2jOXWRh+ X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2019 13:17:20.3972 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64ca7f2a-38db-4dde-4c72-08d76772a612 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Tejas Patel Existing clock divider functions is not checking for base of divider. So, if any clock divider is power of 2 then clock rate calculation will be wrong. Add support to calculate divider value for the clocks with CLK_DIVIDER_POWER_OF_TWO flag. Signed-off-by: Tejas Patel Signed-off-by: Radhey Shyam Pandey Signed-off-by: Rajan Vaja --- drivers/clk/zynqmp/divider.c | 36 +++++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index b564696..67aa88c 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -2,7 +2,7 @@ /* * Zynq UltraScale+ MPSoC Divider support * - * Copyright (C) 2016-2018 Xilinx + * Copyright (C) 2016-2019 Xilinx * * Adjustable divider clock implementation */ @@ -45,9 +45,26 @@ struct zynqmp_clk_divider { }; static inline int zynqmp_divider_get_val(unsigned long parent_rate, - unsigned long rate) + unsigned long rate, u16 flags) { - return DIV_ROUND_CLOSEST(parent_rate, rate); + int up, down; + unsigned long up_rate, down_rate; + + if (flags & CLK_DIVIDER_POWER_OF_TWO) { + up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); + down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate); + + up = __roundup_pow_of_two(up); + down = __rounddown_pow_of_two(down); + + up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up); + down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down); + + return (rate - up_rate) <= (down_rate - rate) ? up : down; + + } else { + return DIV_ROUND_CLOSEST(parent_rate, rate); + } } /** @@ -79,6 +96,9 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, else value = div >> 16; + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + value = 1 << value; + if (!value) { WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", @@ -157,10 +177,13 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, else bestdiv = bestdiv >> 16; + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + bestdiv = 1 << bestdiv; + return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); } - bestdiv = zynqmp_divider_get_val(*prate, rate); + bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags); /* * In case of two divisors, compute best divider values and return @@ -198,7 +221,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, int ret; const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - value = zynqmp_divider_get_val(parent_rate, rate); + value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); if (div_type == TYPE_DIV1) { div = value & 0xFFFF; div |= 0xffff << 16; @@ -207,6 +230,9 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, div |= value << 16; } + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + div = __ffs(div); + ret = eemi_ops->clock_setdivider(clk_id, div); if (ret) -- 2.7.4