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Mon, 02 Dec 2019 20:57:51 -0800 (PST) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id k4sm1667807wmk.26.2019.12.02.20.57.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Dec 2019 20:57:50 -0800 (PST) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v3 4/6] arm: dts: Change PCIe INTx mapping for NSP Date: Tue, 3 Dec 2019 10:27:04 +0530 Message-Id: <1575349026-8743-5-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> References: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ray Jui Change the PCIe INTx mapping to model the 4 INTx interrupts in the IRQ domain of the iProc PCIe controller itself Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- arch/arm/boot/dts/bcm-nsp.dtsi | 45 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index da6d70f..6d73221 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -529,8 +529,11 @@ reg = <0x18012000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -559,6 +562,14 @@ ; brcm,pcie-msi-inten; }; + + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie1: pcie@18013000 { @@ -566,8 +577,11 @@ reg = <0x18013000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; linux,pci-domain = <1>; @@ -596,6 +610,14 @@ ; brcm,pcie-msi-inten; }; + + pcie1_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie2: pcie@18014000 { @@ -603,8 +625,11 @@ reg = <0x18014000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; linux,pci-domain = <2>; @@ -633,6 +658,14 @@ ; brcm,pcie-msi-inten; }; + + pcie2_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; thermal-zones { -- 2.7.4