* [PATCH v2] memory: mtk-smi: Add bandwidth initial setting for MT6779
@ 2019-12-09 6:19 Ming-Fan Chen
2019-12-09 6:19 ` [PATCH v2 0/2] " Ming-Fan Chen
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Ming-Fan Chen @ 2019-12-09 6:19 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger
Cc: Yong Wu, Evan Green, Joerg Roedel, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, wsd_upstream
This patch add description and bandwidth initial golden setting for MT6779 SMI.
The setting make better performance of memory control for multimedia modules.
changelog since v1:
-add description of GALS for mt6779 into smi-common documentation
-remove unused define
-rename structure member to correspond to related registers
-replace pointer of array with single pointer to reduce intention
Ming-Fan Chen (2):
dt-bindings: mediatek: Add binding for MT6779 SMI
memory: mtk-smi: Add bandwidth initial golden setting for MT6779
.../memory-controllers/mediatek,smi-common.txt | 5 +-
.../memory-controllers/mediatek,smi-larb.txt | 3 +-
drivers/memory/mtk-smi.c | 143 +++++++++++++++++++-
3 files changed, 147 insertions(+), 4 deletions(-)
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 0/2] memory: mtk-smi: Add bandwidth initial setting for MT6779 2019-12-09 6:19 [PATCH v2] memory: mtk-smi: Add bandwidth initial setting for MT6779 Ming-Fan Chen @ 2019-12-09 6:19 ` Ming-Fan Chen 2019-12-09 6:19 ` [PATCH v2 1/2] dt-bindings: mediatek: Add binding for MT6779 SMI Ming-Fan Chen 2019-12-09 6:19 ` [PATCH v2 2/2] memory: mtk-smi: Add bandwidth initial golden setting for MT6779 Ming-Fan Chen 2 siblings, 0 replies; 6+ messages in thread From: Ming-Fan Chen @ 2019-12-09 6:19 UTC (permalink / raw) To: Rob Herring, Matthias Brugger Cc: Yong Wu, Evan Green, Joerg Roedel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, wsd_upstream, Ming-Fan Chen *** BLURB HERE *** Ming-Fan Chen (2): dt-bindings: mediatek: Add binding for MT6779 SMI memory: mtk-smi: Add bandwidth initial golden setting for MT6779 .../memory-controllers/mediatek,smi-common.txt | 5 +- .../memory-controllers/mediatek,smi-larb.txt | 3 +- drivers/memory/mtk-smi.c | 143 +++++++++++++++++++- 3 files changed, 147 insertions(+), 4 deletions(-) -- 1.7.9.5 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/2] dt-bindings: mediatek: Add binding for MT6779 SMI 2019-12-09 6:19 [PATCH v2] memory: mtk-smi: Add bandwidth initial setting for MT6779 Ming-Fan Chen 2019-12-09 6:19 ` [PATCH v2 0/2] " Ming-Fan Chen @ 2019-12-09 6:19 ` Ming-Fan Chen 2019-12-13 19:10 ` Rob Herring 2019-12-09 6:19 ` [PATCH v2 2/2] memory: mtk-smi: Add bandwidth initial golden setting for MT6779 Ming-Fan Chen 2 siblings, 1 reply; 6+ messages in thread From: Ming-Fan Chen @ 2019-12-09 6:19 UTC (permalink / raw) To: Rob Herring, Matthias Brugger Cc: Yong Wu, Evan Green, Joerg Roedel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, wsd_upstream, Ming-Fan Chen This patch add description for MT6779 SMI. Signed-off-by: Ming-Fan Chen <ming-fan.chen@mediatek.com> --- .../memory-controllers/mediatek,smi-common.txt | 5 +++-- .../memory-controllers/mediatek,smi-larb.txt | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt index b478ade..b645736 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt @@ -5,7 +5,7 @@ The hardware block diagram please check bindings/iommu/mediatek,iommu.txt Mediatek SMI have two generations of HW architecture, here is the list which generation the SoCs use: generation 1: mt2701 and mt7623. -generation 2: mt2712, mt8173 and mt8183. +generation 2: mt2712, mt6779, mt8173 and mt8183. There's slight differences between the two SMI, for generation 2, the register which control the iommu port is at each larb's register base. But @@ -18,6 +18,7 @@ Required properties: - compatible : must be one of : "mediatek,mt2701-smi-common" "mediatek,mt2712-smi-common" + "mediatek,mt6779-smi-common" "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common" "mediatek,mt8173-smi-common" "mediatek,mt8183-smi-common" @@ -35,7 +36,7 @@ Required properties: and these 2 option clocks for generation 2 smi HW: - "gals0": the path0 clock of GALS(Global Async Local Sync). - "gals1": the path1 clock of GALS(Global Async Local Sync). - Here is the list which has this GALS: mt8183. + Here is the list which has this GALS: mt6779 and mt8183. Example: smi_common: smi@14022000 { diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt index 4b369b3..8f19dfe 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt @@ -6,6 +6,7 @@ Required properties: - compatible : must be one of : "mediatek,mt2701-smi-larb" "mediatek,mt2712-smi-larb" + "mediatek,mt6779-smi-larb" "mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb" "mediatek,mt8173-smi-larb" "mediatek,mt8183-smi-larb" @@ -21,7 +22,7 @@ Required properties: - "gals": the clock for GALS(Global Async Local Sync). Here is the list which has this GALS: mt8183. -Required property for mt2701, mt2712 and mt7623: +Required property for mt2701, mt2712, mt6779 and mt7623: - mediatek,larb-id :the hardware id of this larb. Example: -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: mediatek: Add binding for MT6779 SMI 2019-12-09 6:19 ` [PATCH v2 1/2] dt-bindings: mediatek: Add binding for MT6779 SMI Ming-Fan Chen @ 2019-12-13 19:10 ` Rob Herring 0 siblings, 0 replies; 6+ messages in thread From: Rob Herring @ 2019-12-13 19:10 UTC (permalink / raw) To: Ming-Fan Chen Cc: Matthias Brugger, Yong Wu, Evan Green, Joerg Roedel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, wsd_upstream, Ming-Fan Chen On Mon, 9 Dec 2019 14:19:30 +0800, Ming-Fan Chen wrote: > This patch add description for MT6779 SMI. > > Signed-off-by: Ming-Fan Chen <ming-fan.chen@mediatek.com> > --- > .../memory-controllers/mediatek,smi-common.txt | 5 +++-- > .../memory-controllers/mediatek,smi-larb.txt | 3 ++- > 2 files changed, 5 insertions(+), 3 deletions(-) > Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply. If a tag was not added on purpose, please state why and what changed. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] memory: mtk-smi: Add bandwidth initial golden setting for MT6779 2019-12-09 6:19 [PATCH v2] memory: mtk-smi: Add bandwidth initial setting for MT6779 Ming-Fan Chen 2019-12-09 6:19 ` [PATCH v2 0/2] " Ming-Fan Chen 2019-12-09 6:19 ` [PATCH v2 1/2] dt-bindings: mediatek: Add binding for MT6779 SMI Ming-Fan Chen @ 2019-12-09 6:19 ` Ming-Fan Chen 2019-12-27 7:21 ` Yong Wu 2 siblings, 1 reply; 6+ messages in thread From: Ming-Fan Chen @ 2019-12-09 6:19 UTC (permalink / raw) To: Rob Herring, Matthias Brugger Cc: Yong Wu, Evan Green, Joerg Roedel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, wsd_upstream, Ming-Fan Chen SMI bandwidth initial golden setting for MT6779 make sure better performance of memory control for multimedia modules. Signed-off-by: Ming-Fan Chen <ming-fan.chen@mediatek.com> --- drivers/memory/mtk-smi.c | 143 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 142 insertions(+), 1 deletion(-) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index 439d7d8..6b18b71 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -41,21 +41,49 @@ #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) #define F_MMU_EN BIT(0) +#define SMI_LARB_CMD_THRT_CON 0x24 +#define SMI_LARB_SW_FLAG 0x40 +#define SMI_LARB_OSTDL_PORT 0x200 +#define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) + /* SMI COMMON */ +#define SMI_L1LEN 0x100 +#define SMI_L1ARB0 0x104 +#define SMI_L1ARB(id) (SMI_L1ARB0 + (((id) & 0x7) << 2)) + #define SMI_BUS_SEL 0x220 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) /* All are MMU0 defaultly. Only specialize mmu1 here. */ #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) +#define SMI_M4U_TH 0x234 +#define SMI_FIFO_TH1 0x238 +#define SMI_FIFO_TH2 0x23c +#define SMI_DCM 0x300 +#define SMI_DUMMY 0x444 + +#define SMI_LARB_PORT_NR_MAX 32 +#define SMI_LARB_MISC_NR 2 +#define SMI_COMMON_MISC_NR 6 + enum mtk_smi_gen { MTK_SMI_GEN1, MTK_SMI_GEN2 }; +struct mtk_smi_reg_pair { + u16 offset; + u32 value; +}; + struct mtk_smi_common_plat { enum mtk_smi_gen gen; bool has_gals; u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ + bool has_bwc; + u8 larb_nr; + const u16 *l1arb; + const struct mtk_smi_reg_pair *misc; }; struct mtk_smi_larb_gen { @@ -63,6 +91,9 @@ struct mtk_smi_larb_gen { void (*config_port)(struct device *); unsigned int larb_direct_to_common_mask; bool has_gals; + bool has_bwc; + const u8 (*ostdl)[SMI_LARB_PORT_NR_MAX]; + const struct mtk_smi_reg_pair (*misc)[SMI_LARB_MISC_NR]; }; struct mtk_smi { @@ -161,6 +192,8 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) struct mtk_smi_larb *larb = dev_get_drvdata(dev); u32 reg; int i; + const u8 *ostdl; + const struct mtk_smi_reg_pair *misc; if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) return; @@ -170,6 +203,20 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) reg |= F_MMU_EN; writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); } + + if (!larb->larb_gen->has_bwc) + return; + + for (i = 0, ostdl = larb->larb_gen->ostdl[larb->larbid]; + i < SMI_LARB_PORT_NR_MAX; i++) + writel_relaxed(ostdl[i], + larb->base + SMI_LARB_OSTDL_PORTx(i)); + + for (i = 0, misc = larb->larb_gen->misc[larb->larbid]; + i < SMI_LARB_MISC_NR; i++) + writel_relaxed(misc[i].value, + larb->base + misc[i].offset); + wmb(); /* make sure settings are written */ } static void mtk_smi_larb_config_port_mt8173(struct device *dev) @@ -239,6 +286,55 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ }; +static const u8 mtk_smi_larb_mt6779_ostdl[][SMI_LARB_PORT_NR_MAX] = { + {0x28, 0x28, 0x01, 0x28, 0x01, 0x01, 0x0a, 0x0a, 0x28,}, + {0x28, 0x01, 0x28, 0x28, 0x0a, 0x01, 0x01, 0x0d, 0x0d, 0x07, + 0x01, 0x07, 0x01, 0x28,}, + {0x18, 0x01, 0x08, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, + 0x01, 0x01}, + {0x01, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01, 0x04, 0x02, 0x01, + 0x04, 0x01, 0x01, 0x01, 0x01, 0x04, 0x0b, 0x13, 0x14,}, + {}, + {0x13, 0x0f, 0x0d, 0x07, 0x07, 0x04, 0x03, 0x01, 0x03, 0x01, + 0x05, 0x0c, 0x01, 0x01, 0x08, 0x06, 0x02, 0x01, 0x08, 0x08, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,}, + {0x01, 0x01, 0x01,}, + {0x01, 0x01, 0x01, 0x01,}, + {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,}, + {0x1f, 0x1a, 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x1f, 0x04, + 0x04, 0x01, 0x01, 0x01, 0x02, 0x02, 0x04, 0x02, 0x01, 0x02, + 0x04, 0x02, 0x02, 0x01,}, + {0x1f, 0x1a, 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x1f, 0x1a, + 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x01, 0x02, 0x02, 0x04, + 0x02, 0x0a, 0x02, 0x02, 0x04, 0x02, 0x0a, 0x02, 0x04, 0x02, 0x04,}, + {0x01, 0x01, 0x01, 0x01, 0x01,}, +}; + +static const struct mtk_smi_reg_pair +mtk_smi_larb_mt6779_misc[][SMI_LARB_MISC_NR] = { + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, + {}, + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, +}; + +static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { + .config_port = mtk_smi_larb_config_port_gen2_general, + .larb_direct_to_common_mask = + BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), + /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ + .has_bwc = true, + .ostdl = mtk_smi_larb_mt6779_ostdl, + .misc = mtk_smi_larb_mt6779_misc, +}; + static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { .has_gals = true, .config_port = mtk_smi_larb_config_port_gen2_general, @@ -260,6 +356,10 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) .data = &mtk_smi_larb_mt2712 }, { + .compatible = "mediatek,mt6779-smi-larb", + .data = &mtk_smi_larb_mt6779 + }, + { .compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183 }, @@ -386,6 +486,31 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) .gen = MTK_SMI_GEN2, }; +static const u16 mtk_smi_common_mt6779_l1arb[] = { + 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, +}; + +static const struct +mtk_smi_reg_pair mtk_smi_common_mt6779_misc[SMI_COMMON_MISC_NR] = { + {SMI_L1LEN, 0xb}, + {SMI_M4U_TH, 0xe100e10}, + {SMI_FIFO_TH1, 0x506090a}, + {SMI_FIFO_TH2, 0x506090a}, + {SMI_DCM, 0x4f1}, + {SMI_DUMMY, 0x1}, +}; + +static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { + .gen = MTK_SMI_GEN2, + .has_gals = true, + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | + F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), + .has_bwc = true, + .larb_nr = ARRAY_SIZE(mtk_smi_common_mt6779_l1arb), + .l1arb = mtk_smi_common_mt6779_l1arb, + .misc = mtk_smi_common_mt6779_misc, +}; + static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { .gen = MTK_SMI_GEN2, .has_gals = true, @@ -407,6 +532,10 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) .data = &mtk_smi_common_gen2, }, { + .compatible = "mediatek,mt6779-smi-common", + .data = &mtk_smi_common_mt6779, + }, + { .compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183, }, @@ -484,7 +613,7 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) { struct mtk_smi *common = dev_get_drvdata(dev); u32 bus_sel = common->plat->bus_sel; - int ret; + int i, ret; ret = mtk_smi_clk_enable(common); if (ret) { @@ -494,6 +623,18 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) if (common->plat->gen == MTK_SMI_GEN2 && bus_sel) writel(bus_sel, common->base + SMI_BUS_SEL); + + if (!common->plat->has_bwc) + return 0; + + for (i = 0; i < common->plat->larb_nr; i++) + writel_relaxed(common->plat->l1arb[i], + common->base + SMI_L1ARB(i)); + + for (i = 0; i < SMI_COMMON_MISC_NR; i++) + writel_relaxed(common->plat->misc[i].value, + common->base + common->plat->misc[i].value); + wmb(); /* make sure settings are written */ return 0; } -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] memory: mtk-smi: Add bandwidth initial golden setting for MT6779 2019-12-09 6:19 ` [PATCH v2 2/2] memory: mtk-smi: Add bandwidth initial golden setting for MT6779 Ming-Fan Chen @ 2019-12-27 7:21 ` Yong Wu 0 siblings, 0 replies; 6+ messages in thread From: Yong Wu @ 2019-12-27 7:21 UTC (permalink / raw) To: Ming-Fan Chen Cc: Rob Herring, Matthias Brugger, Evan Green, Joerg Roedel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, wsd_upstream On Mon, 2019-12-09 at 14:19 +0800, Ming-Fan Chen wrote: > SMI bandwidth initial golden setting for MT6779 make sure > better performance of memory control for multimedia modules. > > Signed-off-by: Ming-Fan Chen <ming-fan.chen@mediatek.com> > --- > drivers/memory/mtk-smi.c | 143 +++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 142 insertions(+), 1 deletion(-) > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > index 439d7d8..6b18b71 100644 > --- a/drivers/memory/mtk-smi.c > +++ b/drivers/memory/mtk-smi.c > @@ -41,21 +41,49 @@ > #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) > #define F_MMU_EN BIT(0) > > +#define SMI_LARB_CMD_THRT_CON 0x24 > +#define SMI_LARB_SW_FLAG 0x40 > +#define SMI_LARB_OSTDL_PORT 0x200 > +#define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) > + > /* SMI COMMON */ > +#define SMI_L1LEN 0x100 > +#define SMI_L1ARB0 0x104 > +#define SMI_L1ARB(id) (SMI_L1ARB0 + (((id) & 0x7) << 2)) > + > #define SMI_BUS_SEL 0x220 > #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) > /* All are MMU0 defaultly. Only specialize mmu1 here. */ > #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) > > +#define SMI_M4U_TH 0x234 > +#define SMI_FIFO_TH1 0x238 > +#define SMI_FIFO_TH2 0x23c > +#define SMI_DCM 0x300 > +#define SMI_DUMMY 0x444 > + > +#define SMI_LARB_PORT_NR_MAX 32 > +#define SMI_LARB_MISC_NR 2 > +#define SMI_COMMON_MISC_NR 6 > + > enum mtk_smi_gen { > MTK_SMI_GEN1, > MTK_SMI_GEN2 > }; > > +struct mtk_smi_reg_pair { > + u16 offset; > + u32 value; > +}; > + > struct mtk_smi_common_plat { > enum mtk_smi_gen gen; > bool has_gals; > u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ > + bool has_bwc; > + u8 larb_nr; > + const u16 *l1arb; > + const struct mtk_smi_reg_pair *misc; > }; > > struct mtk_smi_larb_gen { > @@ -63,6 +91,9 @@ struct mtk_smi_larb_gen { > void (*config_port)(struct device *); > unsigned int larb_direct_to_common_mask; > bool has_gals; > + bool has_bwc; > + const u8 (*ostdl)[SMI_LARB_PORT_NR_MAX]; > + const struct mtk_smi_reg_pair (*misc)[SMI_LARB_MISC_NR]; > }; > > struct mtk_smi { > @@ -161,6 +192,8 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > u32 reg; > int i; > + const u8 *ostdl; > + const struct mtk_smi_reg_pair *misc; Normally define the local variables from long to short. That means: + const struct mtk_smi_reg_pair *misc; + const u8 *ostdl; u32 reg; int i; > > if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > return; > @@ -170,6 +203,20 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > reg |= F_MMU_EN; > writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); > } > + > + if (!larb->larb_gen->has_bwc) > + return; > + > + for (i = 0, ostdl = larb->larb_gen->ostdl[larb->larbid]; > + i < SMI_LARB_PORT_NR_MAX; i++) > + writel_relaxed(ostdl[i], > + larb->base + SMI_LARB_OSTDL_PORTx(i)); the writel_relaxed can be done in one line, it isn't over 80. ostdl = larb->larb_gen->ostdl[larb->larbid]; for (i = 0; i < SMI_LARB_PORT_NR_MAX; i++) writel_relaxed(ostdl[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); > + > + for (i = 0, misc = larb->larb_gen->misc[larb->larbid]; > + i < SMI_LARB_MISC_NR; i++) > + writel_relaxed(misc[i].value, > + larb->base + misc[i].offset); ditto. it also don't over 80 chars. misc = larb->larb_gen->misc[larb->larbid]; for (i = 0; i < SMI_LARB_MISC_NR; i++) writel_relaxed(misc[i].value, larb->base + misc[i].offset); > + wmb(); /* make sure settings are written */ > } > > static void mtk_smi_larb_config_port_mt8173(struct device *dev) > @@ -239,6 +286,55 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) > .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ > }; > > +static const u8 mtk_smi_larb_mt6779_ostdl[][SMI_LARB_PORT_NR_MAX] = { > + {0x28, 0x28, 0x01, 0x28, 0x01, 0x01, 0x0a, 0x0a, 0x28,}, > + {0x28, 0x01, 0x28, 0x28, 0x0a, 0x01, 0x01, 0x0d, 0x0d, 0x07, > + 0x01, 0x07, 0x01, 0x28,}, > + {0x18, 0x01, 0x08, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, > + 0x01, 0x01}, > + {0x01, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01, 0x04, 0x02, 0x01, > + 0x04, 0x01, 0x01, 0x01, 0x01, 0x04, 0x0b, 0x13, 0x14,}, > + {}, > + {0x13, 0x0f, 0x0d, 0x07, 0x07, 0x04, 0x03, 0x01, 0x03, 0x01, > + 0x05, 0x0c, 0x01, 0x01, 0x08, 0x06, 0x02, 0x01, 0x08, 0x08, > + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,}, > + {0x01, 0x01, 0x01,}, > + {0x01, 0x01, 0x01, 0x01,}, > + {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,}, > + {0x1f, 0x1a, 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x1f, 0x04, > + 0x04, 0x01, 0x01, 0x01, 0x02, 0x02, 0x04, 0x02, 0x01, 0x02, > + 0x04, 0x02, 0x02, 0x01,}, > + {0x1f, 0x1a, 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x1f, 0x1a, > + 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x01, 0x02, 0x02, 0x04, > + 0x02, 0x0a, 0x02, 0x02, 0x04, 0x02, 0x0a, 0x02, 0x04, 0x02, 0x04,}, > + {0x01, 0x01, 0x01, 0x01, 0x01,}, > +}; > + > +static const struct mtk_smi_reg_pair > +mtk_smi_larb_mt6779_misc[][SMI_LARB_MISC_NR] = { > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, I am confused why we need SMI_LARB_SW_FLAG. Does it only indicate that the setting is not the default one?. I guess we also get it from the other regsiter, like SMI_LARB_CMD_THRT_CON. > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {}, > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > +}; > + > +static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { > + .config_port = mtk_smi_larb_config_port_gen2_general, > + .larb_direct_to_common_mask = > + BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), > + /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ > + .has_bwc = true, Does the larb also have has_gals? > + .ostdl = mtk_smi_larb_mt6779_ostdl, > + .misc = mtk_smi_larb_mt6779_misc, > +}; > + > static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { > .has_gals = true, > .config_port = mtk_smi_larb_config_port_gen2_general, > @@ -260,6 +356,10 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) > .data = &mtk_smi_larb_mt2712 > }, > { > + .compatible = "mediatek,mt6779-smi-larb", > + .data = &mtk_smi_larb_mt6779 > + }, > + { > .compatible = "mediatek,mt8183-smi-larb", > .data = &mtk_smi_larb_mt8183 > }, > @@ -386,6 +486,31 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) > .gen = MTK_SMI_GEN2, > }; > > +static const u16 mtk_smi_common_mt6779_l1arb[] = { > + 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, > +}; > + > +static const struct > +mtk_smi_reg_pair mtk_smi_common_mt6779_misc[SMI_COMMON_MISC_NR] = { > + {SMI_L1LEN, 0xb}, > + {SMI_M4U_TH, 0xe100e10}, > + {SMI_FIFO_TH1, 0x506090a}, > + {SMI_FIFO_TH2, 0x506090a}, > + {SMI_DCM, 0x4f1}, > + {SMI_DUMMY, 0x1}, > +}; > + > +static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { > + .gen = MTK_SMI_GEN2, > + .has_gals = true, > + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | > + F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), > + .has_bwc = true, > + .larb_nr = ARRAY_SIZE(mtk_smi_common_mt6779_l1arb), > + .l1arb = mtk_smi_common_mt6779_l1arb, > + .misc = mtk_smi_common_mt6779_misc, How about add a new one?: misc_nr = ARRAY_SIZE(mtk_smi_common_mt6779_misc); Because we should move the "bus_sel" into this misc structure later, right? > +}; > + > static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { > .gen = MTK_SMI_GEN2, > .has_gals = true, > @@ -407,6 +532,10 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) > .data = &mtk_smi_common_gen2, > }, > { > + .compatible = "mediatek,mt6779-smi-common", > + .data = &mtk_smi_common_mt6779, > + }, > + { > .compatible = "mediatek,mt8183-smi-common", > .data = &mtk_smi_common_mt8183, > }, > @@ -484,7 +613,7 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) > { > struct mtk_smi *common = dev_get_drvdata(dev); > u32 bus_sel = common->plat->bus_sel; > - int ret; > + int i, ret; > > ret = mtk_smi_clk_enable(common); > if (ret) { > @@ -494,6 +623,18 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) > > if (common->plat->gen == MTK_SMI_GEN2 && bus_sel) > writel(bus_sel, common->base + SMI_BUS_SEL); > + > + if (!common->plat->has_bwc) > + return 0; > + > + for (i = 0; i < common->plat->larb_nr; i++) > + writel_relaxed(common->plat->l1arb[i], > + common->base + SMI_L1ARB(i)); > + > + for (i = 0; i < SMI_COMMON_MISC_NR; i++) > + writel_relaxed(common->plat->misc[i].value, > + common->base + common->plat->misc[i].value); > + wmb(); /* make sure settings are written */ > return 0; > } In the end, As the comment in v1, this patch should split: a. add basic mt6779 smi-larb support(only add nodes and config_port like the previous SoC.) b. add bandwidth initial settting for mt6779. c. Move the bus_sel into the smi-common misc setting. > ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-12-27 7:22 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-12-09 6:19 [PATCH v2] memory: mtk-smi: Add bandwidth initial setting for MT6779 Ming-Fan Chen 2019-12-09 6:19 ` [PATCH v2 0/2] " Ming-Fan Chen 2019-12-09 6:19 ` [PATCH v2 1/2] dt-bindings: mediatek: Add binding for MT6779 SMI Ming-Fan Chen 2019-12-13 19:10 ` Rob Herring 2019-12-09 6:19 ` [PATCH v2 2/2] memory: mtk-smi: Add bandwidth initial golden setting for MT6779 Ming-Fan Chen 2019-12-27 7:21 ` Yong Wu
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