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Mon, 9 Dec 2019 11:25:41 +0000 From: Yash Shah To: robh+dt@kernel.org, mark.rutland@arm.com, paul.walmsley@sifive.com Cc: palmer@dabbelt.com, aou@eecs.berkeley.edu, bmeng.cn@gmail.com, allison@lohutok.net, alexios.zavras@intel.com, atish.patra@wdc.com, tglx@linutronix.de, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Yash Shah Subject: [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Date: Mon, 9 Dec 2019 16:55:05 +0530 Message-Id: <1575890706-36162-2-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575890706-36162-1-git-send-email-yash.shah@sifive.com> References: <1575890706-36162-1-git-send-email-yash.shah@sifive.com> Content-Type: text/plain X-ClientProxiedBy: BM1PR01CA0100.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00::16) To CH2PR13MB3368.namprd13.prod.outlook.com (2603:10b6:610:2c::26) MIME-Version: 1.0 Received: from dhananjayk-PowerEdge-R620.open-silicon.com (114.143.65.226) by BM1PR01CA0100.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00::16) with Microsoft SMTP Server (version=TLS1_2, cipher=) via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: K0U8yJv63UabKSgpeRxZ0HR+CmAWevUuTF03cmCad3MCZr5Runftzquzdmv9/3ttXF9y4unes5x9g0pvFlSgssVwCdTRcS2U7lphZqQAd7YWFGx5jAKLKdeekB0h0FlKbJWVKGSNsPxCzRqNFbcueVB8cn/dA+YvmBHMtVVU2Vea/4HddDBC1GRPlBjWmxtpFHtaQYWWKqXdknv2ZbExpbEipCJpis7W3Q2gNvZCFk6+NQBN9mmLL80ckyyIE7yT3NDvNKBNXhid2jXD4uFBWjIwA7LKTe9mlwT7XXqCah38cFwqhx0aJFmuk6T3J2We2LhXJVtb0KYU8J/ik0AXnsC/ZhYo4ib7K4DN4B7tqKxVI9lw1sh9mqdvb22S2tVjbhhFHGFX1HjY/WDrTQxqbgZ/nEICT/S21hC68IYarZZhoTDMz4hUccIJgpRQvDAN X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: e31495ca-530c-41bc-c090-08d77c9a85da X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2019 11:25:40.9907 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: c6d/NrZ+4rTJ8PdFD2jsKgA5oWJqRAS6d/WcAj8iO90dD5r3z7dY7xfju3NVsD/CAVW8qRLGrei8LVJRfv3WQQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR13MB3894 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file Signed-off-by: Yash Shah --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index afa43c7..812db02 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -19,6 +19,16 @@ chosen { }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + l2_lim: lim@0x8000000 { + reg = <0x0 0x8000000 0x0 0x2000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -54,6 +64,7 @@ reg = <1>; riscv,isa = "rv64imafdc"; tlb-split; + next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -77,6 +88,7 @@ reg = <2>; riscv,isa = "rv64imafdc"; tlb-split; + next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -100,6 +112,7 @@ reg = <3>; riscv,isa = "rv64imafdc"; tlb-split; + next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -123,6 +136,7 @@ reg = <4>; riscv,isa = "rv64imafdc"; tlb-split; + next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -246,6 +260,18 @@ #pwm-cells = <3>; status = "disabled"; }; + l2cache: cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic0>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + memory-region = <&l2_lim>; + }; }; }; -- 2.7.4