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From: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>
To: linux-mips@vger.kernel.org
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, paul@crapouillou.net,
	mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
	mark.rutland@arm.com
Subject: [PATCH v5 1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers.
Date: Sat, 15 Feb 2020 01:27:37 +0800	[thread overview]
Message-ID: <1581701262-110556-3-git-send-email-zhouyanjie@wanyeetech.com> (raw)
In-Reply-To: <1581701262-110556-1-git-send-email-zhouyanjie@wanyeetech.com>

It is not necessary to use spinlock when reading registers,
so remove it from cgu.c.

Suggested-by: Paul Cercueil <paul@crapouillou.net>
Suggested-by: Paul Burton <paulburton@kernel.org>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---

Notes:
    v2:
    New patch.
    
    v2->v3:
    Adjust order from [5/5] in v2 to [1/5] in v3.
    
    v3->v4:
    Remove the spinlock around ingenic_cgu_gate_get().
    
    v4->v5:
    Rebase on top of kernel 5.6-rc1.

 drivers/clk/ingenic/cgu.c | 12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 6e96303..ab1302a 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -76,16 +76,13 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 	const struct ingenic_cgu_pll_info *pll_info;
 	unsigned m, n, od_enc, od;
 	bool bypass;
-	unsigned long flags;
 	u32 ctl;
 
 	clk_info = &cgu->clock_info[ingenic_clk->idx];
 	BUG_ON(clk_info->type != CGU_CLK_PLL);
 	pll_info = &clk_info->pll;
 
-	spin_lock_irqsave(&cgu->lock, flags);
 	ctl = readl(cgu->base + pll_info->reg);
-	spin_unlock_irqrestore(&cgu->lock, flags);
 
 	m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);
 	m += pll_info->m_offset;
@@ -259,12 +256,9 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw)
 	struct ingenic_cgu *cgu = ingenic_clk->cgu;
 	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
 	const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
-	unsigned long flags;
 	u32 ctl;
 
-	spin_lock_irqsave(&cgu->lock, flags);
 	ctl = readl(cgu->base + pll_info->reg);
-	spin_unlock_irqrestore(&cgu->lock, flags);
 
 	return !!(ctl & BIT(pll_info->enable_bit));
 }
@@ -562,16 +556,12 @@ static int ingenic_clk_is_enabled(struct clk_hw *hw)
 	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
 	struct ingenic_cgu *cgu = ingenic_clk->cgu;
 	const struct ingenic_cgu_clk_info *clk_info;
-	unsigned long flags;
 	int enabled = 1;
 
 	clk_info = &cgu->clock_info[ingenic_clk->idx];
 
-	if (clk_info->type & CGU_CLK_GATE) {
-		spin_lock_irqsave(&cgu->lock, flags);
+	if (clk_info->type & CGU_CLK_GATE)
 		enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);
-		spin_unlock_irqrestore(&cgu->lock, flags);
-	}
 
 	return enabled;
 }
-- 
2.7.4


  parent reply	other threads:[~2020-02-14 17:28 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14 17:27 Add support for the X1830 and fix bugs for X1000 v5 周琰杰 (Zhou Yanjie)
2020-02-14 17:27 ` [PATCH v5 0/6] " 周琰杰 (Zhou Yanjie)
2020-02-14 17:27 ` 周琰杰 (Zhou Yanjie) [this message]
2020-02-14 17:27 ` [PATCH v5 2/6] clk: Ingenic: Adjust cgu code to make it compatible with X1830 周琰杰 (Zhou Yanjie)
2020-02-14 18:49   ` Paul Cercueil
2020-02-15 14:07     ` Zhou Yanjie
2020-02-14 17:27 ` [PATCH v5 3/6] dt-bindings: clock: Add X1830 bindings 周琰杰 (Zhou Yanjie)
2020-02-14 17:27 ` [PATCH v5 4/6] clk: Ingenic: Add CGU driver for X1830 周琰杰 (Zhou Yanjie)
2020-02-14 17:27 ` [PATCH v5 5/6] dt-bindings: clock: Add and reorder ABI for X1000 周琰杰 (Zhou Yanjie)
2020-02-18 21:05   ` Rob Herring
2020-02-14 17:27 ` [PATCH v5 6/6] clk: X1000: Add FIXDIV for SSI clock of X1000 周琰杰 (Zhou Yanjie)

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