From: Stephen Boyd <sboyd@kernel.org>
To: Sivaprakash Murugesan <sivaprak@codeaurora.org>,
agross@kernel.org, bjorn.andersson@linaro.org,
devicetree@vger.kernel.org, jassisinghbrar@gmail.com,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, mturquette@baylibre.com,
robh+dt@kernel.org
Cc: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Subject: Re: [PATCH V3 5/8] clk: qcom: Add ipq apss clock controller
Date: Wed, 22 Apr 2020 02:04:22 -0700 [thread overview]
Message-ID: <158754626202.132238.18279860573775399302@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1586832922-29191-6-git-send-email-sivaprak@codeaurora.org>
Quoting Sivaprakash Murugesan (2020-04-13 19:55:19)
> The CPU on Qualcomm's IPQ platform devices are clocked primarily by a
> PLL and xo which are connected to a mux and enable block, This patch adds
The comma should be a period? Don't write "This patch" in commit text.
> support for the mux and the enable.
>
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
> drivers/clk/qcom/Kconfig | 10 +++++
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/apss-ipq.c | 107 ++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 118 insertions(+)
> create mode 100644 drivers/clk/qcom/apss-ipq.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 15cdcdc..8573f2e 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -89,6 +89,16 @@ config APQ_MMCC_8084
> Say Y if you want to support multimedia devices such as display,
> graphics, video encode/decode, camera, etc.
>
> +config IPQ_APSS
> + tristate "IPQ APSS Clock Controller"
> + default N
Drop this, it's already the default.
> + help
> + Support for APSS clock controller on ipq platform devices. The
Maybe say "IPQ platforms" and drop the devices part?
> + APSS clock controller manages the Mux and enable block that feeds the
> + CPUs.
> + Say Y if you want to support CPU frequency scaling on
> + ipq based devices.
> +
> config IPQ_GCC_4019
> tristate "IPQ4019 Global Clock Controller"
> help
> diff --git a/drivers/clk/qcom/apss-ipq.c b/drivers/clk/qcom/apss-ipq.c
> new file mode 100644
> index 0000000..a37cd98
> --- /dev/null
> +++ b/drivers/clk/qcom/apss-ipq.c
> @@ -0,0 +1,107 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/regmap.h>
> +#include <linux/module.h>
> +
> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> +
> +#include "common.h"
> +#include "clk-regmap.h"
> +#include "clk-branch.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-regmap-mux.h"
> +
> +enum {
> + P_XO,
> + P_APSS_PLL_EARLY,
> +};
> +
> +static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
> + { .fw_name = "xo" },
> + { .fw_name = "pll" },
> +};
> +
> +static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
> + { P_XO, 0 },
> + { P_APSS_PLL_EARLY, 5 },
> +};
> +
> +static struct clk_regmap_mux apcs_alias0_clk_src = {
> + .reg = 0x0050,
> + .width = 3,
> + .shift = 7,
> + .parent_map = parents_apcs_alias0_clk_src_map,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "apcs_alias0_clk_src",
> + .parent_data = parents_apcs_alias0_clk_src,
> + .num_parents = 2,
> + .ops = &clk_regmap_mux_closest_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/*required for cpufreq*/
This comment doesn't help in understanding.
> +static struct clk_branch apcs_alias0_core_clk = {
> + .halt_reg = 0x0058,
> + .clkr = {
> + .enable_reg = 0x0058,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "apcs_alias0_core_clk",
> + .parent_hws = (const struct clk_hw *[]){
> + &apcs_alias0_clk_src.clkr.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
Please comment why the clk is critical.
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static const struct regmap_config apss_ipq_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x1000,
> + .fast_io = true,
> +};
> +
> +static struct clk_regmap *apss_ipq_clks[] = {
> + [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr,
> + [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr,
> +};
> +
> +static const struct qcom_cc_desc apss_ipq_desc = {
> + .config = &apss_ipq_regmap_config,
> + .clks = apss_ipq_clks,
> + .num_clks = ARRAY_SIZE(apss_ipq_clks),
> +};
> +
> +static int apss_ipq_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> +
> + regmap = dev_get_regmap(pdev->dev.parent, NULL);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + return qcom_cc_really_probe(pdev, &apss_ipq_desc, regmap);
What is this a child of?
> +}
> +
> +static struct platform_driver apss_ipq_driver = {
> + .probe = apss_ipq_probe,
> + .driver = {
> + .name = "qcom,apss-ipq-clk",
> + },
> +};
next prev parent reply other threads:[~2020-04-22 9:04 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-14 2:55 [PATCH V3 0/8] Add APSS clock controller support for IPQ6018 Sivaprakash Murugesan
2020-04-14 2:55 ` [PATCH V3 1/8] dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block Sivaprakash Murugesan
2020-04-20 20:59 ` Rob Herring
2020-05-04 6:14 ` Sivaprakash Murugesan
2020-04-14 2:55 ` [PATCH V3 2/8] dt-bindings: clock: Add YAML schemas for QCOM A53 PLL Sivaprakash Murugesan
2020-04-20 21:01 ` Rob Herring
2020-05-04 6:13 ` Sivaprakash Murugesan
2020-04-20 21:03 ` Rob Herring
2020-04-14 2:55 ` [PATCH V3 3/8] clk: qcom: Add A53 PLL support for ipq6018 devices Sivaprakash Murugesan
2020-04-22 9:00 ` Stephen Boyd
2020-04-22 10:44 ` Sivaprakash Murugesan
2020-05-14 20:40 ` Stephen Boyd
2020-05-24 9:36 ` Sivaprakash Murugesan
2020-04-14 2:55 ` [PATCH V3 4/8] clk: qcom: Add DT bindings for ipq6018 apss clock controller Sivaprakash Murugesan
2020-04-14 2:55 ` [PATCH V3 5/8] clk: qcom: Add ipq " Sivaprakash Murugesan
2020-04-22 9:04 ` Stephen Boyd [this message]
2020-05-04 6:10 ` Sivaprakash Murugesan
2020-04-14 2:55 ` [PATCH V3 6/8] dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block Sivaprakash Murugesan
2020-04-20 21:05 ` Rob Herring
2020-04-14 2:55 ` [PATCH V3 7/8] mailbox: qcom: Add ipq6018 apcs compatible Sivaprakash Murugesan
2020-04-14 2:55 ` [PATCH V3 8/8] arm64: dts: ipq6018: Add a53 pll and apcs clock Sivaprakash Murugesan
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