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* [PATCH v5 0/4] add NXP imx8mp usb support
@ 2020-10-03 12:02 Li Jun
  2020-10-03 12:02 ` [PATCH v5 1/4] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings Li Jun
                   ` (4 more replies)
  0 siblings, 5 replies; 9+ messages in thread
From: Li Jun @ 2020-10-03 12:02 UTC (permalink / raw)
  To: robh+dt, shawnguo, balbi
  Cc: krzk, gregkh, s.hauer, kernel, festevam, linux-imx, Anson.Huang,
	jun.li, aisheng.dong, peng.fan, fugang.duan, horia.geanta,
	qiangqing.zhang, peter.chen, devicetree, linux-arm-kernel

NXP imx8MPlus integrates 2 indentical dwc3 3.30b IP with additional wakeup
logic to support low power, this wakeup logic has a separated interrupt
which can generate events with suspend clock(32K); due to SoC integration
limitation, it only can support 32 bits DMA, so add dma-ranges property,

changes for v5
- Remove "Items" of compatible in binding doc [1/4]
- Add Krzysztof's R-b tag for patches [3-4/4].

changes for v4:
- Use dma-ranges property to limit 32bits DMA, so don't need the new
  property "xhci-64bit-support-disable".
- Fix binding doc to pass dt_binding_check dtbs_check.

changes for v3:
- Add dwc3 core related clocks into dwc3 core node, and glue layer driver
  only handle the clocks(hsio and suspend) for glue block, this is to
  match real HW.
- Change to use property "xhci-64bit-support-disable" to disable 64bit DMA
  as imx8mp USB integration actully can't support it, so remove platform
  data in v2.
- Some changes of imx8mp usb driver binding doc to address comments from Rob

Changes for v2:
- Drop the 2 patches for new property("snps,xhci-dis-64bit-support-quirk")
  introduction, as suggested, imply by SoC compatible string, this is done
  by introduce dwc3 core platform data and pass the xhci_plat_priv to
  xhci-plat for those xhci quirks, so a new patch added:
  [1/5] usb: dwc3: add platform data to dwc3 core device to pass data.
  this patch is based on Peter's one patch which is also in review:
  https://patchwork.kernel.org/patch/11640945/
- dts change, use the USB power function of TRL logic instead of a always-on
  regulator to control vbus on/off.
- Some changes to address Peter's command on patch [2/5].

Li Jun (4):
  dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings
  usb: dwc3: add imx8mp dwc3 glue layer driver
  arm64: dtsi: imx8mp: add usb nodes
  arm64: dts: imx8mp-evk: enable usb1 as host mode

 .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml   | 105 ++++++
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts       |  21 ++
 arch/arm64/boot/dts/freescale/imx8mp.dtsi          |  82 +++++
 drivers/usb/dwc3/Kconfig                           |  10 +
 drivers/usb/dwc3/Makefile                          |   1 +
 drivers/usb/dwc3/dwc3-imx8mp.c                     | 363 +++++++++++++++++++++
 6 files changed, 582 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
 create mode 100644 drivers/usb/dwc3/dwc3-imx8mp.c

-- 
2.7.4


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v5 1/4] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings
  2020-10-03 12:02 [PATCH v5 0/4] add NXP imx8mp usb support Li Jun
@ 2020-10-03 12:02 ` Li Jun
  2020-10-04 13:44   ` Krzysztof Kozlowski
  2020-10-06 21:10   ` Rob Herring
  2020-10-03 12:02 ` [PATCH v5 2/4] usb: dwc3: add imx8mp dwc3 glue layer driver Li Jun
                   ` (3 subsequent siblings)
  4 siblings, 2 replies; 9+ messages in thread
From: Li Jun @ 2020-10-03 12:02 UTC (permalink / raw)
  To: robh+dt, shawnguo, balbi
  Cc: krzk, gregkh, s.hauer, kernel, festevam, linux-imx, Anson.Huang,
	jun.li, aisheng.dong, peng.fan, fugang.duan, horia.geanta,
	qiangqing.zhang, peter.chen, devicetree, linux-arm-kernel

NXP imx8mp integrates 2 dwc3 3.30b IP and add some wakeup logic
to support low power mode, the glue layer is for this wakeup
functionality, which has a separated interrupt, can support
wakeup from U3 and connect events for host, and vbus wakeup for
device.

Signed-off-by: Li Jun <jun.li@nxp.com>
---
 .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml   | 105 +++++++++++++++++++++
 1 file changed, 105 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
new file mode 100644
index 0000000..cb4c6f6
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP iMX8MP Soc USB Controller
+
+maintainers:
+  - Li Jun <jun.li@nxp.com>
+
+properties:
+  compatible:
+    const: fsl,imx8mp-dwc3
+
+  reg:
+    maxItems: 1
+    description: Address and length of the register set for the wrapper of
+      dwc3 core on the SOC.
+
+  "#address-cells":
+    enum: [ 1, 2 ]
+
+  "#size-cells":
+    enum: [ 1, 2 ]
+
+  dma-ranges:
+    description:
+      See section 2.3.9 of the DeviceTree Specification.
+
+  ranges: true
+
+  interrupts:
+    maxItems: 1
+    description: The interrupt that is asserted when a wakeup event is
+      received.
+
+  clocks:
+    description:
+      A list of phandle and clock-specifier pairs for the clocks
+      listed in clock-names.
+    items:
+      - description: system hsio root clock.
+      - description: suspend clock, used for usb wakeup logic.
+
+  clock-names:
+    items:
+      - const: hsio
+      - const: suspend
+
+# Required child node:
+
+patternProperties:
+  "^dwc3@[0-9a-f]+$":
+    type: object
+    description:
+      A child node must exist to represent the core DWC3 IP block
+      The content of the node is defined in dwc3.txt.
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+  - dma-ranges
+  - ranges
+  - clocks
+  - clock-names
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mp-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    usb3_0: usb@32f10100 {
+      compatible = "fsl,imx8mp-dwc3";
+      reg = <0x32f10100 0x8>;
+      clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+               <&clk IMX8MP_CLK_USB_ROOT>;
+      clock-names = "hsio", "suspend";
+      interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+      #address-cells = <1>;
+      #size-cells = <1>;
+      dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+      ranges;
+
+      dwc3@38100000 {
+        compatible = "snps,dwc3";
+        reg = <0x38100000 0x10000>;
+        clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+                 <&clk IMX8MP_CLK_USB_CORE_REF>,
+                 <&clk IMX8MP_CLK_USB_ROOT>;
+        clock-names = "bus_early", "ref", "suspend";
+        assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+        assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+        assigned-clock-rates = <500000000>;
+        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+        phys = <&usb3_phy0>, <&usb3_phy0>;
+        phy-names = "usb2-phy", "usb3-phy";
+        snps,dis-u2-freeclk-exists-quirk;
+      };
+    };
-- 
2.7.4


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v5 2/4] usb: dwc3: add imx8mp dwc3 glue layer driver
  2020-10-03 12:02 [PATCH v5 0/4] add NXP imx8mp usb support Li Jun
  2020-10-03 12:02 ` [PATCH v5 1/4] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings Li Jun
@ 2020-10-03 12:02 ` Li Jun
  2020-12-04  2:07   ` Jun Li
  2020-10-03 12:02 ` [PATCH v5 3/4] arm64: dtsi: imx8mp: add usb nodes Li Jun
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 9+ messages in thread
From: Li Jun @ 2020-10-03 12:02 UTC (permalink / raw)
  To: robh+dt, shawnguo, balbi
  Cc: krzk, gregkh, s.hauer, kernel, festevam, linux-imx, Anson.Huang,
	jun.li, aisheng.dong, peng.fan, fugang.duan, horia.geanta,
	qiangqing.zhang, peter.chen, devicetree, linux-arm-kernel

imx8mp SoC integrate dwc3 3.30b IP and has some customizations to
support low power, which has a seprated wakeup irq and additional
logic to wakeup usb from low power mode both for host mode and
device mode.

Signed-off-by: Li Jun <jun.li@nxp.com>
---
 drivers/usb/dwc3/Kconfig       |  10 ++
 drivers/usb/dwc3/Makefile      |   1 +
 drivers/usb/dwc3/dwc3-imx8mp.c | 363 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 374 insertions(+)

diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 7a23045..2133acf 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -139,4 +139,14 @@ config USB_DWC3_QCOM
 	  for peripheral mode support.
 	  Say 'Y' or 'M' if you have one such device.
 
+config USB_DWC3_IMX8MP
+	tristate "NXP iMX8MP Platform"
+	depends on OF && COMMON_CLK
+	depends on (ARCH_MXC && ARM64) || COMPILE_TEST
+	default USB_DWC3
+	help
+	  NXP iMX8M Plus SoC use DesignWare Core IP for USB2/3
+	  functionality.
+	  Say 'Y' or 'M' if you have one such device.
+
 endif
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index ae86da0..2259f88 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A)	+= dwc3-meson-g12a.o
 obj-$(CONFIG_USB_DWC3_OF_SIMPLE)	+= dwc3-of-simple.o
 obj-$(CONFIG_USB_DWC3_ST)		+= dwc3-st.o
 obj-$(CONFIG_USB_DWC3_QCOM)		+= dwc3-qcom.o
+obj-$(CONFIG_USB_DWC3_IMX8MP)		+= dwc3-imx8mp.o
diff --git a/drivers/usb/dwc3/dwc3-imx8mp.c b/drivers/usb/dwc3/dwc3-imx8mp.c
new file mode 100644
index 0000000..75f0042
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-imx8mp.c
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
+ *
+ * Copyright (c) 2020 NXP.
+ */
+
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include "core.h"
+
+/* USB wakeup registers */
+#define USB_WAKEUP_CTRL			0x00
+
+/* Global wakeup interrupt enable, also used to clear interrupt */
+#define USB_WAKEUP_EN			BIT(31)
+/* Wakeup from connect or disconnect, only for superspeed */
+#define USB_WAKEUP_SS_CONN		BIT(5)
+/* 0 select vbus_valid, 1 select sessvld */
+#define USB_WAKEUP_VBUS_SRC_SESS_VAL	BIT(4)
+/* Enable signal for wake up from u3 state */
+#define USB_WAKEUP_U3_EN		BIT(3)
+/* Enable signal for wake up from id change */
+#define USB_WAKEUP_ID_EN		BIT(2)
+/* Enable signal for wake up from vbus change */
+#define	USB_WAKEUP_VBUS_EN		BIT(1)
+/* Enable signal for wake up from dp/dm change */
+#define USB_WAKEUP_DPDM_EN		BIT(0)
+
+#define USB_WAKEUP_EN_MASK		GENMASK(5, 0)
+
+struct dwc3_imx8mp {
+	struct device			*dev;
+	struct platform_device		*dwc3;
+	void __iomem			*glue_base;
+	struct clk			*hsio_clk;
+	struct clk			*suspend_clk;
+	int				irq;
+	bool				pm_suspended;
+	bool				wakeup_pending;
+};
+
+static void dwc3_imx8mp_wakeup_enable(struct dwc3_imx8mp *dwc3_imx)
+{
+	struct dwc3	*dwc3 = platform_get_drvdata(dwc3_imx->dwc3);
+	u32		val;
+
+	if (!dwc3)
+		return;
+
+	val = readl(dwc3_imx->glue_base + USB_WAKEUP_CTRL);
+
+	if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci)
+		val |= USB_WAKEUP_EN | USB_WAKEUP_SS_CONN |
+		       USB_WAKEUP_U3_EN | USB_WAKEUP_DPDM_EN;
+	else if (dwc3->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE)
+		val |= USB_WAKEUP_EN | USB_WAKEUP_VBUS_EN |
+		       USB_WAKEUP_VBUS_SRC_SESS_VAL;
+
+	writel(val, dwc3_imx->glue_base + USB_WAKEUP_CTRL);
+}
+
+static void dwc3_imx8mp_wakeup_disable(struct dwc3_imx8mp *dwc3_imx)
+{
+	u32 val;
+
+	val = readl(dwc3_imx->glue_base + USB_WAKEUP_CTRL);
+	val &= ~(USB_WAKEUP_EN | USB_WAKEUP_EN_MASK);
+	writel(val, dwc3_imx->glue_base + USB_WAKEUP_CTRL);
+}
+
+static irqreturn_t dwc3_imx8mp_interrupt(int irq, void *_dwc3_imx)
+{
+	struct dwc3_imx8mp	*dwc3_imx = _dwc3_imx;
+	struct dwc3		*dwc = platform_get_drvdata(dwc3_imx->dwc3);
+
+	if (!dwc3_imx->pm_suspended)
+		return IRQ_HANDLED;
+
+	disable_irq_nosync(dwc3_imx->irq);
+	dwc3_imx->wakeup_pending = true;
+
+	if ((dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc->xhci)
+		pm_runtime_resume(&dwc->xhci->dev);
+	else if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE)
+		pm_runtime_get(dwc->dev);
+
+	return IRQ_HANDLED;
+}
+
+static int dwc3_imx8mp_probe(struct platform_device *pdev)
+{
+	struct device		*dev = &pdev->dev;
+	struct device_node	*dwc3_np, *node = dev->of_node;
+	struct dwc3_imx8mp	*dwc3_imx;
+	int			err, irq;
+
+	if (!node) {
+		dev_err(dev, "device node not found\n");
+		return -EINVAL;
+	}
+
+	dwc3_imx = devm_kzalloc(dev, sizeof(*dwc3_imx), GFP_KERNEL);
+	if (!dwc3_imx)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, dwc3_imx);
+
+	dwc3_imx->dev = dev;
+
+	dwc3_imx->glue_base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(dwc3_imx->glue_base))
+		return PTR_ERR(dwc3_imx->glue_base);
+
+	dwc3_imx->hsio_clk = devm_clk_get(dev, "hsio");
+	if (IS_ERR(dwc3_imx->hsio_clk)) {
+		err = PTR_ERR(dwc3_imx->hsio_clk);
+		dev_err(dev, "Failed to get hsio clk, err=%d\n", err);
+		return err;
+	}
+
+	err = clk_prepare_enable(dwc3_imx->hsio_clk);
+	if (err) {
+		dev_err(dev, "Failed to enable hsio clk, err=%d\n", err);
+		return err;
+	}
+
+	dwc3_imx->suspend_clk = devm_clk_get(dev, "suspend");
+	if (IS_ERR(dwc3_imx->suspend_clk)) {
+		err = PTR_ERR(dwc3_imx->suspend_clk);
+		dev_err(dev, "Failed to get suspend clk, err=%d\n", err);
+		goto disable_hsio_clk;
+	}
+
+	err = clk_prepare_enable(dwc3_imx->suspend_clk);
+	if (err) {
+		dev_err(dev, "Failed to enable suspend clk, err=%d\n", err);
+		goto disable_hsio_clk;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		err = irq;
+		goto disable_clks;
+	}
+	dwc3_imx->irq = irq;
+
+	err = devm_request_threaded_irq(dev, irq, NULL, dwc3_imx8mp_interrupt,
+					IRQF_ONESHOT, dev_name(dev), dwc3_imx);
+	if (err) {
+		dev_err(dev, "failed to request IRQ #%d --> %d\n", irq, err);
+		goto disable_clks;
+	}
+
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
+	err = pm_runtime_get_sync(dev);
+	if (err < 0)
+		goto disable_rpm;
+
+	dwc3_np = of_get_child_by_name(node, "dwc3");
+	if (!dwc3_np) {
+		dev_err(dev, "failed to find dwc3 core child\n");
+		goto disable_rpm;
+	}
+
+	err = of_platform_populate(node, NULL, NULL, dev);
+	if (err) {
+		dev_err(&pdev->dev, "failed to create dwc3 core\n");
+		goto err_node_put;
+	}
+
+	dwc3_imx->dwc3 = of_find_device_by_node(dwc3_np);
+	if (!dwc3_imx->dwc3) {
+		dev_err(dev, "failed to get dwc3 platform device\n");
+		err = -ENODEV;
+		goto depopulate;
+	}
+	of_node_put(dwc3_np);
+
+	device_set_wakeup_capable(dev, true);
+	pm_runtime_put(dev);
+
+	return 0;
+
+depopulate:
+	of_platform_depopulate(dev);
+err_node_put:
+	of_node_put(dwc3_np);
+disable_rpm:
+	pm_runtime_disable(dev);
+	pm_runtime_put_noidle(dev);
+disable_clks:
+	clk_disable_unprepare(dwc3_imx->suspend_clk);
+disable_hsio_clk:
+	clk_disable_unprepare(dwc3_imx->hsio_clk);
+
+	return err;
+}
+
+static int dwc3_imx8mp_remove(struct platform_device *pdev)
+{
+	struct dwc3_imx8mp *dwc3_imx = platform_get_drvdata(pdev);
+	struct device *dev = &pdev->dev;
+
+	pm_runtime_get_sync(dev);
+	of_platform_depopulate(dev);
+
+	clk_disable_unprepare(dwc3_imx->suspend_clk);
+	clk_disable_unprepare(dwc3_imx->hsio_clk);
+
+	pm_runtime_disable(dev);
+	pm_runtime_put_noidle(dev);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static int __maybe_unused dwc3_imx8mp_suspend(struct dwc3_imx8mp *dwc3_imx,
+					      pm_message_t msg)
+{
+	if (dwc3_imx->pm_suspended)
+		return 0;
+
+	/* Wakeup enable */
+	if (PMSG_IS_AUTO(msg) || device_may_wakeup(dwc3_imx->dev))
+		dwc3_imx8mp_wakeup_enable(dwc3_imx);
+
+	dwc3_imx->pm_suspended = true;
+
+	return 0;
+}
+
+static int __maybe_unused dwc3_imx8mp_resume(struct dwc3_imx8mp *dwc3_imx,
+					     pm_message_t msg)
+{
+	struct dwc3	*dwc = platform_get_drvdata(dwc3_imx->dwc3);
+	int ret = 0;
+
+	if (!dwc3_imx->pm_suspended)
+		return 0;
+
+	/* Wakeup disable */
+	dwc3_imx8mp_wakeup_disable(dwc3_imx);
+	dwc3_imx->pm_suspended = false;
+
+	if (dwc3_imx->wakeup_pending) {
+		dwc3_imx->wakeup_pending = false;
+		if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) {
+			pm_runtime_mark_last_busy(dwc->dev);
+			pm_runtime_put_autosuspend(dwc->dev);
+		} else {
+			/*
+			 * Add wait for xhci switch from suspend
+			 * clock to normal clock to detect connection.
+			 */
+			usleep_range(9000, 10000);
+		}
+		enable_irq(dwc3_imx->irq);
+	}
+
+	return ret;
+}
+
+static int __maybe_unused dwc3_imx8mp_pm_suspend(struct device *dev)
+{
+	struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
+	int ret;
+
+	ret = dwc3_imx8mp_suspend(dwc3_imx, PMSG_SUSPEND);
+
+	if (device_may_wakeup(dwc3_imx->dev))
+		enable_irq_wake(dwc3_imx->irq);
+	else
+		clk_disable_unprepare(dwc3_imx->suspend_clk);
+
+	clk_disable_unprepare(dwc3_imx->hsio_clk);
+	dev_dbg(dev, "dwc3 imx8mp pm suspend.\n");
+
+	return ret;
+}
+
+static int __maybe_unused dwc3_imx8mp_pm_resume(struct device *dev)
+{
+	struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
+	int ret;
+
+	if (device_may_wakeup(dwc3_imx->dev)) {
+		disable_irq_wake(dwc3_imx->irq);
+	} else {
+		ret = clk_prepare_enable(dwc3_imx->suspend_clk);
+		if (ret)
+			return ret;
+	}
+
+	ret = clk_prepare_enable(dwc3_imx->hsio_clk);
+	if (ret)
+		return ret;
+
+	ret = dwc3_imx8mp_resume(dwc3_imx, PMSG_RESUME);
+
+	pm_runtime_disable(dev);
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
+
+	dev_dbg(dev, "dwc3 imx8mp pm resume.\n");
+
+	return ret;
+}
+
+static int __maybe_unused dwc3_imx8mp_runtime_suspend(struct device *dev)
+{
+	struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
+
+	dev_dbg(dev, "dwc3 imx8mp runtime suspend.\n");
+
+	return dwc3_imx8mp_suspend(dwc3_imx, PMSG_AUTO_SUSPEND);
+}
+
+static int __maybe_unused dwc3_imx8mp_runtime_resume(struct device *dev)
+{
+	struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
+
+	dev_dbg(dev, "dwc3 imx8mp runtime resume.\n");
+
+	return dwc3_imx8mp_resume(dwc3_imx, PMSG_AUTO_RESUME);
+}
+
+static const struct dev_pm_ops dwc3_imx8mp_dev_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(dwc3_imx8mp_pm_suspend, dwc3_imx8mp_pm_resume)
+	SET_RUNTIME_PM_OPS(dwc3_imx8mp_runtime_suspend,
+			   dwc3_imx8mp_runtime_resume, NULL)
+};
+
+static const struct of_device_id dwc3_imx8mp_of_match[] = {
+	{ .compatible = "fsl,imx8mp-dwc3", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, dwc3_imx8mp_of_match);
+
+static struct platform_driver dwc3_imx8mp_driver = {
+	.probe		= dwc3_imx8mp_probe,
+	.remove		= dwc3_imx8mp_remove,
+	.driver		= {
+		.name	= "imx8mp-dwc3",
+		.pm	= &dwc3_imx8mp_dev_pm_ops,
+		.of_match_table	= dwc3_imx8mp_of_match,
+	},
+};
+
+module_platform_driver(dwc3_imx8mp_driver);
+
+MODULE_ALIAS("platform:imx8mp-dwc3");
+MODULE_AUTHOR("jun.li@nxp.com");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DesignWare USB3 imx8mp Glue Layer");
-- 
2.7.4


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v5 3/4] arm64: dtsi: imx8mp: add usb nodes
  2020-10-03 12:02 [PATCH v5 0/4] add NXP imx8mp usb support Li Jun
  2020-10-03 12:02 ` [PATCH v5 1/4] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings Li Jun
  2020-10-03 12:02 ` [PATCH v5 2/4] usb: dwc3: add imx8mp dwc3 glue layer driver Li Jun
@ 2020-10-03 12:02 ` Li Jun
  2020-10-03 12:02 ` [PATCH v5 4/4] arm64: dts: imx8mp-evk: enable usb1 as host mode Li Jun
  2020-10-30  7:23 ` [PATCH v5 0/4] add NXP imx8mp usb support Shawn Guo
  4 siblings, 0 replies; 9+ messages in thread
From: Li Jun @ 2020-10-03 12:02 UTC (permalink / raw)
  To: robh+dt, shawnguo, balbi
  Cc: krzk, gregkh, s.hauer, kernel, festevam, linux-imx, Anson.Huang,
	jun.li, aisheng.dong, peng.fan, fugang.duan, horia.geanta,
	qiangqing.zhang, peter.chen, devicetree, linux-arm-kernel

imx8mp integrates 2 identical dwc3 based USB3 controllers and
Synopsys phys, each instance has additional wakeup logic to
support low power mode, so the glue layer need a node with dwc3
core sub node.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Li Jun <jun.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 82 +++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 9de2aa1..2d2efc9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -750,5 +750,87 @@
 			reg = <0x3d800000 0x400000>;
 			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		usb3_phy0: usb-phy@381f0040 {
+			compatible = "fsl,imx8mp-usb-phy";
+			reg = <0x381f0040 0x40>;
+			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+			clock-names = "phy";
+			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usb3_0: usb@32f10100 {
+			compatible = "fsl,imx8mp-dwc3";
+			reg = <0x32f10100 0x8>;
+			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+				 <&clk IMX8MP_CLK_USB_ROOT>;
+			clock-names = "hsio", "suspend";
+			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+			ranges;
+			status = "disabled";
+
+			usb_dwc3_0: dwc3@38100000 {
+				compatible = "snps,dwc3";
+				reg = <0x38100000 0x10000>;
+				clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+					 <&clk IMX8MP_CLK_USB_CORE_REF>,
+					 <&clk IMX8MP_CLK_USB_ROOT>;
+				clock-names = "bus_early", "ref", "suspend";
+				assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+				assigned-clock-rates = <500000000>;
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb3_phy0>, <&usb3_phy0>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u2-freeclk-exists-quirk;
+			};
+
+		};
+
+		usb3_phy1: usb-phy@382f0040 {
+			compatible = "fsl,imx8mp-usb-phy";
+			reg = <0x382f0040 0x40>;
+			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+			clock-names = "phy";
+			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+			#phy-cells = <0>;
+		};
+
+		usb3_1: usb@32f10108 {
+			compatible = "fsl,imx8mp-dwc3";
+			reg = <0x32f10108 0x8>;
+			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+				 <&clk IMX8MP_CLK_USB_ROOT>;
+			clock-names = "hsio", "suspend";
+			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+			ranges;
+			status = "disabled";
+
+			usb_dwc3_1: dwc3@38200000 {
+				compatible = "snps,dwc3";
+				reg = <0x38200000 0x10000>;
+				clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+					 <&clk IMX8MP_CLK_USB_CORE_REF>,
+					 <&clk IMX8MP_CLK_USB_ROOT>;
+				clock-names = "bus_early", "ref", "suspend";
+				assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+				assigned-clock-rates = <500000000>;
+				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb3_phy1>, <&usb3_phy1>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u2-freeclk-exists-quirk;
+			};
+		};
 	};
 };
-- 
2.7.4


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v5 4/4] arm64: dts: imx8mp-evk: enable usb1 as host mode
  2020-10-03 12:02 [PATCH v5 0/4] add NXP imx8mp usb support Li Jun
                   ` (2 preceding siblings ...)
  2020-10-03 12:02 ` [PATCH v5 3/4] arm64: dtsi: imx8mp: add usb nodes Li Jun
@ 2020-10-03 12:02 ` Li Jun
  2020-10-30  7:23 ` [PATCH v5 0/4] add NXP imx8mp usb support Shawn Guo
  4 siblings, 0 replies; 9+ messages in thread
From: Li Jun @ 2020-10-03 12:02 UTC (permalink / raw)
  To: robh+dt, shawnguo, balbi
  Cc: krzk, gregkh, s.hauer, kernel, festevam, linux-imx, Anson.Huang,
	jun.li, aisheng.dong, peng.fan, fugang.duan, horia.geanta,
	qiangqing.zhang, peter.chen, devicetree, linux-arm-kernel

Enable usb host port with type-A connector on imx8mp-evk board.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Li Jun <jun.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 432c1a7..0cb3b16 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -176,6 +176,21 @@
 	};
 };
 
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb1_vbus>;
+	dr_mode = "host";
+	status = "okay";
+};
+
 &usdhc2 {
 	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 	assigned-clock-rates = <400000000>;
@@ -276,6 +291,12 @@
 		>;
 	};
 
+	pinctrl_usb1_vbus: usb1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR	0x19
+		>;
+	};
+
 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
-- 
2.7.4


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v5 1/4] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings
  2020-10-03 12:02 ` [PATCH v5 1/4] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings Li Jun
@ 2020-10-04 13:44   ` Krzysztof Kozlowski
  2020-10-06 21:10   ` Rob Herring
  1 sibling, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-04 13:44 UTC (permalink / raw)
  To: Li Jun
  Cc: robh+dt, shawnguo, balbi, gregkh, s.hauer, kernel, festevam,
	linux-imx, Anson.Huang, aisheng.dong, peng.fan, fugang.duan,
	horia.geanta, qiangqing.zhang, peter.chen, devicetree,
	linux-arm-kernel

On Sat, Oct 03, 2020 at 08:02:04PM +0800, Li Jun wrote:
> NXP imx8mp integrates 2 dwc3 3.30b IP and add some wakeup logic
> to support low power mode, the glue layer is for this wakeup
> functionality, which has a separated interrupt, can support
> wakeup from U3 and connect events for host, and vbus wakeup for
> device.
> 
> Signed-off-by: Li Jun <jun.li@nxp.com>
> ---
>  .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml   | 105 +++++++++++++++++++++
>  1 file changed, 105 insertions(+)
> 

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v5 1/4] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings
  2020-10-03 12:02 ` [PATCH v5 1/4] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings Li Jun
  2020-10-04 13:44   ` Krzysztof Kozlowski
@ 2020-10-06 21:10   ` Rob Herring
  1 sibling, 0 replies; 9+ messages in thread
From: Rob Herring @ 2020-10-06 21:10 UTC (permalink / raw)
  To: Li Jun
  Cc: kernel, fugang.duan, peng.fan, Anson.Huang, devicetree,
	linux-imx, shawnguo, aisheng.dong, s.hauer, qiangqing.zhang,
	peter.chen, krzk, linux-arm-kernel, gregkh, balbi, festevam,
	robh+dt, horia.geanta

On Sat, 03 Oct 2020 20:02:04 +0800, Li Jun wrote:
> NXP imx8mp integrates 2 dwc3 3.30b IP and add some wakeup logic
> to support low power mode, the glue layer is for this wakeup
> functionality, which has a separated interrupt, can support
> wakeup from U3 and connect events for host, and vbus wakeup for
> device.
> 
> Signed-off-by: Li Jun <jun.li@nxp.com>
> ---
>  .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml   | 105 +++++++++++++++++++++
>  1 file changed, 105 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v5 0/4] add NXP imx8mp usb support
  2020-10-03 12:02 [PATCH v5 0/4] add NXP imx8mp usb support Li Jun
                   ` (3 preceding siblings ...)
  2020-10-03 12:02 ` [PATCH v5 4/4] arm64: dts: imx8mp-evk: enable usb1 as host mode Li Jun
@ 2020-10-30  7:23 ` Shawn Guo
  4 siblings, 0 replies; 9+ messages in thread
From: Shawn Guo @ 2020-10-30  7:23 UTC (permalink / raw)
  To: Li Jun
  Cc: robh+dt, balbi, krzk, gregkh, s.hauer, kernel, festevam,
	linux-imx, Anson.Huang, aisheng.dong, peng.fan, fugang.duan,
	horia.geanta, qiangqing.zhang, peter.chen, devicetree,
	linux-arm-kernel

On Sat, Oct 03, 2020 at 08:02:03PM +0800, Li Jun wrote:
> NXP imx8MPlus integrates 2 indentical dwc3 3.30b IP with additional wakeup
> logic to support low power, this wakeup logic has a separated interrupt
> which can generate events with suspend clock(32K); due to SoC integration
> limitation, it only can support 32 bits DMA, so add dma-ranges property,
> 
> changes for v5
> - Remove "Items" of compatible in binding doc [1/4]
> - Add Krzysztof's R-b tag for patches [3-4/4].
> 
> changes for v4:
> - Use dma-ranges property to limit 32bits DMA, so don't need the new
>   property "xhci-64bit-support-disable".
> - Fix binding doc to pass dt_binding_check dtbs_check.
> 
> changes for v3:
> - Add dwc3 core related clocks into dwc3 core node, and glue layer driver
>   only handle the clocks(hsio and suspend) for glue block, this is to
>   match real HW.
> - Change to use property "xhci-64bit-support-disable" to disable 64bit DMA
>   as imx8mp USB integration actully can't support it, so remove platform
>   data in v2.
> - Some changes of imx8mp usb driver binding doc to address comments from Rob
> 
> Changes for v2:
> - Drop the 2 patches for new property("snps,xhci-dis-64bit-support-quirk")
>   introduction, as suggested, imply by SoC compatible string, this is done
>   by introduce dwc3 core platform data and pass the xhci_plat_priv to
>   xhci-plat for those xhci quirks, so a new patch added:
>   [1/5] usb: dwc3: add platform data to dwc3 core device to pass data.
>   this patch is based on Peter's one patch which is also in review:
>   https://patchwork.kernel.org/patch/11640945/
> - dts change, use the USB power function of TRL logic instead of a always-on
>   regulator to control vbus on/off.
> - Some changes to address Peter's command on patch [2/5].
> 
> Li Jun (4):
>   dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings
>   usb: dwc3: add imx8mp dwc3 glue layer driver
>   arm64: dtsi: imx8mp: add usb nodes
>   arm64: dts: imx8mp-evk: enable usb1 as host mode

The last two dts patches look good to me.  Ping me for applying after
the first two are accepted.

Shawn

^ permalink raw reply	[flat|nested] 9+ messages in thread

* RE: [PATCH v5 2/4] usb: dwc3: add imx8mp dwc3 glue layer driver
  2020-10-03 12:02 ` [PATCH v5 2/4] usb: dwc3: add imx8mp dwc3 glue layer driver Li Jun
@ 2020-12-04  2:07   ` Jun Li
  0 siblings, 0 replies; 9+ messages in thread
From: Jun Li @ 2020-12-04  2:07 UTC (permalink / raw)
  To: balbi
  Cc: krzk, gregkh, s.hauer, kernel, festevam, dl-linux-imx,
	Anson Huang, Aisheng Dong, Peng Fan, Andy Duan, Horia Geanta,
	Joakim Zhang, Peter Chen, devicetree, linux-arm-kernel,
	linux-usb, robh+dt, shawnguo

Hi

> -----Original Message-----
> From: Jun Li <jun.li@nxp.com>
> Sent: Saturday, October 3, 2020 8:02 PM
> To: robh+dt@kernel.org; shawnguo@kernel.org; balbi@kernel.org
> Cc: krzk@kernel.org; gregkh@linuxfoundation.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx
> <linux-imx@nxp.com>; Anson Huang <anson.huang@nxp.com>; Jun Li
> <jun.li@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com>; Peng Fan
> <peng.fan@nxp.com>; Andy Duan <fugang.duan@nxp.com>; Horia Geanta
> <horia.geanta@nxp.com>; Joakim Zhang <qiangqing.zhang@nxp.com>; Peter Chen
> <peter.chen@nxp.com>; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org
> Subject: [PATCH v5 2/4] usb: dwc3: add imx8mp dwc3 glue layer driver
> 
> imx8mp SoC integrate dwc3 3.30b IP and has some customizations to support
> low power, which has a seprated wakeup irq and additional logic to wakeup
> usb from low power mode both for host mode and device mode.
> 
> Signed-off-by: Li Jun <jun.li@nxp.com>
> ---
>  drivers/usb/dwc3/Kconfig       |  10 ++
>  drivers/usb/dwc3/Makefile      |   1 +
>  drivers/usb/dwc3/dwc3-imx8mp.c | 363
> +++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 374 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index
> 7a23045..2133acf 100644
> --- a/drivers/usb/dwc3/Kconfig
> +++ b/drivers/usb/dwc3/Kconfig
> @@ -139,4 +139,14 @@ config USB_DWC3_QCOM
>  	  for peripheral mode support.
>  	  Say 'Y' or 'M' if you have one such device.
> 
> +config USB_DWC3_IMX8MP
> +	tristate "NXP iMX8MP Platform"
> +	depends on OF && COMMON_CLK
> +	depends on (ARCH_MXC && ARM64) || COMPILE_TEST
> +	default USB_DWC3
> +	help
> +	  NXP iMX8M Plus SoC use DesignWare Core IP for USB2/3
> +	  functionality.
> +	  Say 'Y' or 'M' if you have one such device.
> +
>  endif
> diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index
> ae86da0..2259f88 100644
> --- a/drivers/usb/dwc3/Makefile
> +++ b/drivers/usb/dwc3/Makefile
> @@ -51,3 +51,4 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A)	+=
> dwc3-meson-g12a.o
>  obj-$(CONFIG_USB_DWC3_OF_SIMPLE)	+= dwc3-of-simple.o
>  obj-$(CONFIG_USB_DWC3_ST)		+= dwc3-st.o
>  obj-$(CONFIG_USB_DWC3_QCOM)		+= dwc3-qcom.o
> +obj-$(CONFIG_USB_DWC3_IMX8MP)		+= dwc3-imx8mp.o
> diff --git a/drivers/usb/dwc3/dwc3-imx8mp.c
> b/drivers/usb/dwc3/dwc3-imx8mp.c new file mode 100644 index
> 0000000..75f0042
> --- /dev/null
> +++ b/drivers/usb/dwc3/dwc3-imx8mp.c
> @@ -0,0 +1,363 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
> + *
> + * Copyright (c) 2020 NXP.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +
> +#include "core.h"
> +
> +/* USB wakeup registers */
> +#define USB_WAKEUP_CTRL			0x00
> +
> +/* Global wakeup interrupt enable, also used to clear interrupt */
> +#define USB_WAKEUP_EN			BIT(31)
> +/* Wakeup from connect or disconnect, only for superspeed */
> +#define USB_WAKEUP_SS_CONN		BIT(5)
> +/* 0 select vbus_valid, 1 select sessvld */
> +#define USB_WAKEUP_VBUS_SRC_SESS_VAL	BIT(4)
> +/* Enable signal for wake up from u3 state */
> +#define USB_WAKEUP_U3_EN		BIT(3)
> +/* Enable signal for wake up from id change */
> +#define USB_WAKEUP_ID_EN		BIT(2)
> +/* Enable signal for wake up from vbus change */
> +#define	USB_WAKEUP_VBUS_EN		BIT(1)
> +/* Enable signal for wake up from dp/dm change */
> +#define USB_WAKEUP_DPDM_EN		BIT(0)
> +
> +#define USB_WAKEUP_EN_MASK		GENMASK(5, 0)
> +
> +struct dwc3_imx8mp {
> +	struct device			*dev;
> +	struct platform_device		*dwc3;
> +	void __iomem			*glue_base;
> +	struct clk			*hsio_clk;
> +	struct clk			*suspend_clk;
> +	int				irq;
> +	bool				pm_suspended;
> +	bool				wakeup_pending;
> +};
> +
> +static void dwc3_imx8mp_wakeup_enable(struct dwc3_imx8mp *dwc3_imx) {
> +	struct dwc3	*dwc3 = platform_get_drvdata(dwc3_imx->dwc3);
> +	u32		val;
> +
> +	if (!dwc3)
> +		return;
> +
> +	val = readl(dwc3_imx->glue_base + USB_WAKEUP_CTRL);
> +
> +	if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci)
> +		val |= USB_WAKEUP_EN | USB_WAKEUP_SS_CONN |
> +		       USB_WAKEUP_U3_EN | USB_WAKEUP_DPDM_EN;
> +	else if (dwc3->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE)
> +		val |= USB_WAKEUP_EN | USB_WAKEUP_VBUS_EN |
> +		       USB_WAKEUP_VBUS_SRC_SESS_VAL;
> +
> +	writel(val, dwc3_imx->glue_base + USB_WAKEUP_CTRL); }
> +
> +static void dwc3_imx8mp_wakeup_disable(struct dwc3_imx8mp *dwc3_imx) {
> +	u32 val;
> +
> +	val = readl(dwc3_imx->glue_base + USB_WAKEUP_CTRL);
> +	val &= ~(USB_WAKEUP_EN | USB_WAKEUP_EN_MASK);
> +	writel(val, dwc3_imx->glue_base + USB_WAKEUP_CTRL); }
> +
> +static irqreturn_t dwc3_imx8mp_interrupt(int irq, void *_dwc3_imx) {
> +	struct dwc3_imx8mp	*dwc3_imx = _dwc3_imx;
> +	struct dwc3		*dwc = platform_get_drvdata(dwc3_imx->dwc3);
> +
> +	if (!dwc3_imx->pm_suspended)
> +		return IRQ_HANDLED;
> +
> +	disable_irq_nosync(dwc3_imx->irq);
> +	dwc3_imx->wakeup_pending = true;
> +
> +	if ((dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc->xhci)
> +		pm_runtime_resume(&dwc->xhci->dev);
> +	else if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE)
> +		pm_runtime_get(dwc->dev);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int dwc3_imx8mp_probe(struct platform_device *pdev) {
> +	struct device		*dev = &pdev->dev;
> +	struct device_node	*dwc3_np, *node = dev->of_node;
> +	struct dwc3_imx8mp	*dwc3_imx;
> +	int			err, irq;
> +
> +	if (!node) {
> +		dev_err(dev, "device node not found\n");
> +		return -EINVAL;
> +	}
> +
> +	dwc3_imx = devm_kzalloc(dev, sizeof(*dwc3_imx), GFP_KERNEL);
> +	if (!dwc3_imx)
> +		return -ENOMEM;
> +
> +	platform_set_drvdata(pdev, dwc3_imx);
> +
> +	dwc3_imx->dev = dev;
> +
> +	dwc3_imx->glue_base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(dwc3_imx->glue_base))
> +		return PTR_ERR(dwc3_imx->glue_base);
> +
> +	dwc3_imx->hsio_clk = devm_clk_get(dev, "hsio");
> +	if (IS_ERR(dwc3_imx->hsio_clk)) {
> +		err = PTR_ERR(dwc3_imx->hsio_clk);
> +		dev_err(dev, "Failed to get hsio clk, err=%d\n", err);
> +		return err;
> +	}
> +
> +	err = clk_prepare_enable(dwc3_imx->hsio_clk);
> +	if (err) {
> +		dev_err(dev, "Failed to enable hsio clk, err=%d\n", err);
> +		return err;
> +	}
> +
> +	dwc3_imx->suspend_clk = devm_clk_get(dev, "suspend");
> +	if (IS_ERR(dwc3_imx->suspend_clk)) {
> +		err = PTR_ERR(dwc3_imx->suspend_clk);
> +		dev_err(dev, "Failed to get suspend clk, err=%d\n", err);
> +		goto disable_hsio_clk;
> +	}
> +
> +	err = clk_prepare_enable(dwc3_imx->suspend_clk);
> +	if (err) {
> +		dev_err(dev, "Failed to enable suspend clk, err=%d\n", err);
> +		goto disable_hsio_clk;
> +	}
> +
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0) {
> +		err = irq;
> +		goto disable_clks;
> +	}
> +	dwc3_imx->irq = irq;
> +
> +	err = devm_request_threaded_irq(dev, irq, NULL, dwc3_imx8mp_interrupt,
> +					IRQF_ONESHOT, dev_name(dev), dwc3_imx);
> +	if (err) {
> +		dev_err(dev, "failed to request IRQ #%d --> %d\n", irq, err);
> +		goto disable_clks;
> +	}
> +
> +	pm_runtime_set_active(dev);
> +	pm_runtime_enable(dev);
> +	err = pm_runtime_get_sync(dev);
> +	if (err < 0)
> +		goto disable_rpm;
> +
> +	dwc3_np = of_get_child_by_name(node, "dwc3");
> +	if (!dwc3_np) {
> +		dev_err(dev, "failed to find dwc3 core child\n");
> +		goto disable_rpm;
> +	}
> +
> +	err = of_platform_populate(node, NULL, NULL, dev);
> +	if (err) {
> +		dev_err(&pdev->dev, "failed to create dwc3 core\n");
> +		goto err_node_put;
> +	}
> +
> +	dwc3_imx->dwc3 = of_find_device_by_node(dwc3_np);
> +	if (!dwc3_imx->dwc3) {
> +		dev_err(dev, "failed to get dwc3 platform device\n");
> +		err = -ENODEV;
> +		goto depopulate;
> +	}
> +	of_node_put(dwc3_np);
> +
> +	device_set_wakeup_capable(dev, true);
> +	pm_runtime_put(dev);
> +
> +	return 0;
> +
> +depopulate:
> +	of_platform_depopulate(dev);
> +err_node_put:
> +	of_node_put(dwc3_np);
> +disable_rpm:
> +	pm_runtime_disable(dev);
> +	pm_runtime_put_noidle(dev);
> +disable_clks:
> +	clk_disable_unprepare(dwc3_imx->suspend_clk);
> +disable_hsio_clk:
> +	clk_disable_unprepare(dwc3_imx->hsio_clk);
> +
> +	return err;
> +}
> +
> +static int dwc3_imx8mp_remove(struct platform_device *pdev) {
> +	struct dwc3_imx8mp *dwc3_imx = platform_get_drvdata(pdev);
> +	struct device *dev = &pdev->dev;
> +
> +	pm_runtime_get_sync(dev);
> +	of_platform_depopulate(dev);
> +
> +	clk_disable_unprepare(dwc3_imx->suspend_clk);
> +	clk_disable_unprepare(dwc3_imx->hsio_clk);
> +
> +	pm_runtime_disable(dev);
> +	pm_runtime_put_noidle(dev);
> +	platform_set_drvdata(pdev, NULL);
> +
> +	return 0;
> +}
> +
> +static int __maybe_unused dwc3_imx8mp_suspend(struct dwc3_imx8mp
> *dwc3_imx,
> +					      pm_message_t msg)
> +{
> +	if (dwc3_imx->pm_suspended)
> +		return 0;
> +
> +	/* Wakeup enable */
> +	if (PMSG_IS_AUTO(msg) || device_may_wakeup(dwc3_imx->dev))
> +		dwc3_imx8mp_wakeup_enable(dwc3_imx);
> +
> +	dwc3_imx->pm_suspended = true;
> +
> +	return 0;
> +}
> +
> +static int __maybe_unused dwc3_imx8mp_resume(struct dwc3_imx8mp
> *dwc3_imx,
> +					     pm_message_t msg)
> +{
> +	struct dwc3	*dwc = platform_get_drvdata(dwc3_imx->dwc3);
> +	int ret = 0;
> +
> +	if (!dwc3_imx->pm_suspended)
> +		return 0;
> +
> +	/* Wakeup disable */
> +	dwc3_imx8mp_wakeup_disable(dwc3_imx);
> +	dwc3_imx->pm_suspended = false;
> +
> +	if (dwc3_imx->wakeup_pending) {
> +		dwc3_imx->wakeup_pending = false;
> +		if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) {
> +			pm_runtime_mark_last_busy(dwc->dev);
> +			pm_runtime_put_autosuspend(dwc->dev);
> +		} else {
> +			/*
> +			 * Add wait for xhci switch from suspend
> +			 * clock to normal clock to detect connection.
> +			 */
> +			usleep_range(9000, 10000);
> +		}
> +		enable_irq(dwc3_imx->irq);
> +	}
> +
> +	return ret;
> +}
> +
> +static int __maybe_unused dwc3_imx8mp_pm_suspend(struct device *dev) {
> +	struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
> +	int ret;
> +
> +	ret = dwc3_imx8mp_suspend(dwc3_imx, PMSG_SUSPEND);
> +
> +	if (device_may_wakeup(dwc3_imx->dev))
> +		enable_irq_wake(dwc3_imx->irq);
> +	else
> +		clk_disable_unprepare(dwc3_imx->suspend_clk);
> +
> +	clk_disable_unprepare(dwc3_imx->hsio_clk);
> +	dev_dbg(dev, "dwc3 imx8mp pm suspend.\n");
> +
> +	return ret;
> +}
> +
> +static int __maybe_unused dwc3_imx8mp_pm_resume(struct device *dev) {
> +	struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
> +	int ret;
> +
> +	if (device_may_wakeup(dwc3_imx->dev)) {
> +		disable_irq_wake(dwc3_imx->irq);
> +	} else {
> +		ret = clk_prepare_enable(dwc3_imx->suspend_clk);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	ret = clk_prepare_enable(dwc3_imx->hsio_clk);
> +	if (ret)
> +		return ret;
> +
> +	ret = dwc3_imx8mp_resume(dwc3_imx, PMSG_RESUME);
> +
> +	pm_runtime_disable(dev);
> +	pm_runtime_set_active(dev);
> +	pm_runtime_enable(dev);
> +
> +	dev_dbg(dev, "dwc3 imx8mp pm resume.\n");
> +
> +	return ret;
> +}
> +
> +static int __maybe_unused dwc3_imx8mp_runtime_suspend(struct device
> +*dev) {
> +	struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
> +
> +	dev_dbg(dev, "dwc3 imx8mp runtime suspend.\n");
> +
> +	return dwc3_imx8mp_suspend(dwc3_imx, PMSG_AUTO_SUSPEND); }
> +
> +static int __maybe_unused dwc3_imx8mp_runtime_resume(struct device
> +*dev) {
> +	struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
> +
> +	dev_dbg(dev, "dwc3 imx8mp runtime resume.\n");
> +
> +	return dwc3_imx8mp_resume(dwc3_imx, PMSG_AUTO_RESUME); }
> +
> +static const struct dev_pm_ops dwc3_imx8mp_dev_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(dwc3_imx8mp_pm_suspend,
> dwc3_imx8mp_pm_resume)
> +	SET_RUNTIME_PM_OPS(dwc3_imx8mp_runtime_suspend,
> +			   dwc3_imx8mp_runtime_resume, NULL) };
> +
> +static const struct of_device_id dwc3_imx8mp_of_match[] = {
> +	{ .compatible = "fsl,imx8mp-dwc3", },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, dwc3_imx8mp_of_match);
> +
> +static struct platform_driver dwc3_imx8mp_driver = {
> +	.probe		= dwc3_imx8mp_probe,
> +	.remove		= dwc3_imx8mp_remove,
> +	.driver		= {
> +		.name	= "imx8mp-dwc3",
> +		.pm	= &dwc3_imx8mp_dev_pm_ops,
> +		.of_match_table	= dwc3_imx8mp_of_match,
> +	},
> +};
> +
> +module_platform_driver(dwc3_imx8mp_driver);
> +
> +MODULE_ALIAS("platform:imx8mp-dwc3");
> +MODULE_AUTHOR("jun.li@nxp.com");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("DesignWare USB3 imx8mp Glue Layer");
> --
> 2.7.4

A gentle ping.

Thanks
Li Jun


^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2020-12-04  2:08 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-03 12:02 [PATCH v5 0/4] add NXP imx8mp usb support Li Jun
2020-10-03 12:02 ` [PATCH v5 1/4] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings Li Jun
2020-10-04 13:44   ` Krzysztof Kozlowski
2020-10-06 21:10   ` Rob Herring
2020-10-03 12:02 ` [PATCH v5 2/4] usb: dwc3: add imx8mp dwc3 glue layer driver Li Jun
2020-12-04  2:07   ` Jun Li
2020-10-03 12:02 ` [PATCH v5 3/4] arm64: dtsi: imx8mp: add usb nodes Li Jun
2020-10-03 12:02 ` [PATCH v5 4/4] arm64: dts: imx8mp-evk: enable usb1 as host mode Li Jun
2020-10-30  7:23 ` [PATCH v5 0/4] add NXP imx8mp usb support Shawn Guo

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