Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU

From: Yong Wu <yong.wu@mediatek.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Joerg Roedel <joro@8bytes.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>, Evan Green <evgreen@chromium.org>,
	Tomasz Figa <tfiga@google.com>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<iommu@lists.linux-foundation.org>, <youlin.pei@mediatek.com>,
	Nicolas Boichat <drinkcat@chromium.org>, <anan.sun@mediatek.com>,
	<chao.hao@mediatek.com>, <ming-fan.chen@mediatek.com>,
	Greg Kroah-Hartman <gregkh@google.com>, <kernel-team@android.com>
Subject: Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU
Date: Tue, 6 Oct 2020 12:26:45 +0800	[thread overview]
Message-ID: <1601958405.26323.24.camel@mhfsdcap03> (raw)
In-Reply-To: <20201002111014.GE6888@pi3>

Hi Krzysztof,

On Fri, 2020-10-02 at 13:10 +0200, Krzysztof Kozlowski wrote:
> On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote:
> > This patch adds decriptions for mt8192 IOMMU and SMI.
> > 
> > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> > table format. The M4U-SMI HW diagram is as below:
> > 
> >                           EMI
> >                            |
> >                           M4U
> >                            |
> >                       ------------
> >                        SMI Common
> >                       ------------
> >                            |
> >   +-------+------+------+----------------------+-------+
> >   |       |      |      |       ......         |       |
> >   |       |      |      |                      |       |
> > larb0   larb1  larb2  larb4     ......      larb19   larb20
> > disp0   disp1   mdp    vdec                   IPE      IPE
> > 
> > All the connections are HW fixed, SW can NOT adjust it.
> > 
> > mt8192 M4U support 0~16GB iova range. we preassign different engines
> > into different iova ranges:
> > 
> > domain-id  module     iova-range                  larbs
> >    0       disp        0 ~ 4G                      larb0/1
> >    1       vcodec      4G ~ 8G                     larb4/5/7
> >    2       cam/mdp     8G ~ 12G             larb2/9/11/13/14/16/17/18/19/20
> >    3       CCU0    0x4000_0000 ~ 0x43ff_ffff     larb13: port 9/10
> >    4       CCU1    0x4400_0000 ~ 0x47ff_ffff     larb14: port 4/5
> > 
> > The iova range for CCU0/1(camera control unit) is HW requirement.
> > 
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > ---
> >  .../bindings/iommu/mediatek,iommu.yaml        |   9 +-
> >  .../mediatek,smi-common.yaml                  |   5 +-
> >  .../memory-controllers/mediatek,smi-larb.yaml |   3 +-
> >  include/dt-bindings/memory/mt8192-larb-port.h | 239 ++++++++++++++++++
> >  4 files changed, 251 insertions(+), 5 deletions(-)
> >  create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h
> 
> I see it depends on previous patches but does it have to be within one
> commit? Is it not bisectable? The memory changes/bindings could go via
> memory tree if this is split.

Thanks for the view.

I can split this into two patchset in next version, one is for iommu and
the other is for smi.

Only the patch [18/24] change both the code(iommu and smi). I don't plan
to split it, and the smi patch[24/24] don't depend on it(won't
conflict).

since 18/24 also touch the smi code, I expect it could get Acked-by from
you or Matthias, then Joerg could take it.

Thanks.

> 
> Best regards,
> Krzysztof