From: Harsha <harsha.harsha@xilinx.com>
To: <herbert@gondor.apana.org.au>, <davem@davemloft.net>,
<linux-crypto@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<michal.simek@xilinx.com>, <linux-arm-kernel@lists.infradead.org>,
<robh+dt@kernel.org>, <devicetree@vger.kernel.org>
Cc: <saratcha@xilinx.com>, <harshj@xilinx.com>,
Harsha <harsha.harsha@xilinx.com>
Subject: [RFC PATCH 2/6] firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality
Date: Tue, 30 Nov 2021 14:24:21 +0530 [thread overview]
Message-ID: <1638262465-10790-3-git-send-email-harsha.harsha@xilinx.com> (raw)
In-Reply-To: <1638262465-10790-1-git-send-email-harsha.harsha@xilinx.com>
This patch adds zynqmp_pm_sha_hash API in the ZynqMP firmware to compute
SHA3 hash of given data.
Signed-off-by: Harsha <harsha.harsha@xilinx.com>
---
drivers/firmware/xilinx/zynqmp.c | 26 ++++++++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++
2 files changed, 34 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 3dd45a7..a84c5ea 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -1117,6 +1117,32 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out)
EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);
/**
+ * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash
+ * @address: Address of the data/ Address of output buffer where
+ * hash should be stored.
+ * @size: Size of the data.
+ * @flags:
+ * BIT(0) - for initializing csudma driver and SHA3(Here address
+ * and size inputs can be NULL).
+ * BIT(1) - to call Sha3_Update API which can be called multiple
+ * times when data is not contiguous.
+ * BIT(2) - to get final hash of the whole updated data.
+ * Hash will be overwritten at provided address with
+ * 48 bytes.
+ *
+ * Return: Returns status, either success or error code.
+ */
+int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags)
+{
+ u32 lower_addr = lower_32_bits(address);
+ u32 upper_addr = upper_32_bits(address);
+
+ return zynqmp_pm_invoke_fn(PM_SECURE_SHA, upper_addr, lower_addr,
+ size, flags, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash);
+
+/**
* zynqmp_pm_system_shutdown - PM call to request a system shutdown or restart
* @type: Shutdown or restart? 0 for shutdown, 1 for restart
* @subtype: Specifies which system should be restarted or shut down
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 47fd4e5..38ef708 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -78,6 +78,7 @@ enum pm_api_id {
PM_FPGA_LOAD = 22,
PM_FPGA_GET_STATUS = 23,
PM_GET_CHIPID = 24,
+ PM_SECURE_SHA = 26,
PM_PINCTRL_REQUEST = 28,
PM_PINCTRL_RELEASE = 29,
PM_PINCTRL_GET_FUNCTION = 30,
@@ -410,6 +411,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
const u32 qos,
const enum zynqmp_pm_request_ack ack);
int zynqmp_pm_aes_engine(const u64 address, u32 *out);
+int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
int zynqmp_pm_fpga_get_status(u32 *value);
int zynqmp_pm_write_ggs(u32 index, u32 value);
@@ -581,6 +583,12 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
return -ENODEV;
}
+static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
+ const u32 flags)
+{
+ return -ENODEV;
+}
+
static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
const u32 flags)
{
--
1.8.2.1
next prev parent reply other threads:[~2021-11-30 8:54 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 8:54 [RFC PATCH 0/6] crypto: Add Xilinx ZynqMP SHA3 driver support Harsha
2021-11-30 8:54 ` [RFC PATCH 1/6] drivers: crypto: Updated Makefile for xilinx subdirectory Harsha
2021-11-30 8:54 ` Harsha [this message]
2021-11-30 8:54 ` [RFC PATCH 3/6] dt-bindings: crypto: Add bindings for ZynqMP SHA3 driver Harsha
2021-12-07 21:30 ` Rob Herring
2021-12-08 4:17 ` Harsha Harsha
2021-12-08 17:12 ` Rob Herring
2021-12-09 7:20 ` Harsha Harsha
2021-11-30 8:54 ` [RFC PATCH 4/6] arm64: dts: zynqmp: Add Xilinx SHA3 node Harsha
2021-11-30 8:54 ` [RFC PATCH 5/6] crypto: xilinx: Add Xilinx SHA3 driver Harsha
2021-11-30 14:14 ` Randy Dunlap
2021-11-30 16:38 ` Harsha Harsha
2021-11-30 8:54 ` [RFC PATCH 6/6] MAINTAINERS: Add maintainer for Xilinx ZynqMP " Harsha
[not found] <1638213623-32613-1-git-send-email-harsha.harsha@xilinx.com>
[not found] ` <1638213623-32613-3-git-send-email-harsha.harsha@xilinx.com>
2021-12-03 13:20 ` [RFC PATCH 2/6] firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality Michal Simek
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