From: Rajeev Nandan <quic_rajeevny@quicinc.com>
To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
freedreno@lists.freedesktop.org, devicetree@vger.kernel.org
Cc: Rajeev Nandan <quic_rajeevny@quicinc.com>,
linux-kernel@vger.kernel.org, sean@poorly.run,
robdclark@gmail.com, robh+dt@kernel.org, robh@kernel.org,
quic_abhinavk@quicinc.com, quic_kalyant@quicinc.com,
quic_mkrishn@quicinc.com, jonathan@marek.ca,
dmitry.baryshkov@linaro.org, airlied@linux.ie, daniel@ffwll.ch,
swboyd@chromium.org
Subject: [v2 2/3] drm/msm/dsi: Add dsi phy tuning configuration support
Date: Mon, 10 Jan 2022 18:25:36 +0530 [thread overview]
Message-ID: <1641819337-17037-3-git-send-email-quic_rajeevny@quicinc.com> (raw)
In-Reply-To: <1641819337-17037-1-git-send-email-quic_rajeevny@quicinc.com>
Add support for MSM DSI PHY tuning configuration. Current design is
to support drive strength and drive level/amplitude tuning for
10nm PHY version, but this can be extended to other PHY versions.
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
---
Changes in v2:
- New.
- Split into generic code and 10nm-specific part (Dmitry Baryshkov)
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 3 +++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 16 ++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 8c65ef6..ee3739d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -739,6 +739,9 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
}
}
+ if (phy->cfg->ops.tuning_cfg_init)
+ phy->cfg->ops.tuning_cfg_init(phy);
+
ret = dsi_phy_regulator_init(phy);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index b91303a..b559a2b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -25,6 +25,7 @@ struct msm_dsi_phy_ops {
void (*save_pll_state)(struct msm_dsi_phy *phy);
int (*restore_pll_state)(struct msm_dsi_phy *phy);
bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable);
+ void (*tuning_cfg_init)(struct msm_dsi_phy *phy);
};
struct msm_dsi_phy_cfg {
@@ -81,6 +82,20 @@ struct msm_dsi_dphy_timing {
#define DSI_PIXEL_PLL_CLK 1
#define NUM_PROVIDED_CLKS 2
+#define DSI_LANE_MAX 5
+
+/**
+ * struct msm_dsi_phy_tuning_cfg - Holds PHY tuning config parameters.
+ * @rescode_offset_top: Offset for pull-up legs rescode.
+ * @rescode_offset_bot: Offset for pull-down legs rescode.
+ * @vreg_ctrl: vreg ctrl to drive LDO level
+ */
+struct msm_dsi_phy_tuning_cfg {
+ u8 rescode_offset_top[DSI_LANE_MAX];
+ u8 rescode_offset_bot[DSI_LANE_MAX];
+ u8 vreg_ctrl;
+};
+
struct msm_dsi_phy {
struct platform_device *pdev;
void __iomem *base;
@@ -98,6 +113,7 @@ struct msm_dsi_phy {
struct msm_dsi_dphy_timing timing;
const struct msm_dsi_phy_cfg *cfg;
+ struct msm_dsi_phy_tuning_cfg tuning_cfg;
enum msm_dsi_phy_usecase usecase;
bool regulator_ldo_mode;
--
2.7.4
next prev parent reply other threads:[~2022-01-10 12:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-10 12:55 [v2 0/3] drm/msm/dsi: Add 10nm dsi phy tuning configuration support Rajeev Nandan
2022-01-10 12:55 ` [v2 1/3] dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties Rajeev Nandan
2022-01-10 14:06 ` Dmitry Baryshkov
2022-01-10 17:28 ` Rob Herring
2022-01-12 15:17 ` Rajeev Nandan
2022-01-10 16:48 ` Rob Herring
2022-01-10 12:55 ` Rajeev Nandan [this message]
2022-01-10 14:12 ` [v2 2/3] drm/msm/dsi: Add dsi phy tuning configuration support Dmitry Baryshkov
2022-01-12 16:09 ` Rajeev Nandan
2022-01-12 17:08 ` Dmitry Baryshkov
2022-01-13 11:34 ` Rajeev Nandan
2022-01-10 12:55 ` [v2 3/3] drm/msm/dsi: Add 10nm " Rajeev Nandan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1641819337-17037-3-git-send-email-quic_rajeevny@quicinc.com \
--to=quic_rajeevny@quicinc.com \
--cc=airlied@linux.ie \
--cc=daniel@ffwll.ch \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=freedreno@lists.freedesktop.org \
--cc=jonathan@marek.ca \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=quic_abhinavk@quicinc.com \
--cc=quic_kalyant@quicinc.com \
--cc=quic_mkrishn@quicinc.com \
--cc=robdclark@gmail.com \
--cc=robh+dt@kernel.org \
--cc=robh@kernel.org \
--cc=sean@poorly.run \
--cc=swboyd@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).