From: Johan Jonker <jbx6244@gmail.com>
To: cl@rock-chips.com, heiko@sntech.de
Cc: robh+dt@kernel.org, jagan@amarulasolutions.com, wens@csie.org,
uwe@kleine-koenig.org, mail@david-bauer.net,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
jensenhuang@friendlyarm.com, michael@amarulasolutions.com,
cnsztl@gmail.com, devicetree@vger.kernel.org,
ulf.hansson@linaro.org, linux-mmc@vger.kernel.org,
gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
linux-i2c@vger.kernel.org, jay.xu@rock-chips.com,
shawn.lin@rock-chips.com, david.wu@rock-chips.com,
zhangqing@rock-chips.com, huangtao@rock-chips.com,
wim@linux-watchdog.org, linux@roeck-us.net, jamie@jamieiles.com,
linux-watchdog@vger.kernel.org
Subject: Re: [PATCH v2 6/7] arm64: dts: rockchip: add core dtsi for RK3568 SoC
Date: Tue, 27 Apr 2021 09:41:40 +0200 [thread overview]
Message-ID: <16908f63-4e20-ba1b-3b5c-39b4c4db242b@gmail.com> (raw)
In-Reply-To: <20210425094439.25895-1-cl@rock-chips.com>
On 4/25/21 11:44 AM, cl@rock-chips.com wrote:
> From: Liang Chen <cl@rock-chips.com>
>
> RK3568 is a high-performance and low power quad-core application processor
> designed for personal mobile internet device and AIoT equipments. This patch
> add basic core dtsi file for it.
>
> We use scmi_clk for cortex-a55 instead of standard ARMCLK, so that
> kernel/uboot/rtos can change cpu clk with the same code in ATF, and we will
> enalbe a special high-performacne PLL when high frequency is required. The
> smci_clk code is in ATF, and clkid for cpu is 0, as below:
>
> cpu0: cpu@0 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x0>;
> clocks = <&scmi_clk 0>;
> };
>
> Signed-off-by: Liang Chen <cl@rock-chips.com>
> ---
> .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 3119 +++++++++++++++++
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 812 +++++
> 2 files changed, 3931 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> new file mode 100644
> index 000000000000..94ee3c2c38af
> --- /dev/null
[..]
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> new file mode 100644
> index 000000000000..66cb50218ca1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -0,0 +1,812 @@
[..]
> +
> + pmugrf: syscon@fdc20000 {
> + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
TODO:
> + reg = <0x0 0xfdc20000 0x0 0x10000>;
> +
> + reboot_mode: reboot-mode {
> + compatible = "syscon-reboot-mode";
> + mode-bootloader = <BOOT_BL_DOWNLOAD>;
> + mode-fastboot = <BOOT_FASTBOOT>;
> + mode-loader = <BOOT_BL_DOWNLOAD>;
> + mode-normal = <BOOT_NORMAL>;
> + mode-recovery = <BOOT_RECOVERY>;
> + offset = <0x200>;
> + };
> + };
> +
> + grf: syscon@fdc60000 {
> + compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
TODO:
> + reg = <0x0 0xfdc60000 0x0 0x10000>;
> + };
> +
> + pmucru: clock-controller@fdd00000 {
> + compatible = "rockchip,rk3568-pmucru";
> + reg = <0x0 0xfdd00000 0x0 0x1000>;
> + rockchip,grf = <&grf>;
> + rockchip,pmugrf = <&pmugrf>;
clock-controller@fdd00000: 'rockchip,grf', 'rockchip,pmugrf' do not
match any of the regexes: 'pinctrl-[0-9]+'
Currently clk.c has only support for:
ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
"rockchip,grf");
Manufacturer tree:
ctx->pmugrf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
"rockchip,pmugrf");
case branch_muxpmugrf:
clk = rockchip_clk_register_muxgrf(list->name,
list->parent_names, list->num_parents,
flags, ctx->pmugrf, list->muxdiv_offset,
list->mux_shift, list->mux_width,
list->mux_flags);
break;
MUXPMUGRF(SCLK_32K_IOE, "clk_32k_ioe", clk_32k_ioe_p, 0,
RK3568_PMU_GRF_SOC_CON0, 0, 1, MFLAGS)
Do we need a fix?
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + cru: clock-controller@fdd20000 {
> + compatible = "rockchip,rk3568-cru";
> + reg = <0x0 0xfdd20000 0x0 0x1000>;
> + rockchip,grf = <&grf>;
clock-controller@fdd20000: 'assigned-clock-parents',
'assigned-clock-rates', 'assigned-clocks', 'rockchip,grf' do not match
any of the regexes:
Add more properties to rockchip,rk3568-cru.yaml
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> +
> + assigned-clocks =
> + <&pmucru CLK_RTC_32K>, <&pmucru PLL_PPLL>,
> + <&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
> + <&cru PLL_GPLL>, <&cru ACLK_BUS>,
> + <&cru PCLK_BUS>, <&cru ACLK_TOP_HIGH>,
> + <&cru ACLK_TOP_LOW>, <&cru HCLK_TOP>,
> + <&cru PCLK_TOP>, <&cru ACLK_PERIMID>,
> + <&cru HCLK_PERIMID>, <&cru PLL_NPLL>,
> + <&cru ACLK_PIPE>, <&cru PCLK_PIPE>,
> + <&cru ACLK_VOP>;
> + assigned-clock-rates =
> + <32768>, <200000000>,
> + <100000000>, <1000000000>,
> + <1188000000>, <150000000>,
> + <100000000>, <500000000>,
> + <400000000>, <150000000>,
> + <100000000>, <300000000>,
> + <150000000>, <1200000000>,
> + <400000000>, <100000000>,
> + <500000000>;
> + assigned-clock-parents =
> + <&pmucru CLK_RTC32K_FRAC>;
> + };
next prev parent reply other threads:[~2021-04-27 7:41 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-25 9:42 [PATCH v2 0/7] arm64: dts: rockchip: add basic dtsi/dts files for RK3568 SoC cl
2021-04-25 9:42 ` [PATCH v2 1/7] dt-bindings: i2c: i2c-rk3x: add description for rk3568 cl
2021-04-25 9:42 ` [PATCH v2 2/7] dt-bindings: serial: snps-dw-apb-uart: " cl
2021-04-25 9:42 ` [PATCH v2 3/7] dt-bindings: mmc: rockchip-dw-mshc: " cl
2021-04-25 9:42 ` [PATCH v2 4/7] dt-bindings: watchdog: dw-wdt: " cl
2021-04-25 9:44 ` [PATCH v2 5/7] arm64: dts: rockchip: add generic pinconfig settings used by most Rockchip socs cl
2021-04-25 9:44 ` [PATCH v2 6/7] arm64: dts: rockchip: add core dtsi for RK3568 SoC cl
2021-04-25 10:28 ` Marc Zyngier
2021-04-26 9:21 ` 陈亮
2021-04-26 12:16 ` Johan Jonker
2021-04-27 3:45 ` Kever Yang
2021-04-27 7:48 ` Heiko Stübner
2021-04-27 7:41 ` Johan Jonker [this message]
2021-04-27 8:07 ` Heiko Stübner
2021-04-28 3:51 ` 陈亮
2021-04-25 9:44 ` [PATCH v2 7/7] arm64: dts: rockchip: add basic dts for RK3568 EVB cl
2021-04-27 7:50 ` Heiko Stübner
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