From: Gabriel FERNANDEZ <gabriel.fernandez@st.com>
To: Rob Herring <robh@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Lee Jones <lee.jones@linaro.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre TORGUE <alexandre.torgue@st.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"gabriel.fernandez.st@gmail.com" <gabriel.fernandez.st@gmail.com>,
Olivier BIDEAU <olivier.bideau@st.com>
Subject: Re: [PATCH 01/14] dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings
Date: Mon, 5 Feb 2018 07:01:29 +0000 [thread overview]
Message-ID: <19273eb9-0c8c-cd2a-d100-f25f25e93234@st.com> (raw)
In-Reply-To: <20180205042238.64xjrrguls2drtrg@rob-hp-laptop>
Hi Rob,
Thanks for reviewing.
On 02/05/2018 07:09 AM, Rob Herring wrote:
> On Fri, Feb 02, 2018 at 03:03:29PM +0100, gabriel.fernandez@st.com wrote:
>> From: Gabriel Fernandez <gabriel.fernandez@st.com>
>>
>> The RCC block is responsible of the management of the clock and reset
>> generation for the complete circuit.
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
>> ---
>> .../devicetree/bindings/mfd/st,stm32-rcc.txt | 85 ++++++++++++++++++++++
>> 1 file changed, 85 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt
>> new file mode 100644
>> index 0000000..28017a1
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt
>> @@ -0,0 +1,85 @@
>> +STMicroelectronics STM32 Peripheral Reset Clock Controller
>> +==========================================================
>> +
>> +The RCC IP is both a reset and a clock controller.
>> +
>> +Please also refer to reset.txt for common reset controller binding usage.
>> +
>> +Please also refer to clock-bindings.txt for common clock controller
>> +binding usage.
>> +
>> +
>> +Required properties:
>> +- compatible: "simple-mfd", "syscon"
>
>> +- reg: should be register base and length as documented in the datasheet
>> +
>> +- Sub-nodes:
>> + - compatible: "st,stm32mp1-rcc-clk"
>> + - #clock-cells: 1, device nodes should specify the clock in their
>> + "clocks" property, containing a phandle to the clock device node,
>> + an index specifying the clock to use.
>> +
>> + - compatible: "st,stm32mp1-rcc-rst"
>> + - #reset-cells: Shall be 1
>> +
>> +Example:
>> + rcc: rcc@50000000 {
>> + compatible = "syscon", "simple-mfd";
>> + reg = <0x50000000 0x1000>;
>> +
>> + rcc_clk: rcc-clk@50000000 {
>> + #clock-cells = <1>;
>> + compatible = "st,stm32mp1-rcc-clk";
>> + };
>> +
>> + rcc_rst: rcc-reset@50000000 {
> You should not have the same unit-address twice.
>
> IMO, this should just be:
>
> rcc: rcc@50000000 {
> compatible = "st-stm32mp1-rcc";
> reg = <0x50000000 0x1000>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> };
>
> There's no reason a node can't provide more than 1 function.
RCC is an dedicated IP for clocks and resets, but also for power
management (patches will be sent later)
Then i need to probe 3 drivers with same IP.
It's also a way to avoid use of 'CLK_OF_DECLARE_DRIVER' and i need it to
probe the 3th driver.
BR
Gabriel
>
>
>> + #reset-cells = <1>;
>> + compatible = "st,stm32mp1-rcc-rst";
>> + };
>> + };
>> +
>> +Specifying clocks
>> +=================
>> +
>> +All available clocks are defined as preprocessor macros in
>> +dt-bindings/clock/stm32mp1-clks.h header and can be used in device
>> +tree sources.
>> +
>> +Example:
>> +
>> + /* Accessing DMA1 clock */
>> + ... {
>> + clocks = <&rcc_clk DMA1>
>> + };
>> +
>> + /* Accessing SPI6 kernel clock */
>> + ... {
>> + clocks = <&rcc_clk SPI6_K>
>> + };
> Other than the path to header, the clock binding explains all this. No
> need to duplicate here.
ok
>> +
>> +Specifying softreset control of devices
>> +=======================================
>> +
>> +Device nodes should specify the reset channel required in their "resets"
>> +property, containing a phandle to the reset device node and an index specifying
>> +which channel to use.
>> +The index is the bit number within the RCC registers bank, starting from RCC
>> +base address.
>> +It is calculated as: index = register_offset / 4 * 32 + bit_offset.
>> +Where bit_offset is the bit offset within the register.
>> +
>> +For example on STM32MP1, for LTDC reset:
>> + ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
>> + = 0x180 / 4 * 32 + 0 = 3072
>> +
>> +The list of valid indices for STM32MP1 is available in:
>> +include/dt-bindings/reset-controller/stm32mp1-resets.h
>> +
>> +This file implements defines like:
>> +#define LTDC_R 3072
>> +
>> +example:
>> +
>> + ltdc {
>> + resets = <&rcc_rst LTDC_R>;
>> + };
>> --
>> 1.9.1
>>
next prev parent reply other threads:[~2018-02-05 7:01 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-02 14:03 [PATCH 00/14] Introduce STM32MP1 clock driver gabriel.fernandez-qxv4g6HH51o
2018-02-02 14:03 ` [PATCH 02/14] dt-bindings: clock: add STM32MP1 clocks gabriel.fernandez
[not found] ` <1517580222-23301-3-git-send-email-gabriel.fernandez-qxv4g6HH51o@public.gmane.org>
2018-02-05 6:09 ` Rob Herring
2018-02-05 7:02 ` Gabriel FERNANDEZ
2018-02-02 14:03 ` [PATCH 04/14] clk: stm32mp1: add MP1 gate for osc hse/hsi/csi oscillators gabriel.fernandez
[not found] ` <1517580222-23301-1-git-send-email-gabriel.fernandez-qxv4g6HH51o@public.gmane.org>
2018-02-02 14:03 ` [PATCH 01/14] dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings gabriel.fernandez-qxv4g6HH51o
2018-02-05 6:09 ` Rob Herring
2018-02-05 7:01 ` Gabriel FERNANDEZ [this message]
2018-02-07 18:03 ` Rob Herring
2018-02-13 14:36 ` Gabriel FERNANDEZ
2018-02-05 7:15 ` Gabriel FERNANDEZ
2018-02-02 14:03 ` [PATCH 03/14] clk: stm32mp1: Introduce STM32MP1 clock driver gabriel.fernandez-qxv4g6HH51o
2018-02-02 14:03 ` [PATCH 05/14] clk: stm32mp1: add Source Clocks for PLLs gabriel.fernandez-qxv4g6HH51o
2018-02-02 14:03 ` [PATCH 06/14] clk: stm32mp1: add PLL clocks gabriel.fernandez-qxv4g6HH51o
2018-02-02 14:03 ` [PATCH 07/14] clk: stm32mp1: add Post-dividers for PLL gabriel.fernandez-qxv4g6HH51o
2018-02-02 14:03 ` [PATCH 08/14] clk: stm32mp1: add Sub System clocks gabriel.fernandez-qxv4g6HH51o
2018-02-02 14:03 ` [PATCH 11/14] clk: stm32mp1: add Kernel clocks gabriel.fernandez-qxv4g6HH51o
2018-02-02 14:03 ` [PATCH 12/14] clk: stm32mp1: add RTC clock gabriel.fernandez-qxv4g6HH51o
2018-02-02 14:03 ` [PATCH 09/14] clk: stm32mp1: add Kernel timers gabriel.fernandez
2018-02-02 14:03 ` [PATCH 10/14] clk: stm32mp1: add Peripheral clocks gabriel.fernandez
2018-02-02 14:03 ` [PATCH 13/14] clk: stm32mp1: add MCO clocks gabriel.fernandez
2018-02-02 14:03 ` [PATCH 14/14] clk: stm32mp1: add Debug clocks gabriel.fernandez
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=19273eb9-0c8c-cd2a-d100-f25f25e93234@st.com \
--to=gabriel.fernandez@st.com \
--cc=alexandre.torgue@st.com \
--cc=devicetree@vger.kernel.org \
--cc=gabriel.fernandez.st@gmail.com \
--cc=lee.jones@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mcoquelin.stm32@gmail.com \
--cc=mturquette@baylibre.com \
--cc=olivier.bideau@st.com \
--cc=robh@kernel.org \
--cc=sboyd@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).