From: Alexandre Belloni <alexandre.belloni@free-electrons.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org,
Alexandre Belloni <alexandre.belloni@free-electrons.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: [PATCH v2 06/13] dt-bindings: mips: Add bindings for Microsemi SoCs
Date: Fri, 8 Dec 2017 16:46:11 +0100 [thread overview]
Message-ID: <20171208154618.20105-7-alexandre.belloni@free-electrons.com> (raw)
In-Reply-To: <20171208154618.20105-1-alexandre.belloni@free-electrons.com>
Add bindings for Microsemi SoCs. Currently only Ocelot is supported.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
Documentation/devicetree/bindings/mips/mscc.txt | 46 +++++++++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
new file mode 100644
index 000000000000..1bb578b9d135
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -0,0 +1,46 @@
+* Microsemi MIPS CPUs
+
+Boards with a SoC of the Microsemi MIPS family shall have the following
+properties:
+
+Required properties:
+- compatible: "mscc,ocelot"
+- mips-hpt-frequency: CPU counter frequency.
+
+
+* Other peripherals:
+
+o CPU chip regs:
+
+The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
+functionalities: chip ID, general purpose register for software use, reset
+controller, hardware status and configuration, efuses.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@71070000 {
+ compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
+ reg = <0x71070000 0x1c>;
+ };
+
+
+o CPU system control:
+
+The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
+the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
+endianess, CPU bus control, CPU status.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@70000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x70000000 0x2c>;
+ };
+
+
--
2.15.1
next prev parent reply other threads:[~2017-12-08 15:46 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-08 15:46 [PATCH v2 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni
2017-12-08 15:46 ` Alexandre Belloni [this message]
2017-12-13 0:44 ` [PATCH v2 06/13] dt-bindings: mips: Add bindings for Microsemi SoCs Rob Herring
2017-12-08 15:46 ` [PATCH v2 07/13] dt-bindings: power: reset: Document ocelot-reset binding Alexandre Belloni
[not found] ` <20171208154618.20105-8-alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-15 20:23 ` Rob Herring
2017-12-15 22:07 ` Alexandre Belloni
2017-12-17 16:59 ` [PATCH v2 00/13] MIPS: add support for the Microsemi MIPS SoCs PrasannaKumar Muralidharan
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