From: David Miller <davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org>
To: rmk+kernel-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org
Cc: andrew-g2DYL2Zd6BY@public.gmane.org,
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Subject: Re: [PATCH 1/2] net: dsa: allow XAUI phy interface mode
Date: Wed, 13 Dec 2017 14:59:34 -0500 (EST) [thread overview]
Message-ID: <20171213.145934.2221372837492956535.davem@davemloft.net> (raw)
In-Reply-To: <E1eOgsk-0001AU-5z-eh5Bv4kxaXIk46pC+1QYvQNdhmdF6hFW@public.gmane.org>
From: Russell King <rmk+kernel-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
Date: Tue, 12 Dec 2017 09:29:46 +0000
> XGMII is a 32-bit bus plus two clock signals per direction. XAUI is
> four serial lanes per direction. The 88e6190 supports XAUI but not
> XGMII as it doesn't have enough pins. The same is true of 88e6176.
>
> Match on PHY_INTERFACE_MODE_XAUI for the XAUI port type, but keep
> accepting XGMII for backwards compatibility.
>
> Signed-off-by: Russell King <rmk+kernel-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
Applied.
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prev parent reply other threads:[~2017-12-13 19:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-12 9:29 [PATCH 1/2] net: dsa: allow XAUI phy interface mode Russell King
[not found] ` <E1eOgsk-0001AU-5z-eh5Bv4kxaXIk46pC+1QYvQNdhmdF6hFW@public.gmane.org>
2017-12-12 11:44 ` Andrew Lunn
2017-12-13 19:59 ` David Miller [this message]
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