From: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
Cc: Lorenzo Pieralisi
<lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>,
Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
nsekhar-l0cyMroinI0@public.gmane.org
Subject: Re: [PATCH v2 2/3] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7
Date: Wed, 20 Dec 2017 12:57:15 -0600 [thread overview]
Message-ID: <20171220185715.j5h7dlricom6kuiz@rob-hp-laptop> (raw)
In-Reply-To: <20171219085823.8695-3-kishon-l0cyMroinI0@public.gmane.org>
On Tue, Dec 19, 2017 at 02:28:22PM +0530, Kishon Vijay Abraham I wrote:
> Add syscon properties required for configuring PCIe in x2 lane mode.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
> Signed-off-by: Sekhar Nori <nsekhar-l0cyMroinI0@public.gmane.org>
> ---
> Documentation/devicetree/bindings/pci/ti-pci.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
> index 82cb875e4cec..bfbc77ac7355 100644
> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
> @@ -13,6 +13,12 @@ PCIe DesignWare Controller
> - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
> where <X> is the instance number of the pcie from the HW spec.
> - num-lanes as specified in ../designware-pcie.txt
> + - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control
> + module and the register offset to specify 1 lane or
> + 2 lane.
> + - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
> + module and the register offset to specify lane
> + selection.
Adding a property for every syscon register doesn't really scale and
doesn't work if the register layout changes.
Rob
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next prev parent reply other threads:[~2017-12-20 18:57 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-19 8:58 [PATCH v2 0/3] PCI: dra7xx: Support PCIe x2 lane mode Kishon Vijay Abraham I
2017-12-19 8:58 ` [PATCH v2 1/3] dt-bindings: PCI: dra7xx: Add SoC specific compatible strings Kishon Vijay Abraham I
2017-12-19 8:58 ` [PATCH v2 2/3] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 Kishon Vijay Abraham I
[not found] ` <20171219085823.8695-3-kishon-l0cyMroinI0@public.gmane.org>
2017-12-20 18:57 ` Rob Herring [this message]
2017-12-22 6:03 ` Kishon Vijay Abraham I
2017-12-22 18:24 ` Tony Lindgren
2017-12-26 17:46 ` Rob Herring
[not found] ` <CAL_Jsq+f3u0yvftvESKDiDF76bUiwr9hZED3ZZ75=qMMr6RL1g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-12-26 18:10 ` Tony Lindgren
[not found] ` <20171226181009.GE3875-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
2017-12-27 6:40 ` Kishon Vijay Abraham I
2017-12-19 8:58 ` [PATCH v2 3/3] PCI: dra7xx: Enable x2 mode support for dra74x, dra76x and dra72x Kishon Vijay Abraham I
2018-02-26 10:30 ` Lorenzo Pieralisi
2018-02-28 12:04 ` Kishon Vijay Abraham I
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