From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Cercueil Subject: [PATCH 7/7] MIPS: jz4740: Drop old platform reset code Date: Thu, 28 Dec 2017 17:29:39 +0100 Message-ID: <20171228162939.3928-8-paul@crapouillou.net> References: <20171228162939.3928-1-paul@crapouillou.net> Return-path: In-Reply-To: <20171228162939.3928-1-paul@crapouillou.net> Sender: linux-kernel-owner@vger.kernel.org To: Ralf Baechle , Rob Herring , Mark Rutland , Wim Van Sebroeck , Guenter Roeck Cc: devicetree@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Paul Cercueil List-Id: devicetree@vger.kernel.org This work is now performed by the watchdog driver directly. Signed-off-by: Paul Cercueil --- arch/mips/jz4740/reset.c | 31 ------------------------------- 1 file changed, 31 deletions(-) diff --git a/arch/mips/jz4740/reset.c b/arch/mips/jz4740/reset.c index 67780c4b6573..5bf0cf44b55f 100644 --- a/arch/mips/jz4740/reset.c +++ b/arch/mips/jz4740/reset.c @@ -12,18 +12,9 @@ * */ -#include -#include -#include -#include - #include -#include -#include - #include "reset.h" -#include "clock.h" static void jz4740_halt(void) { @@ -36,29 +27,7 @@ static void jz4740_halt(void) } } -#define JZ_REG_WDT_DATA 0x00 -#define JZ_REG_WDT_COUNTER_ENABLE 0x04 -#define JZ_REG_WDT_COUNTER 0x08 -#define JZ_REG_WDT_CTRL 0x0c - -static void jz4740_restart(char *command) -{ - void __iomem *wdt_base = ioremap(JZ4740_WDT_BASE_ADDR, 0x0f); - - jz4740_timer_enable_watchdog(); - - writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE); - - writew(0, wdt_base + JZ_REG_WDT_COUNTER); - writew(0, wdt_base + JZ_REG_WDT_DATA); - writew(BIT(2), wdt_base + JZ_REG_WDT_CTRL); - - writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE); - jz4740_halt(); -} - void jz4740_reset_init(void) { - _machine_restart = jz4740_restart; _machine_halt = jz4740_halt; } -- 2.11.0