* Re: [PATCH RFC 2/4] dt-bindings/interrupt-controller: pdc: descibe PDC device binding
2018-01-23 17:56 ` [PATCH RFC 2/4] dt-bindings/interrupt-controller: pdc: descibe PDC device binding Lina Iyer
@ 2018-01-23 18:09 ` Sudeep Holla
2018-01-23 18:46 ` Lina Iyer
2018-01-24 14:24 ` Marc Zyngier
2018-01-30 15:20 ` Rob Herring
2 siblings, 1 reply; 5+ messages in thread
From: Sudeep Holla @ 2018-01-23 18:09 UTC (permalink / raw)
To: Lina Iyer
Cc: tglx, jason, marc.zyngier, Sudeep Holla, linux-kernel,
linux-arm-msm, sboyd, rnayak, asathyak, devicetree
On 23/01/18 17:56, Lina Iyer wrote:
> From: Archana Sathyakumar <asathyak@codeaurora.org>
>
> Add device binding documentation for the PDC Interrupt controller on
> QCOM SoC's like the SDM845. The interrupt-controller can be used to
> sense edge low interrupts and wakeup interrupts when the GIC is
> non-operational.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
> Signed-off-by: Lina Iyer <ilina@codeaurora.org>
> ---
> .../bindings/interrupt-controller/qcom,pdc.txt | 55 ++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
> new file mode 100644
> index 000000000000..c4592bbf678d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
> @@ -0,0 +1,55 @@
> +PDC interrupt controller
> +
> +Qualcomm Technologies Inc. SoCs based on the RPM Hardened archicture have a
> +Power Domain Controller (PDC) that is on always-on domain. In addition to
> +providing power control for the power domains, the hardware also has an
> +interrupt controller that can be used to help detect edge low interrupts as
> +well detect interrupts when the GIC is non-operational.
> +
> +GIC is parent interrupt controller at the highest level. Platform interrupt
> +controller PDC is next in hierarchy, followed by others.
> This driver only configures the interrupts, does not handle them.
Not sure if the above statement belongs to the binding.
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH RFC 2/4] dt-bindings/interrupt-controller: pdc: descibe PDC device binding
2018-01-23 18:09 ` Sudeep Holla
@ 2018-01-23 18:46 ` Lina Iyer
0 siblings, 0 replies; 5+ messages in thread
From: Lina Iyer @ 2018-01-23 18:46 UTC (permalink / raw)
To: Sudeep Holla
Cc: tglx, jason, marc.zyngier, linux-kernel, linux-arm-msm, sboyd,
rnayak, asathyak, devicetree
On Tue, Jan 23 2018 at 18:10 +0000, Sudeep Holla wrote:
>
>
>On 23/01/18 17:56, Lina Iyer wrote:
>> From: Archana Sathyakumar <asathyak@codeaurora.org>
>>
>> Add device binding documentation for the PDC Interrupt controller on
>> QCOM SoC's like the SDM845. The interrupt-controller can be used to
>> sense edge low interrupts and wakeup interrupts when the GIC is
>> non-operational.
>>
>> Cc: devicetree@vger.kernel.org
>> Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
>> Signed-off-by: Lina Iyer <ilina@codeaurora.org>
>> ---
>> .../bindings/interrupt-controller/qcom,pdc.txt | 55 ++++++++++++++++++++++
>> 1 file changed, 55 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
>> new file mode 100644
>> index 000000000000..c4592bbf678d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
>> @@ -0,0 +1,55 @@
>> +PDC interrupt controller
>> +
>> +Qualcomm Technologies Inc. SoCs based on the RPM Hardened archicture have a
>> +Power Domain Controller (PDC) that is on always-on domain. In addition to
>> +providing power control for the power domains, the hardware also has an
>> +interrupt controller that can be used to help detect edge low interrupts as
>> +well detect interrupts when the GIC is non-operational.
>> +
>> +GIC is parent interrupt controller at the highest level. Platform interrupt
>> +controller PDC is next in hierarchy, followed by others.
>
>> This driver only configures the interrupts, does not handle them.
>
>Not sure if the above statement belongs to the binding.
>
Will fix.
Thanks,
Lina
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH RFC 2/4] dt-bindings/interrupt-controller: pdc: descibe PDC device binding
2018-01-23 17:56 ` [PATCH RFC 2/4] dt-bindings/interrupt-controller: pdc: descibe PDC device binding Lina Iyer
2018-01-23 18:09 ` Sudeep Holla
@ 2018-01-24 14:24 ` Marc Zyngier
2018-01-30 15:20 ` Rob Herring
2 siblings, 0 replies; 5+ messages in thread
From: Marc Zyngier @ 2018-01-24 14:24 UTC (permalink / raw)
To: Lina Iyer, tglx, jason
Cc: linux-kernel, linux-arm-msm, sboyd, rnayak, asathyak, devicetree
On 23/01/18 17:56, Lina Iyer wrote:
> From: Archana Sathyakumar <asathyak@codeaurora.org>
>
> Add device binding documentation for the PDC Interrupt controller on
> QCOM SoC's like the SDM845. The interrupt-controller can be used to
> sense edge low interrupts and wakeup interrupts when the GIC is
> non-operational.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
> Signed-off-by: Lina Iyer <ilina@codeaurora.org>
> ---
> .../bindings/interrupt-controller/qcom,pdc.txt | 55 ++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
> new file mode 100644
> index 000000000000..c4592bbf678d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
> @@ -0,0 +1,55 @@
> +PDC interrupt controller
> +
> +Qualcomm Technologies Inc. SoCs based on the RPM Hardened archicture have a
nit: architecture
> +Power Domain Controller (PDC) that is on always-on domain. In addition to
> +providing power control for the power domains, the hardware also has an
> +interrupt controller that can be used to help detect edge low interrupts as
> +well detect interrupts when the GIC is non-operational.
> +
> +GIC is parent interrupt controller at the highest level. Platform interrupt
> +controller PDC is next in hierarchy, followed by others. This driver only
> +configures the interrupts, does not handle them.
> +
> +Properties:
> +
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: Should contain "qcom,pdc" and "qcom,pdc-<target>"
> + - "qcom,pdc-sdm845": For sdm845 pin data
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: Specifies the base physical address for PDC hardware.
> +
> +- interrupt-cells:
> + Usage: required
> + Value type: <u32>
> + Definition: Specifies the number of cells needed to encode an interrupt
> + source.
> + Value must be 3.
> + The encoding of these cells are same as described in [1].
The GICv3 binding allows for more cells (at least 4), so you'll have to
adapt both in the binding and in the driver.
> +
> +- interrupt-parent:
> + Usage: required
> + Value type: <phandle>
> + Definition: Specifies the interrupt parent necessary for hierarchical
> + domain to operate.
> +
> +- interrupt-controller:
> + Usage: required
> + Value type: <bool>
> + Definition: Identifies the node as an interrupt controller.
> +
> +Example:
> +
> + pdc: interrupt-controller@b220000 {
> + compatible = "qcom,pdc", "qcom,pdc-sdm845";
> + reg = <0xb220000 0x30000>;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&intc>;
> + interrupt-controller;
> + };
> +
> +[1]. Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
>
You'll also have to specify the ranges for the pin to SPI mapping.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH RFC 2/4] dt-bindings/interrupt-controller: pdc: descibe PDC device binding
2018-01-23 17:56 ` [PATCH RFC 2/4] dt-bindings/interrupt-controller: pdc: descibe PDC device binding Lina Iyer
2018-01-23 18:09 ` Sudeep Holla
2018-01-24 14:24 ` Marc Zyngier
@ 2018-01-30 15:20 ` Rob Herring
2 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2018-01-30 15:20 UTC (permalink / raw)
To: Lina Iyer
Cc: tglx, jason, marc.zyngier, linux-kernel, linux-arm-msm, sboyd,
rnayak, asathyak, devicetree
On Tue, Jan 23, 2018 at 10:56:54AM -0700, Lina Iyer wrote:
> From: Archana Sathyakumar <asathyak@codeaurora.org>
>
> Add device binding documentation for the PDC Interrupt controller on
> QCOM SoC's like the SDM845. The interrupt-controller can be used to
> sense edge low interrupts and wakeup interrupts when the GIC is
> non-operational.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
> Signed-off-by: Lina Iyer <ilina@codeaurora.org>
> ---
> .../bindings/interrupt-controller/qcom,pdc.txt | 55 ++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
> new file mode 100644
> index 000000000000..c4592bbf678d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
> @@ -0,0 +1,55 @@
> +PDC interrupt controller
> +
> +Qualcomm Technologies Inc. SoCs based on the RPM Hardened archicture have a
> +Power Domain Controller (PDC) that is on always-on domain. In addition to
> +providing power control for the power domains, the hardware also has an
> +interrupt controller that can be used to help detect edge low interrupts as
> +well detect interrupts when the GIC is non-operational.
> +
> +GIC is parent interrupt controller at the highest level. Platform interrupt
> +controller PDC is next in hierarchy, followed by others. This driver only
> +configures the interrupts, does not handle them.
> +
> +Properties:
> +
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: Should contain "qcom,pdc" and "qcom,pdc-<target>"
> + - "qcom,pdc-sdm845": For sdm845 pin data
pin data?
Convention is <soc>-<ip block>
Need to make the order of compatibles clear. Generally that is done with
'followed by "qcom,pdc"' after the list of compatibles. But then, do you
really need a fallback. This seems like a block that would change
frequently. If there's not more than 2 or 3 chips with the same block,
don't do a fallback.
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: Specifies the base physical address for PDC hardware.
> +
> +- interrupt-cells:
> + Usage: required
> + Value type: <u32>
> + Definition: Specifies the number of cells needed to encode an interrupt
> + source.
> + Value must be 3.
> + The encoding of these cells are same as described in [1].
> +
> +- interrupt-parent:
> + Usage: required
> + Value type: <phandle>
> + Definition: Specifies the interrupt parent necessary for hierarchical
> + domain to operate.
> +
> +- interrupt-controller:
> + Usage: required
> + Value type: <bool>
> + Definition: Identifies the node as an interrupt controller.
> +
> +Example:
> +
> + pdc: interrupt-controller@b220000 {
> + compatible = "qcom,pdc", "qcom,pdc-sdm845";
This is backwards.
> + reg = <0xb220000 0x30000>;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&intc>;
> + interrupt-controller;
> + };
> +
> +[1]. Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
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^ permalink raw reply [flat|nested] 5+ messages in thread