* [PATCH v4 3/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display
[not found] ` <1516930442-10285-1-git-send-email-hyun.kwon-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2018-01-26 1:33 ` [PATCH v4 2/5] dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings Hyun Kwon
@ 2018-01-26 1:34 ` Hyun Kwon
2018-01-26 1:34 ` [PATCH v4 4/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DisplayPort Hyun Kwon
2018-01-26 1:34 ` [PATCH v4 5/5] drm: xlnx: ZynqMP DP subsystem DRM KMS driver Hyun Kwon
3 siblings, 0 replies; 6+ messages in thread
From: Hyun Kwon @ 2018-01-26 1:34 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Michal Simek, Rob Herring, Daniel Vetter, Laurent Pinchart, Hyun Kwon
Xilinx ZynqMP has a hardened display pipeline. The pipeline can
be logically partitioned into 2 parts: display controller and
DisplayPort encoder / transmitter. This driver handles the display
controller part of the pipeline that handles buffer management and
blending.
Signed-off-by: Hyun Kwon <hyun.kwon-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Acked-by: Daniel Vetter <daniel.vetter-/w4YWyX8dFk@public.gmane.org>
---
v4
- Use drm_crtc_funcs for vblank
- Remove child nodes for layer
v3
- Fix a small typo
v2
- Use drm_fb_cma_get_gem_addr()
- Use drm_crtc_arm_vblank_event()
- Split drm properties into a separate patch
- Remove dummy funcs
- Don't add offset as it's already done by a new helper
- Change the SPDX identifier format
- Minor change of a commit message
---
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 2676 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/xlnx/zynqmp_disp.h | 36 +
2 files changed, 2712 insertions(+)
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c
new file mode 100644
index 0000000..e47d77d
--- /dev/null
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -0,0 +1,2676 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP Display Controller Driver
+ *
+ * Copyright (C) 2017 - 2018 Xilinx, Inc.
+ *
+ * Author: Hyun Woo Kwon <hyun.kwon-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_plane_helper.h>
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/dmaengine.h>
+#include <linux/interrupt.h>
+#include <linux/irqreturn.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+
+#include "xlnx_crtc.h"
+#include "xlnx_fb.h"
+#include "zynqmp_disp.h"
+#include "zynqmp_dp.h"
+#include "zynqmp_dpsub.h"
+
+/*
+ * Overview
+ * --------
+ *
+ * The display part of ZynqMP DP subsystem. Internally, the device
+ * is partitioned into 3 blocks: AV buffer manager, Blender, Audio.
+ * The driver creates the DRM crtc and plane objectes and maps the DRM
+ * interface into those 3 blocks. In high level, the driver is layered
+ * in the following way:
+ *
+ * zynqmp_disp_crtc & zynqmp_disp_plane
+ * |->zynqmp_disp
+ * |->zynqmp_disp_aud
+ * |->zynqmp_disp_blend
+ * |->zynqmp_disp_av_buf
+ *
+ * The driver APIs are used externally by
+ * - zynqmp_dpsub: Top level ZynqMP DP subsystem driver
+ * - zynqmp_dp: ZynqMP DP driver
+ * - xlnx_crtc: Xilinx DRM specific crtc functions
+ */
+
+/* Blender registers */
+#define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x0
+#define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x4
+#define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x8
+#define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff
+#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc
+#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MASK 0x1fe
+#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MAX 0xff
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x0
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444 0x1
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422 0x2
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x3
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC 0x4
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_EN_DOWNSAMPLE BIT(4)
+#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL 0x18
+#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US BIT(0)
+#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB BIT(1)
+#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS BIT(8)
+#define ZYNQMP_DISP_V_BLEND_NUM_COEFF 9
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF0 0x20
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF1 0x24
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF2 0x28
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF3 0x2c
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF4 0x30
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF5 0x34
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF6 0x38
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF7 0x3c
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF8 0x40
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF0 0x44
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF1 0x48
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF2 0x4c
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF3 0x50
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF4 0x54
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF5 0x58
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF6 0x5c
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF7 0x60
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF8 0x64
+#define ZYNQMP_DISP_V_BLEND_NUM_OFFSET 3
+#define ZYNQMP_DISP_V_BLEND_LUMA_IN1CSC_OFFSET 0x68
+#define ZYNQMP_DISP_V_BLEND_CR_IN1CSC_OFFSET 0x6c
+#define ZYNQMP_DISP_V_BLEND_CB_IN1CSC_OFFSET 0x70
+#define ZYNQMP_DISP_V_BLEND_LUMA_OUTCSC_OFFSET 0x74
+#define ZYNQMP_DISP_V_BLEND_CR_OUTCSC_OFFSET 0x78
+#define ZYNQMP_DISP_V_BLEND_CB_OUTCSC_OFFSET 0x7c
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF0 0x80
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF1 0x84
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF2 0x88
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF3 0x8c
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF4 0x90
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF5 0x94
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF6 0x98
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF7 0x9c
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF8 0xa0
+#define ZYNQMP_DISP_V_BLEND_LUMA_IN2CSC_OFFSET 0xa4
+#define ZYNQMP_DISP_V_BLEND_CR_IN2CSC_OFFSET 0xa8
+#define ZYNQMP_DISP_V_BLEND_CB_IN2CSC_OFFSET 0xac
+#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_ENABLE 0x1d0
+#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP1 0x1d4
+#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP2 0x1d8
+#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP3 0x1dc
+
+/* AV buffer manager registers */
+#define ZYNQMP_DISP_AV_BUF_FMT 0x0
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_SHIFT 0
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK (0x1f << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_UYVY (0 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY (1 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YVYU (2 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV (3 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16 (4 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24 (5 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI (6 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MONO (7 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2 (8 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444 (9 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888 (10 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880 (11 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10 (12 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444_10 (13 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_10 (14 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10 (15 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_10 (16 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24_10 (17 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YONLY_10 (18 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420 (19 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420 (20 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420 (21 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420_10 (22 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420_10 (23 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420_10 (24 << 0)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_SHIFT 8
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK (0xf << 8)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888 (0 << 8)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888 (1 << 8)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888 (2 << 8)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888 (3 << 8)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551 (4 << 8)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444 (5 << 8)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565 (6 << 8)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_8BPP (7 << 8)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_4BPP (8 << 8)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_2BPP (9 << 8)
+#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_1BPP (10 << 8)
+#define ZYNQMP_DISP_AV_BUF_NON_LIVE_LATENCY 0x8
+#define ZYNQMP_DISP_AV_BUF_CHBUF 0x10
+#define ZYNQMP_DISP_AV_BUF_CHBUF_EN BIT(0)
+#define ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH BIT(1)
+#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT 2
+#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MASK (0xf << 2)
+#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX 0xf
+#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX 0x3
+#define ZYNQMP_DISP_AV_BUF_STATUS 0x28
+#define ZYNQMP_DISP_AV_BUF_STC_CTRL 0x2c
+#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EN BIT(0)
+#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_SHIFT 1
+#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_VSYNC 0
+#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_VID 1
+#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_AUD 2
+#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_INT_VSYNC 3
+#define ZYNQMP_DISP_AV_BUF_STC_INIT_VALUE0 0x30
+#define ZYNQMP_DISP_AV_BUF_STC_INIT_VALUE1 0x34
+#define ZYNQMP_DISP_AV_BUF_STC_ADJ 0x38
+#define ZYNQMP_DISP_AV_BUF_STC_VID_VSYNC_TS0 0x3c
+#define ZYNQMP_DISP_AV_BUF_STC_VID_VSYNC_TS1 0x40
+#define ZYNQMP_DISP_AV_BUF_STC_EXT_VSYNC_TS0 0x44
+#define ZYNQMP_DISP_AV_BUF_STC_EXT_VSYNC_TS1 0x48
+#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT_TS0 0x4c
+#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT_TS1 0x50
+#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT2_TS0 0x54
+#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT2_TS1 0x58
+#define ZYNQMP_DISP_AV_BUF_STC_SNAPSHOT0 0x60
+#define ZYNQMP_DISP_AV_BUF_STC_SNAPSHOT1 0x64
+#define ZYNQMP_DISP_AV_BUF_OUTPUT 0x70
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_SHIFT 0
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK (0x3 << 0)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE (0 << 0)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM (1 << 0)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_PATTERN (2 << 0)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE (3 << 0)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_SHIFT 2
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK (0x3 << 2)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE (0 << 2)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM (1 << 2)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE (2 << 2)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_NONE (3 << 2)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_SHIFT 4
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK (0x3 << 4)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PL (0 << 4)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM (1 << 4)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PATTERN (2 << 4)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE (3 << 4)
+#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN BIT(6)
+#define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT0 0x74
+#define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT1 0x78
+#define ZYNQMP_DISP_AV_BUF_PATTERN_GEN_SELECT 0x100
+#define ZYNQMP_DISP_AV_BUF_CLK_SRC 0x120
+#define ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS BIT(0)
+#define ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS BIT(1)
+#define ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING BIT(2)
+#define ZYNQMP_DISP_AV_BUF_SRST_REG 0x124
+#define ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST BIT(1)
+#define ZYNQMP_DISP_AV_BUF_AUDIO_CH_CONFIG 0x12c
+#define ZYNQMP_DISP_AV_BUF_GFX_COMP0_SF 0x200
+#define ZYNQMP_DISP_AV_BUF_GFX_COMP1_SF 0x204
+#define ZYNQMP_DISP_AV_BUF_GFX_COMP2_SF 0x208
+#define ZYNQMP_DISP_AV_BUF_VID_COMP0_SF 0x20c
+#define ZYNQMP_DISP_AV_BUF_VID_COMP1_SF 0x210
+#define ZYNQMP_DISP_AV_BUF_VID_COMP2_SF 0x214
+#define ZYNQMP_DISP_AV_BUF_LIVE_VID_COMP0_SF 0x218
+#define ZYNQMP_DISP_AV_BUF_LIVE_VID_COMP1_SF 0x21c
+#define ZYNQMP_DISP_AV_BUF_LIVE_VID_COMP2_SF 0x220
+#define ZYNQMP_DISP_AV_BUF_LIVE_VID_CONFIG 0x224
+#define ZYNQMP_DISP_AV_BUF_LIVE_GFX_COMP0_SF 0x228
+#define ZYNQMP_DISP_AV_BUF_LIVE_GFX_COMP1_SF 0x22c
+#define ZYNQMP_DISP_AV_BUF_LIVE_GFX_COMP2_SF 0x230
+#define ZYNQMP_DISP_AV_BUF_LIVE_GFX_CONFIG 0x234
+#define ZYNQMP_DISP_AV_BUF_4BIT_SF 0x11111
+#define ZYNQMP_DISP_AV_BUF_5BIT_SF 0x10842
+#define ZYNQMP_DISP_AV_BUF_6BIT_SF 0x10410
+#define ZYNQMP_DISP_AV_BUF_8BIT_SF 0x10101
+#define ZYNQMP_DISP_AV_BUF_10BIT_SF 0x10040
+#define ZYNQMP_DISP_AV_BUF_NULL_SF 0
+#define ZYNQMP_DISP_AV_BUF_NUM_SF 3
+#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_6 0x0
+#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 0x1
+#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_10 0x2
+#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_12 0x3
+#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_MASK GENMASK(2, 0)
+#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB 0x0
+#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444 0x1
+#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422 0x2
+#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YONLY 0x3
+#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_MASK GENMASK(5, 4)
+#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_CB_FIRST BIT(8)
+#define ZYNQMP_DISP_AV_BUF_PALETTE_MEMORY 0x400
+
+/* Audio registers */
+#define ZYNQMP_DISP_AUD_MIXER_VOLUME 0x0
+#define ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE 0x20002000
+#define ZYNQMP_DISP_AUD_MIXER_META_DATA 0x4
+#define ZYNQMP_DISP_AUD_CH_STATUS0 0x8
+#define ZYNQMP_DISP_AUD_CH_STATUS1 0xc
+#define ZYNQMP_DISP_AUD_CH_STATUS2 0x10
+#define ZYNQMP_DISP_AUD_CH_STATUS3 0x14
+#define ZYNQMP_DISP_AUD_CH_STATUS4 0x18
+#define ZYNQMP_DISP_AUD_CH_STATUS5 0x1c
+#define ZYNQMP_DISP_AUD_CH_A_DATA0 0x20
+#define ZYNQMP_DISP_AUD_CH_A_DATA1 0x24
+#define ZYNQMP_DISP_AUD_CH_A_DATA2 0x28
+#define ZYNQMP_DISP_AUD_CH_A_DATA3 0x2c
+#define ZYNQMP_DISP_AUD_CH_A_DATA4 0x30
+#define ZYNQMP_DISP_AUD_CH_A_DATA5 0x34
+#define ZYNQMP_DISP_AUD_CH_B_DATA0 0x38
+#define ZYNQMP_DISP_AUD_CH_B_DATA1 0x3c
+#define ZYNQMP_DISP_AUD_CH_B_DATA2 0x40
+#define ZYNQMP_DISP_AUD_CH_B_DATA3 0x44
+#define ZYNQMP_DISP_AUD_CH_B_DATA4 0x48
+#define ZYNQMP_DISP_AUD_CH_B_DATA5 0x4c
+#define ZYNQMP_DISP_AUD_SOFT_RESET 0xc00
+#define ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST BIT(0)
+
+#define ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS 4
+#define ZYNQMP_DISP_AV_BUF_NUM_BUFFERS 6
+
+#define ZYNQMP_DISP_NUM_LAYERS 2
+#define ZYNQMP_DISP_MAX_NUM_SUB_PLANES 3
+/*
+ * 3840x2160 is advertised max resolution, but almost any resolutions under
+ * 300Mhz pixel rate would work. Thus put 4096 as maximum width and height.
+ */
+#define ZYNQMP_DISP_MAX_WIDTH 4096
+#define ZYNQMP_DISP_MAX_HEIGHT 4096
+/* 44 bit addressing. This is acutally DPDMA limitation */
+#define ZYNQMP_DISP_MAX_DMA_BIT 44
+
+/**
+ * enum zynqmp_disp_layer_type - Layer type (can be used for hw ID)
+ * @ZYNQMP_DISP_LAYER_VID: Video layer
+ * @ZYNQMP_DISP_LAYER_GFX: Graphics layer
+ */
+enum zynqmp_disp_layer_type {
+ ZYNQMP_DISP_LAYER_VID,
+ ZYNQMP_DISP_LAYER_GFX
+};
+
+/**
+ * enum zynqmp_disp_layer_mode - Layer mode
+ * @ZYNQMP_DISP_LAYER_NONLIVE: non-live (memory) mode
+ * @ZYNQMP_DISP_LAYER_LIVE: live (stream) mode
+ */
+enum zynqmp_disp_layer_mode {
+ ZYNQMP_DISP_LAYER_NONLIVE,
+ ZYNQMP_DISP_LAYER_LIVE
+};
+
+/**
+ * struct zynqmp_disp_layer_dma - struct for DMA engine
+ * @chan: DMA channel
+ * @is_active: flag if the DMA is active
+ * @xt: Interleaved desc config container
+ * @sgl: Data chunk for dma_interleaved_template
+ */
+struct zynqmp_disp_layer_dma {
+ struct dma_chan *chan;
+ bool is_active;
+ struct dma_interleaved_template xt;
+ struct data_chunk sgl[1];
+};
+
+/**
+ * struct zynqmp_disp_layer - Display subsystem layer
+ * @plane: DRM plane
+ * @of_node: device node
+ * @dma: struct for DMA engine
+ * @num_chan: Number of DMA channel
+ * @id: Layer ID
+ * @offset: Layer offset in the register space
+ * @enabled: flag if enabled
+ * @fmt: Current format descriptor
+ * @drm_fmts: Array of supported DRM formats
+ * @num_fmts: Number of supported DRM formats
+ * @bus_fmts: Array of supported bus formats
+ * @num_bus_fmts: Number of supported bus formats
+ * @w: Width
+ * @h: Height
+ * @mode: the operation mode
+ * @other: other layer
+ * @disp: back pointer to struct zynqmp_disp
+ */
+struct zynqmp_disp_layer {
+ struct drm_plane plane;
+ struct device_node *of_node;
+ struct zynqmp_disp_layer_dma dma[ZYNQMP_DISP_MAX_NUM_SUB_PLANES];
+ unsigned int num_chan;
+ enum zynqmp_disp_layer_type id;
+ u32 offset;
+ u8 enabled;
+ const struct zynqmp_disp_fmt *fmt;
+ u32 *drm_fmts;
+ unsigned int num_fmts;
+ u32 *bus_fmts;
+ unsigned int num_bus_fmts;
+ u32 w;
+ u32 h;
+ enum zynqmp_disp_layer_mode mode;
+ struct zynqmp_disp_layer *other;
+ struct zynqmp_disp *disp;
+};
+
+/**
+ * struct zynqmp_disp_blend - Blender
+ * @base: Base address offset
+ */
+struct zynqmp_disp_blend {
+ void __iomem *base;
+};
+
+/**
+ * struct zynqmp_disp_av_buf - AV buffer manager
+ * @base: Base address offset
+ */
+struct zynqmp_disp_av_buf {
+ void __iomem *base;
+};
+
+/**
+ * struct zynqmp_disp_aud - Audio
+ * @base: Base address offset
+ */
+struct zynqmp_disp_aud {
+ void __iomem *base;
+};
+
+/**
+ * struct zynqmp_disp - Display subsystem
+ * @xlnx_crtc: Xilinx DRM crtc
+ * @dev: device structure
+ * @dpsub: Display subsystem
+ * @drm: DRM core
+ * @enabled: flag if enabled
+ * @blend: Blender block
+ * @av_buf: AV buffer manager block
+ * @aud:Audio block
+ * @layers: layers
+ * @alpha: current global alpha value
+ * @alpha_en: flag if the global alpha is enabled
+ * @color: current output color value
+ * @bg_c0: current value of 1st background color component
+ * @bg_c1: current value of 2nd background color component
+ * @bg_c2: current value of 3rd background color component
+ * @tpg_on: current TPG mode state
+ * @event: pending vblank event request
+ * @_ps_pclk: Pixel clock from PS
+ * @_pl_pclk: Pixel clock from PL
+ * @pclk: Pixel clock
+ * @pclk_en: Flag if the pixel clock is enabled
+ * @_ps_audclk: Audio clock from PS
+ * @_pl_audclk: Audio clock from PL
+ * @audclk: Audio clock
+ * @audclk_en: Flag if the audio clock is enabled
+ * @aclk: APB clock
+ * @aclk_en: Flag if the APB clock is enabled
+ */
+struct zynqmp_disp {
+ struct xlnx_crtc xlnx_crtc;
+ struct device *dev;
+ struct zynqmp_dpsub *dpsub;
+ struct drm_device *drm;
+ bool enabled;
+ struct zynqmp_disp_blend blend;
+ struct zynqmp_disp_av_buf av_buf;
+ struct zynqmp_disp_aud aud;
+ struct zynqmp_disp_layer layers[ZYNQMP_DISP_NUM_LAYERS];
+ u32 alpha;
+ bool alpha_en;
+ unsigned int color;
+ u32 bg_c0;
+ u32 bg_c1;
+ u32 bg_c2;
+ bool tpg_on;
+ struct drm_pending_vblank_event *event;
+ /* Don't operate directly on _ps_ */
+ struct clk *_ps_pclk;
+ struct clk *_pl_pclk;
+ struct clk *pclk;
+ bool pclk_en;
+ struct clk *_ps_audclk;
+ struct clk *_pl_audclk;
+ struct clk *audclk;
+ bool audclk_en;
+ struct clk *aclk;
+ bool aclk_en;
+};
+
+/**
+ * struct zynqmp_disp_fmt - Display subsystem format mapping
+ * @drm_fmt: drm format
+ * @disp_fmt: Display subsystem format
+ * @bus_fmt: Bus formats (live formats)
+ * @rgb: flag for RGB formats
+ * @swap: flag to swap r & b for rgb formats, and u & v for yuv formats
+ * @chroma_sub: flag for chroma subsampled formats
+ * @sf: scaling factors for upto 3 color components
+ */
+struct zynqmp_disp_fmt {
+ u32 drm_fmt;
+ u32 disp_fmt;
+ u32 bus_fmt;
+ bool rgb;
+ bool swap;
+ bool chroma_sub;
+ u32 sf[3];
+};
+
+static void zynqmp_disp_write(void __iomem *base, int offset, u32 val)
+{
+ writel(val, base + offset);
+}
+
+static u32 zynqmp_disp_read(void __iomem *base, int offset)
+{
+ return readl(base + offset);
+}
+
+static void zynqmp_disp_clr(void __iomem *base, int offset, u32 clr)
+{
+ zynqmp_disp_write(base, offset, zynqmp_disp_read(base, offset) & ~clr);
+}
+
+static void zynqmp_disp_set(void __iomem *base, int offset, u32 set)
+{
+ zynqmp_disp_write(base, offset, zynqmp_disp_read(base, offset) | set);
+}
+
+/*
+ * Clock functions
+ */
+
+/**
+ * zynqmp_disp_clk_enable - Enable the clock if needed
+ * @clk: clk device
+ * @flag: flag if the clock is enabled
+ *
+ * Enable the clock only if it's not enabled @flag.
+ *
+ * Return: value from clk_prepare_enable().
+ */
+static int zynqmp_disp_clk_enable(struct clk *clk, bool *flag)
+{
+ int ret = 0;
+
+ if (!*flag) {
+ ret = clk_prepare_enable(clk);
+ if (!ret)
+ *flag = true;
+ }
+
+ return ret;
+}
+
+/**
+ * zynqmp_disp_clk_enable - Enable the clock if needed
+ * @clk: clk device
+ * @flag: flag if the clock is enabled
+ *
+ * Disable the clock only if it's enabled @flag.
+ */
+static void zynqmp_disp_clk_disable(struct clk *clk, bool *flag)
+{
+ if (*flag) {
+ clk_disable_unprepare(clk);
+ *flag = false;
+ }
+}
+
+/**
+ * zynqmp_disp_clk_enable - Enable and disable the clock
+ * @clk: clk device
+ * @flag: flag if the clock is enabled
+ *
+ * This is to ensure the clock is disabled. The initial hardware state is
+ * unknown, and this makes sure that the clock is disabled.
+ *
+ * Return: value from clk_prepare_enable().
+ */
+static int zynqmp_disp_clk_enable_disable(struct clk *clk, bool *flag)
+{
+ int ret = 0;
+
+ if (!*flag) {
+ ret = clk_prepare_enable(clk);
+ clk_disable_unprepare(clk);
+ }
+
+ return ret;
+}
+
+/*
+ * Blender functions
+ */
+
+/**
+ * zynqmp_disp_blend_set_output_fmt - Set the output format of the blend
+ * @blend: blend object
+ * @fmt: output format
+ *
+ * Set the output format to @fmt.
+ */
+static void
+zynqmp_disp_blend_set_output_fmt(struct zynqmp_disp_blend *blend, u32 fmt)
+{
+ u16 reset_coeffs[] = { 0x1000, 0x0, 0x0,
+ 0x0, 0x1000, 0x0,
+ 0x0, 0x0, 0x1000 };
+ u32 reset_offsets[] = { 0x0, 0x0, 0x0 };
+ u16 sdtv_coeffs[] = { 0x4c9, 0x864, 0x1d3,
+ 0x7d4d, 0x7ab3, 0x800,
+ 0x800, 0x794d, 0x7eb3 };
+ u32 full_range_offsets[] = { 0x0, 0x8000000, 0x8000000 };
+ u16 *coeffs;
+ u32 *offsets;
+ u32 offset, i;
+
+ zynqmp_disp_write(blend->base, ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT, fmt);
+ if (fmt == ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB) {
+ coeffs = reset_coeffs;
+ offsets = reset_offsets;
+ } else {
+ /* Hardcode Full-range SDTV values. Can be runtime config */
+ coeffs = sdtv_coeffs;
+ offsets = full_range_offsets;
+ }
+
+ offset = ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF0;
+ for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i++)
+ zynqmp_disp_write(blend->base, offset + i * 4, coeffs[i]);
+
+ offset = ZYNQMP_DISP_V_BLEND_LUMA_OUTCSC_OFFSET;
+ for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++)
+ zynqmp_disp_write(blend->base, offset + i * 4, offsets[i]);
+}
+
+/**
+ * zynqmp_disp_blend_layer_enable - Enable a layer
+ * @blend: blend object
+ * @layer: layer to enable
+ *
+ * Enable a layer @layer.
+ */
+static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp_blend *blend,
+ struct zynqmp_disp_layer *layer)
+{
+ u32 reg, offset, i, s0, s1;
+ u16 sdtv_coeffs[] = { 0x1000, 0x166f, 0x0,
+ 0x1000, 0x7483, 0x7a7f,
+ 0x1000, 0x0, 0x1c5a };
+ u16 swap_coeffs[] = { 0x1000, 0x0, 0x0,
+ 0x0, 0x1000, 0x0,
+ 0x0, 0x0, 0x1000 };
+ u16 *coeffs;
+ u32 offsets[] = { 0x0, 0x1800, 0x1800 };
+
+ reg = layer->fmt->rgb ? ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB : 0;
+ reg |= layer->fmt->chroma_sub ?
+ ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US : 0;
+
+ zynqmp_disp_write(blend->base,
+ ZYNQMP_DISP_V_BLEND_LAYER_CONTROL + layer->offset,
+ reg);
+
+ if (layer->id == ZYNQMP_DISP_LAYER_VID)
+ offset = ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF0;
+ else
+ offset = ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF0;
+
+ if (!layer->fmt->rgb) {
+ coeffs = sdtv_coeffs;
+ s0 = 1;
+ s1 = 2;
+ } else {
+ coeffs = swap_coeffs;
+ s0 = 0;
+ s1 = 2;
+
+ /* No offset for RGB formats */
+ for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++)
+ offsets[i] = 0;
+ }
+
+ if (layer->fmt->swap) {
+ for (i = 0; i < 3; i++) {
+ coeffs[i * 3 + s0] ^= coeffs[i * 3 + s1];
+ coeffs[i * 3 + s1] ^= coeffs[i * 3 + s0];
+ coeffs[i * 3 + s0] ^= coeffs[i * 3 + s1];
+ }
+ }
+
+ /* Program coefficients. Can be runtime configurable */
+ for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i++)
+ zynqmp_disp_write(blend->base, offset + i * 4, coeffs[i]);
+
+ if (layer->id == ZYNQMP_DISP_LAYER_VID)
+ offset = ZYNQMP_DISP_V_BLEND_LUMA_IN1CSC_OFFSET;
+ else
+ offset = ZYNQMP_DISP_V_BLEND_LUMA_IN2CSC_OFFSET;
+
+ /* Program offsets. Can be runtime configurable */
+ for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++)
+ zynqmp_disp_write(blend->base, offset + i * 4, offsets[i]);
+}
+
+/**
+ * zynqmp_disp_blend_layer_disable - Disable a layer
+ * @blend: blend object
+ * @layer: layer to disable
+ *
+ * Disable a layer @layer.
+ */
+static void zynqmp_disp_blend_layer_disable(struct zynqmp_disp_blend *blend,
+ struct zynqmp_disp_layer *layer)
+{
+ u32 offset;
+ unsigned int i;
+
+ zynqmp_disp_write(blend->base,
+ ZYNQMP_DISP_V_BLEND_LAYER_CONTROL + layer->offset, 0);
+
+ if (layer->id == ZYNQMP_DISP_LAYER_VID)
+ offset = ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF0;
+ else
+ offset = ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF0;
+ for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i++)
+ zynqmp_disp_write(blend->base, offset + i * 4, 0);
+
+ if (layer->id == ZYNQMP_DISP_LAYER_VID)
+ offset = ZYNQMP_DISP_V_BLEND_LUMA_IN1CSC_OFFSET;
+ else
+ offset = ZYNQMP_DISP_V_BLEND_LUMA_IN2CSC_OFFSET;
+
+ for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++)
+ zynqmp_disp_write(blend->base, offset + i * 4, 0);
+}
+
+/**
+ * zynqmp_disp_blend_set_bg_color - Set the background color
+ * @blend: blend object
+ * @c0: color component 0
+ * @c1: color component 1
+ * @c2: color component 2
+ *
+ * Set the background color.
+ */
+static void zynqmp_disp_blend_set_bg_color(struct zynqmp_disp_blend *blend,
+ u32 c0, u32 c1, u32 c2)
+{
+ zynqmp_disp_write(blend->base, ZYNQMP_DISP_V_BLEND_BG_CLR_0, c0);
+ zynqmp_disp_write(blend->base, ZYNQMP_DISP_V_BLEND_BG_CLR_1, c1);
+ zynqmp_disp_write(blend->base, ZYNQMP_DISP_V_BLEND_BG_CLR_2, c2);
+}
+
+/**
+ * zynqmp_disp_blend_set_alpha - Set the alpha for blending
+ * @blend: blend object
+ * @alpha: alpha value to be used
+ *
+ * Set the alpha for blending.
+ */
+static void
+zynqmp_disp_blend_set_alpha(struct zynqmp_disp_blend *blend, u32 alpha)
+{
+ u32 reg;
+
+ reg = zynqmp_disp_read(blend->base,
+ ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA);
+ reg &= ~ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MASK;
+ reg |= alpha << 1;
+ zynqmp_disp_write(blend->base, ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA,
+ reg);
+}
+
+/**
+ * zynqmp_disp_blend_enable_alpha - Enable/disable the global alpha
+ * @blend: blend object
+ * @enable: flag to enable or disable alpha blending
+ *
+ * Enable/disable the global alpha blending based on @enable.
+ */
+static void
+zynqmp_disp_blend_enable_alpha(struct zynqmp_disp_blend *blend, bool enable)
+{
+ if (enable)
+ zynqmp_disp_set(blend->base,
+ ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA, BIT(0));
+ else
+ zynqmp_disp_clr(blend->base,
+ ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA, BIT(0));
+}
+
+/* List of blend output formats */
+/* The id / order should be aligned with zynqmp_disp_color_enum */
+static const struct zynqmp_disp_fmt blend_output_fmts[] = {
+ {
+ .disp_fmt = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB,
+ }, {
+ .disp_fmt = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444,
+ }, {
+ .disp_fmt = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422,
+ }, {
+ .disp_fmt = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY,
+ }
+};
+
+/*
+ * AV buffer manager functions
+ */
+
+/* List of video layer formats */
+#define ZYNQMP_DISP_AV_BUF_VID_FMT_YUYV 2
+static const struct zynqmp_disp_fmt av_buf_vid_fmts[] = {
+ {
+ .drm_fmt = DRM_FORMAT_VYUY,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY,
+ .rgb = false,
+ .swap = true,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_UYVY,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY,
+ .rgb = false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_YUYV,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV,
+ .rgb = false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_YVYU,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV,
+ .rgb = false,
+ .swap = true,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_YUV422,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16,
+ .rgb = false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_YVU422,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16,
+ .rgb = false,
+ .swap = true,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_YUV444,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24,
+ .rgb = false,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_YVU444,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24,
+ .rgb = false,
+ .swap = true,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_NV16,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI,
+ .rgb = false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_NV61,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI,
+ .rgb = false,
+ .swap = true,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_BGR888,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888,
+ .rgb = true,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_RGB888,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888,
+ .rgb = true,
+ .swap = true,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_XBGR8888,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880,
+ .rgb = true,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_XRGB8888,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880,
+ .rgb = true,
+ .swap = true,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_XBGR2101010,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10,
+ .rgb = true,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_XRGB2101010,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10,
+ .rgb = true,
+ .swap = true,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_YUV420,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420,
+ .rgb = false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_YVU420,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420,
+ .rgb = false,
+ .swap = true,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_NV12,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420,
+ .rgb = false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_NV21,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420,
+ .rgb = false,
+ .swap = true,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }
+};
+
+/* List of graphics layer formats */
+#define ZYNQMP_DISP_AV_BUF_GFX_FMT_RGB565 10
+static const struct zynqmp_disp_fmt av_buf_gfx_fmts[] = {
+ {
+ .drm_fmt = DRM_FORMAT_ABGR8888,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888,
+ .rgb = true,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_ARGB8888,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888,
+ .rgb = true,
+ .swap = true,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_RGBA8888,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888,
+ .rgb = true,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_BGRA8888,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888,
+ .rgb = true,
+ .swap = true,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_BGR888,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888,
+ .rgb = true,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_RGB888,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888,
+ .rgb = true,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_RGBA5551,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551,
+ .rgb = true,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_5BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_5BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_5BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_BGRA5551,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551,
+ .rgb = true,
+ .swap = true,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_5BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_5BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_5BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_RGBA4444,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444,
+ .rgb = true,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_4BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_4BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_4BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_BGRA4444,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444,
+ .rgb = true,
+ .swap = true,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_4BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_4BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_4BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_RGB565,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565,
+ .rgb = true,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_5BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_6BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_5BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_BGR565,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565,
+ .rgb = true,
+ .swap = true,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_5BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_6BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_5BIT_SF,
+ }
+};
+
+/* List of live formats */
+/* Format can be combination of color, bpc, and cb-cr order.
+ * - Color: RGB / YUV444 / YUV422 / Y only
+ * - BPC: 6, 8, 10, 12
+ * - Swap: Cb and Cr swap
+ * which can be 32 bus formats. Only list the subset of those for now.
+ */
+static const struct zynqmp_disp_fmt av_buf_live_fmts[] = {
+ {
+ .bus_fmt = MEDIA_BUS_FMT_RGB666_1X18,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_6 ||
+ ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB,
+ .rgb = true,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_6BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_6BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_6BIT_SF,
+ }, {
+ .bus_fmt = MEDIA_BUS_FMT_RBG888_1X24,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 ||
+ ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB,
+ .rgb = true,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .bus_fmt = MEDIA_BUS_FMT_UYVY8_1X16,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 ||
+ ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422,
+ .rgb = false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .bus_fmt = MEDIA_BUS_FMT_VUY8_1X24,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 ||
+ ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444,
+ .rgb = false,
+ .swap = false,
+ .chroma_sub = false,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .bus_fmt = MEDIA_BUS_FMT_UYVY10_1X20,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_10 ||
+ ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422,
+ .rgb = false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ }
+};
+
+/**
+ * zynqmp_disp_av_buf_set_fmt - Set the input formats
+ * @av_buf: av buffer manager
+ * @fmt: formats
+ *
+ * Set the av buffer manager format to @fmt. @fmt should have valid values
+ * for both video and graphics layer.
+ */
+static void
+zynqmp_disp_av_buf_set_fmt(struct zynqmp_disp_av_buf *av_buf, u32 fmt)
+{
+ zynqmp_disp_write(av_buf->base, ZYNQMP_DISP_AV_BUF_FMT, fmt);
+}
+
+/**
+ * zynqmp_disp_av_buf_get_fmt - Get the input formats
+ * @av_buf: av buffer manager
+ *
+ * Get the input formats (which include video and graphics) of
+ * av buffer manager.
+ *
+ * Return: value of ZYNQMP_DISP_AV_BUF_FMT register.
+ */
+static u32
+zynqmp_disp_av_buf_get_fmt(struct zynqmp_disp_av_buf *av_buf)
+{
+ return zynqmp_disp_read(av_buf->base, ZYNQMP_DISP_AV_BUF_FMT);
+}
+
+/**
+ * zynqmp_disp_av_buf_set_vid_clock_src - Set the video clock source
+ * @av_buf: av buffer manager
+ * @from_ps: flag if the video clock is from ps
+ *
+ * Set the video clock source based on @from_ps. It can come from either PS or
+ * PL.
+ */
+static void
+zynqmp_disp_av_buf_set_vid_clock_src(struct zynqmp_disp_av_buf *av_buf,
+ bool from_ps)
+{
+ u32 reg = zynqmp_disp_read(av_buf->base, ZYNQMP_DISP_AV_BUF_CLK_SRC);
+
+ if (from_ps)
+ reg |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS;
+ else
+ reg &= ~ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS;
+ zynqmp_disp_write(av_buf->base, ZYNQMP_DISP_AV_BUF_CLK_SRC, reg);
+}
+
+/**
+ * zynqmp_disp_av_buf_set_vid_timing_src - Set the video timing source
+ * @av_buf: av buffer manager
+ * @internal: flag if the video timing is generated internally
+ *
+ * Set the video timing source based on @internal. It can come externally or
+ * be generated internally.
+ */
+static void
+zynqmp_disp_av_buf_set_vid_timing_src(struct zynqmp_disp_av_buf *av_buf,
+ bool internal)
+{
+ u32 reg = zynqmp_disp_read(av_buf->base, ZYNQMP_DISP_AV_BUF_CLK_SRC);
+
+ if (internal)
+ reg |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING;
+ else
+ reg &= ~ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING;
+ zynqmp_disp_write(av_buf->base, ZYNQMP_DISP_AV_BUF_CLK_SRC, reg);
+}
+
+/**
+ * zynqmp_disp_av_buf_set_aud_clock_src - Set the audio clock source
+ * @av_buf: av buffer manager
+ * @from_ps: flag if the video clock is from ps
+ *
+ * Set the audio clock source based on @from_ps. It can come from either PS or
+ * PL.
+ */
+static void
+zynqmp_disp_av_buf_set_aud_clock_src(struct zynqmp_disp_av_buf *av_buf,
+ bool from_ps)
+{
+ u32 reg = zynqmp_disp_read(av_buf->base, ZYNQMP_DISP_AV_BUF_CLK_SRC);
+
+ if (from_ps)
+ reg |= ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS;
+ else
+ reg &= ~ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS;
+ zynqmp_disp_write(av_buf->base, ZYNQMP_DISP_AV_BUF_CLK_SRC, reg);
+}
+
+/**
+ * zynqmp_disp_av_buf_enable_buf - Enable buffers
+ * @av_buf: av buffer manager
+ *
+ * Enable all (video and audio) buffers.
+ */
+static void
+zynqmp_disp_av_buf_enable_buf(struct zynqmp_disp_av_buf *av_buf)
+{
+ u32 reg, i;
+
+ reg = ZYNQMP_DISP_AV_BUF_CHBUF_EN;
+ reg |= ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX <<
+ ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT;
+
+ for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS; i++)
+ zynqmp_disp_write(av_buf->base,
+ ZYNQMP_DISP_AV_BUF_CHBUF + i * 4, reg);
+
+ reg = ZYNQMP_DISP_AV_BUF_CHBUF_EN;
+ reg |= ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX <<
+ ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT;
+
+ for (; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++)
+ zynqmp_disp_write(av_buf->base,
+ ZYNQMP_DISP_AV_BUF_CHBUF + i * 4, reg);
+}
+
+/**
+ * zynqmp_disp_av_buf_disable_buf - Disable buffers
+ * @av_buf: av buffer manager
+ *
+ * Disable all (video and audio) buffers.
+ */
+static void
+zynqmp_disp_av_buf_disable_buf(struct zynqmp_disp_av_buf *av_buf)
+{
+ u32 reg, i;
+
+ reg = ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH & ~ZYNQMP_DISP_AV_BUF_CHBUF_EN;
+ for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++)
+ zynqmp_disp_write(av_buf->base,
+ ZYNQMP_DISP_AV_BUF_CHBUF + i * 4, reg);
+}
+
+/**
+ * zynqmp_disp_av_buf_enable_aud - Enable audio
+ * @av_buf: av buffer manager
+ *
+ * Enable all audio buffers.
+ */
+static void
+zynqmp_disp_av_buf_enable_aud(struct zynqmp_disp_av_buf *av_buf)
+{
+ u32 reg;
+
+ reg = zynqmp_disp_read(av_buf->base, ZYNQMP_DISP_AV_BUF_OUTPUT);
+ reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK;
+ reg |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM;
+ reg |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN;
+ zynqmp_disp_write(av_buf->base, ZYNQMP_DISP_AV_BUF_OUTPUT, reg);
+}
+
+/**
+ * zynqmp_disp_av_buf_enable - Enable the video pipe
+ * @av_buf: av buffer manager
+ *
+ * De-assert the video pipe reset
+ */
+static void
+zynqmp_disp_av_buf_enable(struct zynqmp_disp_av_buf *av_buf)
+{
+ zynqmp_disp_write(av_buf->base, ZYNQMP_DISP_AV_BUF_SRST_REG, 0);
+}
+
+/**
+ * zynqmp_disp_av_buf_disable - Disable the video pipe
+ * @av_buf: av buffer manager
+ *
+ * Assert the video pipe reset
+ */
+static void
+zynqmp_disp_av_buf_disable(struct zynqmp_disp_av_buf *av_buf)
+{
+ zynqmp_disp_write(av_buf->base, ZYNQMP_DISP_AV_BUF_SRST_REG,
+ ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST);
+}
+
+/**
+ * zynqmp_disp_av_buf_disable_aud - Disable audio
+ * @av_buf: av buffer manager
+ *
+ * Disable all audio buffers.
+ */
+static void
+zynqmp_disp_av_buf_disable_aud(struct zynqmp_disp_av_buf *av_buf)
+{
+ u32 reg;
+
+ reg = zynqmp_disp_read(av_buf->base, ZYNQMP_DISP_AV_BUF_OUTPUT);
+ reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK;
+ reg |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE;
+ reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN;
+ zynqmp_disp_write(av_buf->base, ZYNQMP_DISP_AV_BUF_OUTPUT, reg);
+}
+
+/**
+ * zynqmp_disp_av_buf_set_tpg - Set TPG mode
+ * @av_buf: av buffer manager
+ * @tpg_on: if TPG should be on
+ *
+ * Set the TPG mode based on @tpg_on.
+ */
+static void zynqmp_disp_av_buf_set_tpg(struct zynqmp_disp_av_buf *av_buf,
+ bool tpg_on)
+{
+ u32 reg;
+
+ reg = zynqmp_disp_read(av_buf->base, ZYNQMP_DISP_AV_BUF_OUTPUT);
+ reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK;
+ if (tpg_on)
+ reg |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_PATTERN;
+ else
+ reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_PATTERN;
+ zynqmp_disp_write(av_buf->base, ZYNQMP_DISP_AV_BUF_OUTPUT, reg);
+}
+
+/**
+ * zynqmp_disp_av_buf_enable_vid - Enable the video layer buffer
+ * @av_buf: av buffer manager
+ * @layer: layer to enable
+ * @mode: operation mode of layer
+ *
+ * Enable the video/graphics buffer for @layer.
+ */
+static void zynqmp_disp_av_buf_enable_vid(struct zynqmp_disp_av_buf *av_buf,
+ struct zynqmp_disp_layer *layer,
+ enum zynqmp_disp_layer_mode mode)
+{
+ u32 reg;
+
+ reg = zynqmp_disp_read(av_buf->base, ZYNQMP_DISP_AV_BUF_OUTPUT);
+ if (layer->id == ZYNQMP_DISP_LAYER_VID) {
+ reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK;
+ if (mode == ZYNQMP_DISP_LAYER_NONLIVE)
+ reg |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM;
+ else
+ reg |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE;
+ } else {
+ reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK;
+ reg |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM;
+ if (mode == ZYNQMP_DISP_LAYER_NONLIVE)
+ reg |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM;
+ else
+ reg |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE;
+ }
+ zynqmp_disp_write(av_buf->base, ZYNQMP_DISP_AV_BUF_OUTPUT, reg);
+}
+
+/**
+ * zynqmp_disp_av_buf_disable_vid - Disable the video layer buffer
+ * @av_buf: av buffer manager
+ * @layer: layer to disable
+ *
+ * Disable the video/graphics buffer for @layer.
+ */
+static void
+zynqmp_disp_av_buf_disable_vid(struct zynqmp_disp_av_buf *av_buf,
+ struct zynqmp_disp_layer *layer)
+{
+ u32 reg;
+
+ reg = zynqmp_disp_read(av_buf->base, ZYNQMP_DISP_AV_BUF_OUTPUT);
+ if (layer->id == ZYNQMP_DISP_LAYER_VID) {
+ reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK;
+ reg |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE;
+ } else {
+ reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK;
+ reg |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE;
+ }
+ zynqmp_disp_write(av_buf->base, ZYNQMP_DISP_AV_BUF_OUTPUT, reg);
+}
+
+/**
+ * zynqmp_disp_av_buf_init_sf - Initialize scaling factors
+ * @av_buf: av buffer manager
+ * @vid_fmt: video format descriptor
+ * @gfx_fmt: graphics format descriptor
+ *
+ * Initialize scaling factors for both video and graphics layers.
+ * If the format descriptor is NULL, the function skips the programming.
+ */
+static void zynqmp_disp_av_buf_init_sf(struct zynqmp_disp_av_buf *av_buf,
+ const struct zynqmp_disp_fmt *vid_fmt,
+ const struct zynqmp_disp_fmt *gfx_fmt)
+{
+ unsigned int i;
+ u32 offset;
+
+ if (gfx_fmt) {
+ offset = ZYNQMP_DISP_AV_BUF_GFX_COMP0_SF;
+ for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++)
+ zynqmp_disp_write(av_buf->base, offset + i * 4,
+ gfx_fmt->sf[i]);
+ }
+
+ if (vid_fmt) {
+ offset = ZYNQMP_DISP_AV_BUF_VID_COMP0_SF;
+ for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++)
+ zynqmp_disp_write(av_buf->base, offset + i * 4,
+ vid_fmt->sf[i]);
+ }
+}
+
+/*
+ * Audio functions
+ */
+
+/**
+ * zynqmp_disp_aud_init - Initialize the audio
+ * @aud: audio
+ *
+ * Initialize the audio with default mixer volume. The de-assertion will
+ * initialize the audio states.
+ */
+static void zynqmp_disp_aud_init(struct zynqmp_disp_aud *aud)
+{
+ /* Clear the audio soft reset register as it's an non-reset flop */
+ zynqmp_disp_write(aud->base, ZYNQMP_DISP_AUD_SOFT_RESET, 0);
+ zynqmp_disp_write(aud->base, ZYNQMP_DISP_AUD_MIXER_VOLUME,
+ ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE);
+}
+
+/**
+ * zynqmp_disp_aud_deinit - De-initialize the audio
+ * @aud: audio
+ *
+ * Put the audio in reset.
+ */
+static void zynqmp_disp_aud_deinit(struct zynqmp_disp_aud *aud)
+{
+ zynqmp_disp_set(aud->base, ZYNQMP_DISP_AUD_SOFT_RESET,
+ ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST);
+}
+
+/*
+ * ZynqMP Display layer functions
+ */
+
+/**
+ * zynqmp_disp_layer_check_size - Verify width and height for the layer
+ * @disp: Display subsystem
+ * @layer: layer
+ * @width: width
+ * @height: height
+ *
+ * The Display subsystem has the limitation that both layers should have
+ * identical size. This function stores width and height of @layer, and verifies
+ * if the size (width and height) is valid.
+ *
+ * Return: 0 on success, or -EINVAL if width or/and height is invalid.
+ */
+static int zynqmp_disp_layer_check_size(struct zynqmp_disp *disp,
+ struct zynqmp_disp_layer *layer,
+ u32 width, u32 height)
+{
+ struct zynqmp_disp_layer *other = layer->other;
+
+ if (other->enabled && (other->w != width || other->h != height)) {
+ dev_err(disp->dev, "Layer width:height must be %d:%d\n",
+ other->w, other->h);
+ return -EINVAL;
+ }
+
+ layer->w = width;
+ layer->h = height;
+
+ return 0;
+}
+
+/**
+ * zynqmp_disp_map_fmt - Find the Display subsystem format for given drm format
+ * @fmts: format table to look up
+ * @size: size of the table @fmts
+ * @drm_fmt: DRM format to search
+ *
+ * Search a Display subsystem format corresponding to the given DRM format
+ * @drm_fmt, and return the format descriptor which contains the Display
+ * subsystem format value.
+ *
+ * Return: a Display subsystem format descriptor on success, or NULL.
+ */
+static const struct zynqmp_disp_fmt *
+zynqmp_disp_map_fmt(const struct zynqmp_disp_fmt fmts[],
+ unsigned int size, uint32_t drm_fmt)
+{
+ unsigned int i;
+
+ for (i = 0; i < size; i++)
+ if (fmts[i].drm_fmt == drm_fmt)
+ return &fmts[i];
+
+ return NULL;
+}
+
+/**
+ * zynqmp_disp_set_fmt - Set the format of the layer
+ * @disp: Display subsystem
+ * @layer: layer to set the format
+ * @drm_fmt: DRM format to set
+ *
+ * Set the format of the given layer to @drm_fmt.
+ *
+ * Return: 0 on success. -EINVAL if @drm_fmt is not supported by the layer.
+ */
+static int zynqmp_disp_layer_set_fmt(struct zynqmp_disp *disp,
+ struct zynqmp_disp_layer *layer,
+ uint32_t drm_fmt)
+{
+ const struct zynqmp_disp_fmt *fmt;
+ const struct zynqmp_disp_fmt *vid_fmt = NULL, *gfx_fmt = NULL;
+ u32 size, fmts, mask;
+
+ if (layer->id == ZYNQMP_DISP_LAYER_VID) {
+ size = ARRAY_SIZE(av_buf_vid_fmts);
+ mask = ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK;
+ fmt = zynqmp_disp_map_fmt(av_buf_vid_fmts, size, drm_fmt);
+ vid_fmt = fmt;
+ } else {
+ size = ARRAY_SIZE(av_buf_gfx_fmts);
+ mask = ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK;
+ fmt = zynqmp_disp_map_fmt(av_buf_gfx_fmts, size, drm_fmt);
+ gfx_fmt = fmt;
+ }
+
+ if (!fmt)
+ return -EINVAL;
+
+ fmts = zynqmp_disp_av_buf_get_fmt(&disp->av_buf);
+ fmts &= mask;
+ fmts |= fmt->disp_fmt;
+ zynqmp_disp_av_buf_set_fmt(&disp->av_buf, fmts);
+ zynqmp_disp_av_buf_init_sf(&disp->av_buf, vid_fmt, gfx_fmt);
+ layer->fmt = fmt;
+
+ return 0;
+}
+
+/**
+ * zynqmp_disp_set_tpg - Enable or disable TPG
+ * @disp: Display subsystem
+ * @layer: Video layer
+ * @tpg_on: flag if TPG needs to be enabled or disabled
+ *
+ * Enable / disable the TPG mode on the video layer @layer depending on
+ * @tpg_on. The video layer should be disabled prior to enable request.
+ *
+ * Return: 0 on success. -ENODEV if it's not video layer. -EIO if
+ * the video layer is enabled.
+ */
+static int zynqmp_disp_layer_set_tpg(struct zynqmp_disp *disp,
+ struct zynqmp_disp_layer *layer,
+ bool tpg_on)
+{
+ if (layer->id != ZYNQMP_DISP_LAYER_VID) {
+ dev_err(disp->dev,
+ "only the video layer has the tpg mode\n");
+ return -ENODEV;
+ }
+
+ if (layer->enabled) {
+ dev_err(disp->dev,
+ "the video layer should be disabled for tpg mode\n");
+ return -EIO;
+ }
+
+ zynqmp_disp_av_buf_set_tpg(&disp->av_buf, tpg_on);
+ disp->tpg_on = tpg_on;
+
+ return 0;
+}
+
+/**
+ * zynqmp_disp_get_fmt - Get the supported DRM formats of the layer
+ * @disp: Display subsystem
+ * @layer: layer to get the formats
+ * @drm_fmts: pointer to array of DRM format strings
+ * @num_fmts: pointer to number of returned DRM formats
+ *
+ * Get the supported DRM formats of the given layer.
+ */
+static void zynqmp_disp_layer_get_fmts(struct zynqmp_disp *disp,
+ struct zynqmp_disp_layer *layer,
+ u32 **drm_fmts, unsigned int *num_fmts)
+{
+ *drm_fmts = layer->drm_fmts;
+ *num_fmts = layer->num_fmts;
+}
+
+/**
+ * zynqmp_disp_layer_enable - Enable the layer
+ * @disp: Display subsystem
+ * @layer: layer to esable
+ * @mode: operation mode
+ *
+ * Enable the layer @layer.
+ *
+ * Return: 0 on success, otherwise error code.
+ */
+static int zynqmp_disp_layer_enable(struct zynqmp_disp *disp,
+ struct zynqmp_disp_layer *layer,
+ enum zynqmp_disp_layer_mode mode)
+{
+ struct device *dev = disp->dev;
+ struct dma_async_tx_descriptor *desc;
+ enum dma_ctrl_flags flags;
+ unsigned int i;
+
+ if (layer->enabled && layer->mode != mode) {
+ dev_err(dev, "layer is already enabled in different mode\n");
+ return -EBUSY;
+ }
+
+ zynqmp_disp_av_buf_enable_vid(&disp->av_buf, layer, mode);
+ zynqmp_disp_blend_layer_enable(&disp->blend, layer);
+
+ layer->enabled = true;
+ layer->mode = mode;
+
+ if (mode == ZYNQMP_DISP_LAYER_LIVE)
+ return 0;
+
+ for (i = 0; i < ZYNQMP_DISP_MAX_NUM_SUB_PLANES; i++) {
+ struct zynqmp_disp_layer_dma *dma = &layer->dma[i];
+
+ if (dma->chan && dma->is_active) {
+ flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
+ desc = dmaengine_prep_interleaved_dma(dma->chan,
+ &dma->xt, flags);
+ if (!desc) {
+ dev_err(dev, "failed to prep DMA descriptor\n");
+ return -ENOMEM;
+ }
+
+ dmaengine_submit(desc);
+ dma_async_issue_pending(dma->chan);
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * zynqmp_disp_layer_disable - Disable the layer
+ * @disp: Display subsystem
+ * @layer: layer to disable
+ * @mode: operation mode
+ *
+ * Disable the layer @layer.
+ *
+ * Return: 0 on success, or -EBUSY if the layer is in different mode.
+ */
+static int zynqmp_disp_layer_disable(struct zynqmp_disp *disp,
+ struct zynqmp_disp_layer *layer,
+ enum zynqmp_disp_layer_mode mode)
+{
+ struct device *dev = disp->dev;
+ unsigned int i;
+
+ if (layer->mode != mode) {
+ dev_err(dev, "the layer is operating in different mode\n");
+ return -EBUSY;
+ }
+
+ for (i = 0; i < ZYNQMP_DISP_MAX_NUM_SUB_PLANES; i++)
+ if (layer->dma[i].chan && layer->dma[i].is_active)
+ dmaengine_terminate_sync(layer->dma[i].chan);
+
+ zynqmp_disp_av_buf_disable_vid(&disp->av_buf, layer);
+ zynqmp_disp_blend_layer_disable(&disp->blend, layer);
+ layer->enabled = false;
+
+ return 0;
+}
+
+/**
+ * zynqmp_disp_layer_request_dma - Request DMA channels for a layer
+ * @disp: Display subsystem
+ * @layer: layer to request DMA channels
+ * @name: identifier string for layer type
+ *
+ * Request DMA engine channels for corresponding layer.
+ *
+ * Return: 0 on success, or err value from of_dma_request_slave_channel().
+ */
+static int
+zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp,
+ struct zynqmp_disp_layer *layer, const char *name)
+{
+ struct zynqmp_disp_layer_dma *dma;
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < layer->num_chan; i++) {
+ char temp[16];
+
+ dma = &layer->dma[i];
+ snprintf(temp, sizeof(temp), "%s%d", name, i);
+ dma->chan = of_dma_request_slave_channel(layer->of_node,
+ temp);
+ if (IS_ERR(dma->chan)) {
+ dev_err(disp->dev, "failed to request dma channel\n");
+ ret = PTR_ERR(dma->chan);
+ dma->chan = NULL;
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * zynqmp_disp_layer_release_dma - Release DMA channels for a layer
+ * @disp: Display subsystem
+ * @layer: layer to release DMA channels
+ *
+ * Release the dma channels associated with @layer.
+ */
+static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp,
+ struct zynqmp_disp_layer *layer)
+{
+ unsigned int i;
+
+ for (i = 0; i < layer->num_chan; i++) {
+ if (layer->dma[i].chan) {
+ /* Make sure the channel is terminated before release */
+ dmaengine_terminate_all(layer->dma[i].chan);
+ dma_release_channel(layer->dma[i].chan);
+ }
+ }
+}
+
+/**
+ * zynqmp_disp_layer_is_live - if any layer is live
+ * @disp: Display subsystem
+ *
+ * Return: true if any layer is live
+ */
+static bool zynqmp_disp_layer_is_live(struct zynqmp_disp *disp)
+{
+ unsigned int i;
+
+ for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) {
+ if (disp->layers[i].enabled &&
+ disp->layers[i].mode == ZYNQMP_DISP_LAYER_LIVE)
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * zynqmp_disp_layer_is_enabled - if any layer is enabled
+ * @disp: Display subsystem
+ *
+ * Return: true if any layer is enabled
+ */
+static bool zynqmp_disp_layer_is_enabled(struct zynqmp_disp *disp)
+{
+ unsigned int i;
+
+ for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++)
+ if (disp->layers[i].enabled)
+ return true;
+
+ return false;
+}
+
+/**
+ * zynqmp_disp_layer_destroy - Destroy all layers
+ * @disp: Display subsystem
+ *
+ * Destroy all layers.
+ */
+static void zynqmp_disp_layer_destroy(struct zynqmp_disp *disp)
+{
+ unsigned int i;
+
+ for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) {
+ zynqmp_disp_layer_release_dma(disp, &disp->layers[i]);
+ if (disp->layers[i].of_node)
+ of_node_put(disp->layers[i].of_node);
+ }
+}
+
+/**
+ * zynqmp_disp_layer_create - Create all layers
+ * @disp: Display subsystem
+ *
+ * Create all layers.
+ *
+ * Return: 0 on success, otherwise error code from failed function
+ */
+static int zynqmp_disp_layer_create(struct zynqmp_disp *disp)
+{
+ struct zynqmp_disp_layer *layer;
+ unsigned int i;
+ int num_chans[ZYNQMP_DISP_NUM_LAYERS] = { 3, 1 };
+ const char * const dma_name[] = { "vid", "gfx" };
+ int ret;
+
+ for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) {
+ layer = &disp->layers[i];
+ layer->id = i;
+ layer->offset = i * 4;
+ layer->other = &disp->layers[!i];
+ layer->num_chan = num_chans[i];
+ layer->of_node = disp->dev->of_node;
+ ret = zynqmp_disp_layer_request_dma(disp, layer, dma_name[i]);
+ if (ret)
+ goto err;
+ layer->disp = disp;
+ }
+
+ return 0;
+
+err:
+ zynqmp_disp_layer_destroy(disp);
+ return ret;
+}
+
+/*
+ * ZynqMP Display internal functions
+ */
+
+/*
+ * Output format enumeration.
+ * The ID should be aligned with blend_output_fmts.
+ * The string should be aligned with how zynqmp_dp_set_color() decodes.
+ */
+static struct drm_prop_enum_list zynqmp_disp_color_enum[] = {
+ { 0, "rgb" },
+ { 1, "ycrcb444" },
+ { 2, "ycrcb422" },
+ { 3, "yonly" },
+};
+
+/**
+ * zynqmp_disp_set_output_fmt - Set the output format
+ * @disp: Display subsystem
+ * @id: the format ID. Refer to zynqmp_disp_color_enum[].
+ *
+ * This function sets the output format of the display / blender as well as
+ * the format of DP controller. The @id should be aligned with
+ * zynqmp_disp_color_enum.
+ */
+static void
+zynqmp_disp_set_output_fmt(struct zynqmp_disp *disp, unsigned int id)
+{
+ const struct zynqmp_disp_fmt *fmt = &blend_output_fmts[id];
+
+ zynqmp_dp_set_color(disp->dpsub->dp, zynqmp_disp_color_enum[id].name);
+ zynqmp_disp_blend_set_output_fmt(&disp->blend, fmt->disp_fmt);
+}
+
+/**
+ * zynqmp_disp_set_bg_color - Set the background color
+ * @disp: Display subsystem
+ * @c0: color component 0
+ * @c1: color component 1
+ * @c2: color component 2
+ *
+ * Set the background color with given color components (@c0, @c1, @c2).
+ */
+static void zynqmp_disp_set_bg_color(struct zynqmp_disp *disp,
+ u32 c0, u32 c1, u32 c2)
+{
+ zynqmp_disp_blend_set_bg_color(&disp->blend, c0, c1, c2);
+}
+
+/**
+ * zynqmp_disp_set_alpha - Set the alpha value
+ * @disp: Display subsystem
+ * @alpha: alpha value to set
+ *
+ * Set the alpha value for blending.
+ */
+static void zynqmp_disp_set_alpha(struct zynqmp_disp *disp, u32 alpha)
+{
+ disp->alpha = alpha;
+ zynqmp_disp_blend_set_alpha(&disp->blend, alpha);
+}
+
+/**
+ * zynqmp_disp_set_g_alpha - Enable/disable the global alpha blending
+ * @disp: Display subsystem
+ * @enable: flag to enable or disable alpha blending
+ *
+ * Set the alpha value for blending.
+ */
+static void zynqmp_disp_set_g_alpha(struct zynqmp_disp *disp, bool enable)
+{
+ disp->alpha_en = enable;
+ zynqmp_disp_blend_enable_alpha(&disp->blend, enable);
+}
+
+/**
+ * zynqmp_disp_enable - Enable the Display subsystem
+ * @disp: Display subsystem
+ *
+ * Enable the Display subsystem.
+ */
+static void zynqmp_disp_enable(struct zynqmp_disp *disp)
+{
+ bool live;
+
+ if (disp->enabled)
+ return;
+
+ zynqmp_disp_av_buf_enable(&disp->av_buf);
+ /* Choose clock source based on the DT clock handle */
+ zynqmp_disp_av_buf_set_vid_clock_src(&disp->av_buf, !!disp->_ps_pclk);
+ zynqmp_disp_av_buf_set_aud_clock_src(&disp->av_buf, !!disp->_ps_audclk);
+ live = zynqmp_disp_layer_is_live(disp);
+ zynqmp_disp_av_buf_set_vid_timing_src(&disp->av_buf, !live);
+ zynqmp_disp_av_buf_enable_buf(&disp->av_buf);
+ zynqmp_disp_av_buf_enable_aud(&disp->av_buf);
+ zynqmp_disp_aud_init(&disp->aud);
+ disp->enabled = true;
+}
+
+/**
+ * zynqmp_disp_disable - Disable the Display subsystem
+ * @disp: Display subsystem
+ * @force: flag to disable forcefully
+ *
+ * Disable the Display subsystem.
+ */
+static void zynqmp_disp_disable(struct zynqmp_disp *disp, bool force)
+{
+ struct drm_crtc *crtc = &disp->xlnx_crtc.crtc;
+
+ if (!force && (!disp->enabled || zynqmp_disp_layer_is_enabled(disp)))
+ return;
+
+ zynqmp_disp_aud_deinit(&disp->aud);
+ zynqmp_disp_av_buf_disable_aud(&disp->av_buf);
+ zynqmp_disp_av_buf_disable_buf(&disp->av_buf);
+ zynqmp_disp_av_buf_disable(&disp->av_buf);
+
+ /* Mark the flip is done as crtc is disabled anyway */
+ if (crtc->state->event) {
+ complete_all(crtc->state->event->base.completion);
+ crtc->state->event = NULL;
+ }
+
+ disp->enabled = false;
+}
+
+/*
+ * ZynqMP Display external functions for zynqmp_dp
+ */
+
+/**
+ * zynqmp_disp_handle_vblank - Handle the vblank event
+ * @disp: Display subsystem
+ *
+ * This function handles the vblank interrupt, and sends an event to
+ * CRTC object. This will be called by the DP vblank interrupt handler.
+ */
+void zynqmp_disp_handle_vblank(struct zynqmp_disp *disp)
+{
+ struct drm_crtc *crtc = &disp->xlnx_crtc.crtc;
+
+ drm_crtc_handle_vblank(crtc);
+}
+
+/**
+ * zynqmp_disp_get_apb_clk_rate - Get the current APB clock rate
+ * @disp: Display subsystem
+ *
+ * Return: the current APB clock rate.
+ */
+unsigned int zynqmp_disp_get_apb_clk_rate(struct zynqmp_disp *disp)
+{
+ return clk_get_rate(disp->aclk);
+}
+
+/**
+ * zynqmp_disp_aud_enabled - If the audio is enabled
+ * @disp: Display subsystem
+ *
+ * Return if the audio is enabled depending on the audio clock.
+ *
+ * Return: true if audio is enabled, or false.
+ */
+bool zynqmp_disp_aud_enabled(struct zynqmp_disp *disp)
+{
+ return !!disp->audclk;
+}
+
+/**
+ * zynqmp_disp_get_aud_clk_rate - Get the current audio clock rate
+ * @disp: Display subsystem
+ *
+ * Return: the current audio clock rate.
+ */
+unsigned int zynqmp_disp_get_aud_clk_rate(struct zynqmp_disp *disp)
+{
+ if (zynqmp_disp_aud_enabled(disp))
+ return 0;
+ return clk_get_rate(disp->aclk);
+}
+
+/**
+ * zynqmp_disp_get_crtc_mask - Return the CRTC bit mask
+ * @disp: Display subsystem
+ *
+ * Return: the crtc mask of the zyqnmp_disp CRTC.
+ */
+uint32_t zynqmp_disp_get_crtc_mask(struct zynqmp_disp *disp)
+{
+ return drm_crtc_mask(&disp->xlnx_crtc.crtc);
+}
+
+/*
+ * DRM plane functions
+ */
+
+static inline struct zynqmp_disp_layer *plane_to_layer(struct drm_plane *plane)
+{
+ return container_of(plane, struct zynqmp_disp_layer, plane);
+}
+
+static int zynqmp_disp_plane_enable(struct drm_plane *plane)
+{
+ struct zynqmp_disp_layer *layer = plane_to_layer(plane);
+ struct zynqmp_disp *disp = layer->disp;
+ int ret;
+
+ zynqmp_disp_set_g_alpha(disp, disp->alpha_en);
+ zynqmp_disp_set_alpha(disp, disp->alpha);
+ ret = zynqmp_disp_layer_enable(layer->disp, layer,
+ ZYNQMP_DISP_LAYER_NONLIVE);
+ if (ret)
+ return ret;
+
+ if (layer->id == ZYNQMP_DISP_LAYER_GFX && disp->tpg_on) {
+ layer = &disp->layers[ZYNQMP_DISP_LAYER_VID];
+ zynqmp_disp_layer_set_tpg(disp, layer, disp->tpg_on);
+ }
+
+ return 0;
+}
+
+static int zynqmp_disp_plane_disable(struct drm_plane *plane)
+{
+ struct zynqmp_disp_layer *layer = plane_to_layer(plane);
+ struct zynqmp_disp *disp = layer->disp;
+
+ zynqmp_disp_layer_disable(disp, layer, ZYNQMP_DISP_LAYER_NONLIVE);
+ if (layer->id == ZYNQMP_DISP_LAYER_VID && disp->tpg_on)
+ zynqmp_disp_layer_set_tpg(disp, layer, disp->tpg_on);
+
+ return 0;
+}
+
+static int zynqmp_disp_plane_mode_set(struct drm_plane *plane,
+ struct drm_framebuffer *fb,
+ int crtc_x, int crtc_y,
+ unsigned int crtc_w, unsigned int crtc_h,
+ u32 src_x, u32 src_y,
+ u32 src_w, u32 src_h)
+{
+ struct zynqmp_disp_layer *layer = plane_to_layer(plane);
+ const struct drm_format_info *info = fb->format;
+ struct drm_format_name_buf format_name;
+ struct device *dev = layer->disp->dev;
+ dma_addr_t paddr;
+ unsigned int i;
+ int ret;
+
+ if (!info) {
+ dev_err(dev, "unsupported framebuffer format %s\n",
+ drm_get_format_name(info->format, &format_name));
+ return -EINVAL;
+ }
+
+ ret = zynqmp_disp_layer_check_size(layer->disp, layer, src_w, src_h);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < info->num_planes; i++) {
+ unsigned int width = src_w / (i ? info->hsub : 1);
+ unsigned int height = src_h / (i ? info->vsub : 1);
+
+ paddr = drm_fb_cma_get_gem_addr(fb, plane->state, i);
+ if (!paddr) {
+ dev_err(dev, "failed to get a paddr\n");
+ return -EINVAL;
+ }
+
+ layer->dma[i].xt.numf = height;
+ layer->dma[i].sgl[0].size = width * info->cpp[i];
+ layer->dma[i].sgl[0].icg = fb->pitches[i] -
+ layer->dma[i].sgl[0].size;
+ layer->dma[i].xt.src_start = paddr;
+ layer->dma[i].xt.frame_size = 1;
+ layer->dma[i].xt.dir = DMA_MEM_TO_DEV;
+ layer->dma[i].xt.src_sgl = true;
+ layer->dma[i].xt.dst_sgl = false;
+ layer->dma[i].is_active = true;
+ }
+
+ for (; i < ZYNQMP_DISP_MAX_NUM_SUB_PLANES; i++)
+ layer->dma[i].is_active = false;
+
+ ret = zynqmp_disp_layer_set_fmt(layer->disp, layer, info->format);
+ if (ret)
+ dev_err(dev, "failed to set dp_sub layer fmt\n");
+
+ return ret;
+}
+
+static void zynqmp_disp_plane_destroy(struct drm_plane *plane)
+{
+ drm_plane_cleanup(plane);
+}
+
+static struct drm_plane_funcs zynqmp_disp_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .destroy = zynqmp_disp_plane_destroy,
+ .reset = drm_atomic_helper_plane_reset,
+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+static void
+zynqmp_disp_plane_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+ int ret;
+
+ if (!plane->state->crtc || !plane->state->fb)
+ return;
+
+ ret = zynqmp_disp_plane_mode_set(plane, plane->state->fb,
+ plane->state->crtc_x,
+ plane->state->crtc_y,
+ plane->state->crtc_w,
+ plane->state->crtc_h,
+ plane->state->src_x >> 16,
+ plane->state->src_y >> 16,
+ plane->state->src_w >> 16,
+ plane->state->src_h >> 16);
+ if (ret)
+ return;
+
+ zynqmp_disp_plane_enable(plane);
+}
+
+static void
+zynqmp_disp_plane_atomic_disable(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+ zynqmp_disp_plane_disable(plane);
+}
+
+static const struct drm_plane_helper_funcs zynqmp_disp_plane_helper_funcs = {
+ .atomic_update = zynqmp_disp_plane_atomic_update,
+ .atomic_disable = zynqmp_disp_plane_atomic_disable,
+};
+
+static int zynqmp_disp_create_plane(struct zynqmp_disp *disp)
+{
+ struct zynqmp_disp_layer *layer;
+ unsigned int i;
+ u32 *fmts = NULL;
+ unsigned int num_fmts = 0;
+ enum drm_plane_type type;
+ int ret;
+
+ /* graphics layer is primary, and video layer is overaly */
+ type = DRM_PLANE_TYPE_OVERLAY;
+ for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) {
+ layer = &disp->layers[i];
+ zynqmp_disp_layer_get_fmts(disp, layer, &fmts, &num_fmts);
+ ret = drm_universal_plane_init(disp->drm, &layer->plane, 0,
+ &zynqmp_disp_plane_funcs, fmts,
+ num_fmts, NULL, type, NULL);
+ if (ret)
+ goto err_plane;
+ drm_plane_helper_add(&layer->plane,
+ &zynqmp_disp_plane_helper_funcs);
+ type = DRM_PLANE_TYPE_PRIMARY;
+ }
+
+ return ret;
+
+err_plane:
+ if (i)
+ drm_plane_cleanup(&disp->layers[0].plane);
+ return ret;
+}
+
+static void zynqmp_disp_destroy_plane(struct zynqmp_disp *disp)
+{
+ unsigned int i;
+
+ for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++)
+ zynqmp_disp_plane_destroy(&disp->layers[i].plane);
+}
+
+/*
+ * Xlnx crtc functions
+ */
+
+static inline struct zynqmp_disp *xlnx_crtc_to_disp(struct xlnx_crtc *xlnx_crtc)
+{
+ return container_of(xlnx_crtc, struct zynqmp_disp, xlnx_crtc);
+}
+
+static int zynqmp_disp_get_max_width(struct xlnx_crtc *xlnx_crtc)
+{
+ return ZYNQMP_DISP_MAX_WIDTH;
+}
+
+static int zynqmp_disp_get_max_height(struct xlnx_crtc *xlnx_crtc)
+{
+ return ZYNQMP_DISP_MAX_HEIGHT;
+}
+
+static uint32_t zynqmp_disp_get_format(struct xlnx_crtc *xlnx_crtc)
+{
+ struct zynqmp_disp *disp = xlnx_crtc_to_disp(xlnx_crtc);
+
+ return disp->layers[ZYNQMP_DISP_LAYER_GFX].fmt->drm_fmt;
+}
+
+static unsigned int zynqmp_disp_get_align(struct xlnx_crtc *xlnx_crtc)
+{
+ struct zynqmp_disp *disp = xlnx_crtc_to_disp(xlnx_crtc);
+ struct zynqmp_disp_layer *layer = &disp->layers[ZYNQMP_DISP_LAYER_VID];
+
+ return 1 << layer->dma->chan->device->copy_align;
+}
+
+static u64 zynqmp_disp_get_dma_mask(struct xlnx_crtc *xlnx_crtc)
+{
+ return DMA_BIT_MASK(ZYNQMP_DISP_MAX_DMA_BIT);
+}
+
+/*
+ * DRM crtc functions
+ */
+
+static inline struct zynqmp_disp *crtc_to_disp(struct drm_crtc *crtc)
+{
+ struct xlnx_crtc *xlnx_crtc = to_xlnx_crtc(crtc);
+
+ return xlnx_crtc_to_disp(xlnx_crtc);
+}
+
+static int zynqmp_disp_crtc_mode_set(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+ int x, int y,
+ struct drm_framebuffer *old_fb)
+{
+ struct zynqmp_disp *disp = crtc_to_disp(crtc);
+ unsigned long rate;
+ long diff;
+ int ret;
+
+ zynqmp_disp_clk_disable(disp->pclk, &disp->pclk_en);
+ ret = clk_set_rate(disp->pclk, adjusted_mode->clock * 1000);
+ if (ret) {
+ dev_err(disp->dev, "failed to set a pixel clock\n");
+ return ret;
+ }
+
+ rate = clk_get_rate(disp->pclk);
+ diff = rate - adjusted_mode->clock * 1000;
+ if (abs(diff) > (adjusted_mode->clock * 1000) / 20) {
+ dev_info(disp->dev, "request pixel rate: %d actual rate: %lu\n",
+ adjusted_mode->clock, rate);
+ } else {
+ dev_dbg(disp->dev, "request pixel rate: %d actual rate: %lu\n",
+ adjusted_mode->clock, rate);
+ }
+
+ /* The timing register should be programmed always */
+ zynqmp_dp_encoder_mode_set_stream(disp->dpsub->dp, adjusted_mode);
+
+ return 0;
+}
+
+static void
+zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ struct zynqmp_disp *disp = crtc_to_disp(crtc);
+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
+ int ret, vrefresh;
+
+ zynqmp_disp_crtc_mode_set(crtc, &crtc->state->mode,
+ adjusted_mode, crtc->x, crtc->y, NULL);
+
+ pm_runtime_get_sync(disp->dev);
+ ret = zynqmp_disp_clk_enable(disp->pclk, &disp->pclk_en);
+ if (ret) {
+ dev_err(disp->dev, "failed to enable a pixel clock\n");
+ return;
+ }
+ zynqmp_disp_set_output_fmt(disp, disp->color);
+ zynqmp_disp_set_bg_color(disp, disp->bg_c0, disp->bg_c1, disp->bg_c2);
+ zynqmp_disp_enable(disp);
+ /* Delay of 3 vblank intervals for timing gen to be stable */
+ vrefresh = (adjusted_mode->clock * 1000) /
+ (adjusted_mode->vtotal * adjusted_mode->htotal);
+ msleep(3 * 1000 / vrefresh);
+}
+
+static void
+zynqmp_disp_crtc_atomic_disable(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ struct zynqmp_disp *disp = crtc_to_disp(crtc);
+
+ zynqmp_disp_clk_disable(disp->pclk, &disp->pclk_en);
+ zynqmp_disp_plane_disable(crtc->primary);
+ zynqmp_disp_disable(disp, true);
+ pm_runtime_put_sync(disp->dev);
+}
+
+static int zynqmp_disp_crtc_atomic_check(struct drm_crtc *crtc,
+ struct drm_crtc_state *state)
+{
+ return drm_atomic_add_affected_planes(state->state, crtc);
+}
+
+static void
+zynqmp_disp_crtc_atomic_begin(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ /* Don't rely on vblank when disabling crtc */
+ spin_lock_irq(&crtc->dev->event_lock);
+ if (crtc->primary->state->fb && crtc->state->event) {
+ /* Consume the flip_done event from atomic helper */
+ crtc->state->event->pipe = drm_crtc_index(crtc);
+ WARN_ON(drm_crtc_vblank_get(crtc) != 0);
+ drm_crtc_arm_vblank_event(crtc, crtc->state->event);
+ crtc->state->event = NULL;
+ }
+ spin_unlock_irq(&crtc->dev->event_lock);
+}
+
+static struct drm_crtc_helper_funcs zynqmp_disp_crtc_helper_funcs = {
+ .atomic_enable = zynqmp_disp_crtc_atomic_enable,
+ .atomic_disable = zynqmp_disp_crtc_atomic_disable,
+ .atomic_check = zynqmp_disp_crtc_atomic_check,
+ .atomic_begin = zynqmp_disp_crtc_atomic_begin,
+};
+
+static void zynqmp_disp_crtc_destroy(struct drm_crtc *crtc)
+{
+ zynqmp_disp_crtc_atomic_disable(crtc, NULL);
+ drm_crtc_cleanup(crtc);
+}
+
+static int zynqmp_disp_crtc_enable_vblank(struct drm_crtc *crtc)
+{
+ struct zynqmp_disp *disp = crtc_to_disp(crtc);
+
+ zynqmp_dp_enable_vblank(disp->dpsub->dp);
+
+ return 0;
+}
+
+static void zynqmp_disp_crtc_disable_vblank(struct drm_crtc *crtc)
+{
+ struct zynqmp_disp *disp = crtc_to_disp(crtc);
+
+ zynqmp_dp_disable_vblank(disp->dpsub->dp);
+}
+
+static struct drm_crtc_funcs zynqmp_disp_crtc_funcs = {
+ .destroy = zynqmp_disp_crtc_destroy,
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .reset = drm_atomic_helper_crtc_reset,
+ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+ .enable_vblank = zynqmp_disp_crtc_enable_vblank,
+ .disable_vblank = zynqmp_disp_crtc_disable_vblank,
+};
+
+static void zynqmp_disp_create_crtc(struct zynqmp_disp *disp)
+{
+ struct drm_plane *plane = &disp->layers[ZYNQMP_DISP_LAYER_GFX].plane;
+ int ret;
+
+ ret = drm_crtc_init_with_planes(disp->drm, &disp->xlnx_crtc.crtc, plane,
+ NULL, &zynqmp_disp_crtc_funcs, NULL);
+ drm_crtc_helper_add(&disp->xlnx_crtc.crtc,
+ &zynqmp_disp_crtc_helper_funcs);
+
+ disp->xlnx_crtc.get_max_width = &zynqmp_disp_get_max_width;
+ disp->xlnx_crtc.get_max_height = &zynqmp_disp_get_max_height;
+ disp->xlnx_crtc.get_format = &zynqmp_disp_get_format;
+ disp->xlnx_crtc.get_align = &zynqmp_disp_get_align;
+ disp->xlnx_crtc.get_dma_mask = &zynqmp_disp_get_dma_mask;
+ xlnx_crtc_register(disp->drm, &disp->xlnx_crtc);
+}
+
+static void zynqmp_disp_destroy_crtc(struct zynqmp_disp *disp)
+{
+ xlnx_crtc_unregister(disp->drm, &disp->xlnx_crtc);
+ zynqmp_disp_crtc_destroy(&disp->xlnx_crtc.crtc);
+}
+
+static void zynqmp_disp_map_crtc_to_plane(struct zynqmp_disp *disp)
+{
+ u32 possible_crtcs = drm_crtc_mask(&disp->xlnx_crtc.crtc);
+ unsigned int i;
+
+ for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++)
+ disp->layers[i].plane.possible_crtcs = possible_crtcs;
+}
+
+/*
+ * Component functions
+ */
+
+int zynqmp_disp_bind(struct device *dev, struct device *master, void *data)
+{
+ struct zynqmp_dpsub *dpsub = dev_get_drvdata(dev);
+ struct zynqmp_disp *disp = dpsub->disp;
+ struct drm_device *drm = data;
+ int ret;
+
+ disp->drm = drm;
+
+ ret = zynqmp_disp_create_plane(disp);
+ if (ret)
+ return ret;
+ zynqmp_disp_create_crtc(disp);
+ zynqmp_disp_map_crtc_to_plane(disp);
+
+ return 0;
+}
+
+void zynqmp_disp_unbind(struct device *dev, struct device *master, void *data)
+{
+ struct zynqmp_dpsub *dpsub = dev_get_drvdata(dev);
+ struct zynqmp_disp *disp = dpsub->disp;
+
+ zynqmp_disp_destroy_crtc(disp);
+ zynqmp_disp_destroy_plane(disp);
+}
+
+/*
+ * Platform initialization functions
+ */
+
+static int zynqmp_disp_enumerate_fmts(struct zynqmp_disp *disp)
+{
+ struct zynqmp_disp_layer *layer;
+ u32 *bus_fmts;
+ u32 i, size, num_bus_fmts;
+
+ num_bus_fmts = ARRAY_SIZE(av_buf_live_fmts);
+ bus_fmts = devm_kzalloc(disp->dev, sizeof(*bus_fmts) * num_bus_fmts,
+ GFP_KERNEL);
+ if (!bus_fmts)
+ return -ENOMEM;
+ for (i = 0; i < num_bus_fmts; i++)
+ bus_fmts[i] = av_buf_live_fmts[i].bus_fmt;
+
+ layer = &disp->layers[ZYNQMP_DISP_LAYER_VID];
+ layer->num_bus_fmts = num_bus_fmts;
+ layer->bus_fmts = bus_fmts;
+ size = ARRAY_SIZE(av_buf_vid_fmts);
+ layer->num_fmts = size;
+ layer->drm_fmts = devm_kzalloc(disp->dev,
+ sizeof(*layer->drm_fmts) * size,
+ GFP_KERNEL);
+ if (!layer->drm_fmts)
+ return -ENOMEM;
+ for (i = 0; i < layer->num_fmts; i++)
+ layer->drm_fmts[i] = av_buf_vid_fmts[i].drm_fmt;
+ layer->fmt = &av_buf_vid_fmts[ZYNQMP_DISP_AV_BUF_VID_FMT_YUYV];
+
+ layer = &disp->layers[ZYNQMP_DISP_LAYER_GFX];
+ layer->num_bus_fmts = num_bus_fmts;
+ layer->bus_fmts = bus_fmts;
+ size = ARRAY_SIZE(av_buf_gfx_fmts);
+ layer->num_fmts = size;
+ layer->drm_fmts = devm_kzalloc(disp->dev,
+ sizeof(*layer->drm_fmts) * size,
+ GFP_KERNEL);
+ if (!layer->drm_fmts)
+ return -ENOMEM;
+
+ for (i = 0; i < layer->num_fmts; i++)
+ layer->drm_fmts[i] = av_buf_gfx_fmts[i].drm_fmt;
+ layer->fmt = &av_buf_gfx_fmts[ZYNQMP_DISP_AV_BUF_GFX_FMT_RGB565];
+
+ return 0;
+}
+
+int zynqmp_disp_probe(struct platform_device *pdev)
+{
+ struct zynqmp_dpsub *dpsub;
+ struct zynqmp_disp *disp;
+ struct resource *res;
+ int ret;
+
+ disp = devm_kzalloc(&pdev->dev, sizeof(*disp), GFP_KERNEL);
+ if (!disp)
+ return -ENOMEM;
+ disp->dev = &pdev->dev;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "blend");
+ disp->blend.base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(disp->blend.base))
+ return PTR_ERR(disp->blend.base);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "av_buf");
+ disp->av_buf.base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(disp->av_buf.base))
+ return PTR_ERR(disp->av_buf.base);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aud");
+ disp->aud.base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(disp->aud.base))
+ return PTR_ERR(disp->aud.base);
+
+ dpsub = platform_get_drvdata(pdev);
+ dpsub->disp = disp;
+ disp->dpsub = dpsub;
+
+ ret = zynqmp_disp_enumerate_fmts(disp);
+ if (ret)
+ return ret;
+
+ /* Try the live PL video clock */
+ disp->_pl_pclk = devm_clk_get(disp->dev, "dp_live_video_in_clk");
+ if (!IS_ERR(disp->_pl_pclk)) {
+ disp->pclk = disp->_pl_pclk;
+ ret = zynqmp_disp_clk_enable_disable(disp->pclk,
+ &disp->pclk_en);
+ if (ret)
+ disp->pclk = NULL;
+ } else if (PTR_ERR(disp->_pl_pclk) == -EPROBE_DEFER) {
+ return PTR_ERR(disp->_pl_pclk);
+ }
+
+ /* If the live PL video clock is not valid, fall back to PS clock */
+ if (!disp->pclk) {
+ disp->_ps_pclk = devm_clk_get(disp->dev, "dp_vtc_pixel_clk_in");
+ if (IS_ERR(disp->_ps_pclk)) {
+ dev_err(disp->dev, "failed to init any video clock\n");
+ return PTR_ERR(disp->_ps_pclk);
+ }
+ disp->pclk = disp->_ps_pclk;
+ ret = zynqmp_disp_clk_enable_disable(disp->pclk,
+ &disp->pclk_en);
+ if (ret) {
+ dev_err(disp->dev, "failed to init any video clock\n");
+ return ret;
+ }
+ }
+
+ disp->aclk = devm_clk_get(disp->dev, "dp_apb_clk");
+ if (IS_ERR(disp->aclk))
+ return PTR_ERR(disp->aclk);
+ ret = zynqmp_disp_clk_enable(disp->aclk, &disp->aclk_en);
+ if (ret) {
+ dev_err(disp->dev, "failed to enable the APB clk\n");
+ return ret;
+ }
+
+ /* Try the live PL audio clock */
+ disp->_pl_audclk = devm_clk_get(disp->dev, "dp_live_audio_aclk");
+ if (!IS_ERR(disp->_pl_audclk)) {
+ disp->audclk = disp->_pl_audclk;
+ ret = zynqmp_disp_clk_enable_disable(disp->audclk,
+ &disp->audclk_en);
+ if (ret)
+ disp->audclk = NULL;
+ }
+
+ /* If the live PL audio clock is not valid, fall back to PS clock */
+ if (!disp->audclk) {
+ disp->_ps_audclk = devm_clk_get(disp->dev, "dp_aud_clk");
+ if (!IS_ERR(disp->_ps_audclk)) {
+ disp->audclk = disp->_ps_audclk;
+ ret = zynqmp_disp_clk_enable_disable(disp->audclk,
+ &disp->audclk_en);
+ if (ret)
+ disp->audclk = NULL;
+ }
+
+ if (!disp->audclk) {
+ dev_err(disp->dev,
+ "audio is disabled due to clock failure\n");
+ }
+ }
+
+ ret = zynqmp_disp_layer_create(disp);
+ if (ret)
+ goto error_aclk;
+
+ return 0;
+
+error_aclk:
+ zynqmp_disp_clk_disable(disp->aclk, &disp->aclk_en);
+ return ret;
+}
+
+int zynqmp_disp_remove(struct platform_device *pdev)
+{
+ struct zynqmp_dpsub *dpsub = platform_get_drvdata(pdev);
+ struct zynqmp_disp *disp = dpsub->disp;
+
+ zynqmp_disp_layer_destroy(disp);
+ if (disp->audclk)
+ zynqmp_disp_clk_disable(disp->audclk, &disp->audclk_en);
+ zynqmp_disp_clk_disable(disp->aclk, &disp->aclk_en);
+ zynqmp_disp_clk_disable(disp->pclk, &disp->pclk_en);
+ dpsub->disp = NULL;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.h b/drivers/gpu/drm/xlnx/zynqmp_disp.h
new file mode 100644
index 0000000..28d8188
--- /dev/null
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.h
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP Display Driver
+ *
+ * Copyright (C) 2017 - 2018 Xilinx, Inc.
+ *
+ * Author: Hyun Woo Kwon <hyun.kwon-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ZYNQMP_DISP_H_
+#define _ZYNQMP_DISP_H_
+
+struct zynqmp_disp;
+
+void zynqmp_disp_handle_vblank(struct zynqmp_disp *disp);
+unsigned int zynqmp_disp_get_apb_clk_rate(struct zynqmp_disp *disp);
+bool zynqmp_disp_aud_enabled(struct zynqmp_disp *disp);
+unsigned int zynqmp_disp_get_aud_clk_rate(struct zynqmp_disp *disp);
+uint32_t zynqmp_disp_get_crtc_mask(struct zynqmp_disp *disp);
+
+int zynqmp_disp_bind(struct device *dev, struct device *master, void *data);
+void zynqmp_disp_unbind(struct device *dev, struct device *master, void *data);
+
+int zynqmp_disp_probe(struct platform_device *pdev);
+int zynqmp_disp_remove(struct platform_device *pdev);
+
+#endif /* _ZYNQMP_DISP_H_ */
--
2.7.4
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v4 4/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DisplayPort
[not found] ` <1516930442-10285-1-git-send-email-hyun.kwon-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2018-01-26 1:33 ` [PATCH v4 2/5] dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings Hyun Kwon
2018-01-26 1:34 ` [PATCH v4 3/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display Hyun Kwon
@ 2018-01-26 1:34 ` Hyun Kwon
2018-01-26 1:34 ` [PATCH v4 5/5] drm: xlnx: ZynqMP DP subsystem DRM KMS driver Hyun Kwon
3 siblings, 0 replies; 6+ messages in thread
From: Hyun Kwon @ 2018-01-26 1:34 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Michal Simek, Rob Herring, Daniel Vetter, Laurent Pinchart, Hyun Kwon
This driver creates DRM encoder and connector for ZynqMP DisplayPort.
Signed-off-by: Hyun Kwon <hyun.kwon-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Acked-by: Daniel Vetter <daniel.vetter-/w4YWyX8dFk@public.gmane.org>
---
v2
- Change the SPDX identifier format
- Split drm properties into a separate patch
---
---
drivers/gpu/drm/xlnx/zynqmp_dp.c | 1738 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/xlnx/zynqmp_dp.h | 37 +
2 files changed, 1775 insertions(+)
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.c
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.h
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c
new file mode 100644
index 0000000..9c9f4df
--- /dev/null
+++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
@@ -0,0 +1,1738 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP DisplayPort Driver
+ *
+ * Copyright (C) 2017 - 2018 Xilinx, Inc.
+ *
+ * Author: Hyun Woo Kwon <hyun.kwon-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_connector.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_of.h>
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/uaccess.h>
+
+#include "zynqmp_disp.h"
+#include "zynqmp_dpsub.h"
+
+static uint zynqmp_dp_aux_timeout_ms = 50;
+module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444);
+MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
+
+/*
+ * Some sink requires a delay after power on request
+ */
+static uint zynqmp_dp_power_on_delay_ms = 4;
+module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444);
+MODULE_PARM_DESC(aux_timeout_ms, "DP power on delay in msec (default: 4)");
+
+/* Link configuration registers */
+#define ZYNQMP_DP_TX_LINK_BW_SET 0x0
+#define ZYNQMP_DP_TX_LANE_CNT_SET 0x4
+#define ZYNQMP_DP_TX_ENHANCED_FRAME_EN 0x8
+#define ZYNQMP_DP_TX_TRAINING_PATTERN_SET 0xc
+#define ZYNQMP_DP_TX_SCRAMBLING_DISABLE 0x14
+#define ZYNQMP_DP_TX_DOWNSPREAD_CTL 0x18
+#define ZYNQMP_DP_TX_SW_RESET 0x1c
+#define ZYNQMP_DP_TX_SW_RESET_STREAM1 BIT(0)
+#define ZYNQMP_DP_TX_SW_RESET_STREAM2 BIT(1)
+#define ZYNQMP_DP_TX_SW_RESET_STREAM3 BIT(2)
+#define ZYNQMP_DP_TX_SW_RESET_STREAM4 BIT(3)
+#define ZYNQMP_DP_TX_SW_RESET_AUX BIT(7)
+#define ZYNQMP_DP_TX_SW_RESET_ALL (ZYNQMP_DP_TX_SW_RESET_STREAM1 | \
+ ZYNQMP_DP_TX_SW_RESET_STREAM2 | \
+ ZYNQMP_DP_TX_SW_RESET_STREAM3 | \
+ ZYNQMP_DP_TX_SW_RESET_STREAM4 | \
+ ZYNQMP_DP_TX_SW_RESET_AUX)
+
+/* Core enable registers */
+#define ZYNQMP_DP_TX_ENABLE 0x80
+#define ZYNQMP_DP_TX_ENABLE_MAIN_STREAM 0x84
+#define ZYNQMP_DP_TX_FORCE_SCRAMBLER_RESET 0xc0
+#define ZYNQMP_DP_TX_VERSION 0xf8
+#define ZYNQMP_DP_TX_VERSION_MAJOR_MASK GENMASK(31, 24)
+#define ZYNQMP_DP_TX_VERSION_MAJOR_SHIFT 24
+#define ZYNQMP_DP_TX_VERSION_MINOR_MASK GENMASK(23, 16)
+#define ZYNQMP_DP_TX_VERSION_MINOR_SHIFT 16
+#define ZYNQMP_DP_TX_VERSION_REVISION_MASK GENMASK(15, 12)
+#define ZYNQMP_DP_TX_VERSION_REVISION_SHIFT 12
+#define ZYNQMP_DP_TX_VERSION_PATCH_MASK GENMASK(11, 8)
+#define ZYNQMP_DP_TX_VERSION_PATCH_SHIFT 8
+#define ZYNQMP_DP_TX_VERSION_INTERNAL_MASK GENMASK(7, 0)
+#define ZYNQMP_DP_TX_VERSION_INTERNAL_SHIFT 0
+
+/* Core ID registers */
+#define ZYNQMP_DP_TX_CORE_ID 0xfc
+#define ZYNQMP_DP_TX_CORE_ID_MAJOR_MASK GENMASK(31, 24)
+#define ZYNQMP_DP_TX_CORE_ID_MAJOR_SHIFT 24
+#define ZYNQMP_DP_TX_CORE_ID_MINOR_MASK GENMASK(23, 16)
+#define ZYNQMP_DP_TX_CORE_ID_MINOR_SHIFT 16
+#define ZYNQMP_DP_TX_CORE_ID_REVISION_MASK GENMASK(15, 8)
+#define ZYNQMP_DP_TX_CORE_ID_REVISION_SHIFT 8
+#define ZYNQMP_DP_TX_CORE_ID_DIRECTION GENMASK(1)
+
+/* AUX channel interface registers */
+#define ZYNQMP_DP_TX_AUX_COMMAND 0x100
+#define ZYNQMP_DP_TX_AUX_COMMAND_CMD_SHIFT 8
+#define ZYNQMP_DP_TX_AUX_COMMAND_ADDRESS_ONLY BIT(12)
+#define ZYNQMP_DP_TX_AUX_COMMAND_BYTES_SHIFT 0
+#define ZYNQMP_DP_TX_AUX_WRITE_FIFO 0x104
+#define ZYNQMP_DP_TX_AUX_ADDRESS 0x108
+#define ZYNQMP_DP_TX_CLK_DIVIDER 0x10c
+#define ZYNQMP_DP_TX_CLK_DIVIDER_MHZ 1000000
+#define ZYNQMP_DP_TX_CLK_DIVIDER_AUX_FILTER_SHIFT 8
+#define ZYNQMP_DP_TX_INTR_SIGNAL_STATE 0x130
+#define ZYNQMP_DP_TX_INTR_SIGNAL_STATE_HPD BIT(0)
+#define ZYNQMP_DP_TX_INTR_SIGNAL_STATE_REQUEST BIT(1)
+#define ZYNQMP_DP_TX_INTR_SIGNAL_STATE_REPLY BIT(2)
+#define ZYNQMP_DP_TX_INTR_SIGNAL_STATE_REPLY_TIMEOUT BIT(3)
+#define ZYNQMP_DP_TX_AUX_REPLY_DATA 0x134
+#define ZYNQMP_DP_TX_AUX_REPLY_CODE 0x138
+#define ZYNQMP_DP_TX_AUX_REPLY_CODE_AUX_ACK (0)
+#define ZYNQMP_DP_TX_AUX_REPLY_CODE_AUX_NACK BIT(0)
+#define ZYNQMP_DP_TX_AUX_REPLY_CODE_AUX_DEFER BIT(1)
+#define ZYNQMP_DP_TX_AUX_REPLY_CODE_I2C_ACK (0)
+#define ZYNQMP_DP_TX_AUX_REPLY_CODE_I2C_NACK BIT(2)
+#define ZYNQMP_DP_TX_AUX_REPLY_CODE_I2C_DEFER BIT(3)
+#define ZYNQMP_DP_TX_AUX_REPLY_CNT 0x13c
+#define ZYNQMP_DP_TX_AUX_REPLY_CNT_MASK 0xff
+#define ZYNQMP_DP_TX_INTR_STATUS 0x140
+#define ZYNQMP_DP_TX_INTR_MASK 0x144
+#define ZYNQMP_DP_TX_INTR_HPD_IRQ BIT(0)
+#define ZYNQMP_DP_TX_INTR_HPD_EVENT BIT(1)
+#define ZYNQMP_DP_TX_INTR_REPLY_RECV BIT(2)
+#define ZYNQMP_DP_TX_INTR_REPLY_TIMEOUT BIT(3)
+#define ZYNQMP_DP_TX_INTR_HPD_PULSE BIT(4)
+#define ZYNQMP_DP_TX_INTR_EXT_PKT_TXD BIT(5)
+#define ZYNQMP_DP_TX_INTR_LIV_ABUF_UNDRFLW BIT(12)
+#define ZYNQMP_DP_TX_INTR_VBLANK_START BIT(13)
+#define ZYNQMP_DP_TX_INTR_PIXEL0_MATCH BIT(14)
+#define ZYNQMP_DP_TX_INTR_PIXEL1_MATCH BIT(15)
+#define ZYNQMP_DP_TX_INTR_CHBUF_UNDERFLW_MASK 0x3f0000
+#define ZYNQMP_DP_TX_INTR_CHBUF_OVERFLW_MASK 0xfc00000
+#define ZYNQMP_DP_TX_INTR_CUST_TS_2 BIT(28)
+#define ZYNQMP_DP_TX_INTR_CUST_TS BIT(29)
+#define ZYNQMP_DP_TX_INTR_EXT_VSYNC_TS BIT(30)
+#define ZYNQMP_DP_TX_INTR_VSYNC_TS BIT(31)
+#define ZYNQMP_DP_TX_INTR_ALL (ZYNQMP_DP_TX_INTR_HPD_IRQ | \
+ ZYNQMP_DP_TX_INTR_HPD_EVENT | \
+ ZYNQMP_DP_TX_INTR_REPLY_RECV | \
+ ZYNQMP_DP_TX_INTR_REPLY_TIMEOUT | \
+ ZYNQMP_DP_TX_INTR_HPD_PULSE | \
+ ZYNQMP_DP_TX_INTR_EXT_PKT_TXD | \
+ ZYNQMP_DP_TX_INTR_LIV_ABUF_UNDRFLW | \
+ ZYNQMP_DP_TX_INTR_CHBUF_UNDERFLW_MASK | \
+ ZYNQMP_DP_TX_INTR_CHBUF_OVERFLW_MASK)
+#define ZYNQMP_DP_TX_NO_INTR_ALL (ZYNQMP_DP_TX_INTR_PIXEL0_MATCH | \
+ ZYNQMP_DP_TX_INTR_PIXEL1_MATCH | \
+ ZYNQMP_DP_TX_INTR_CUST_TS_2 | \
+ ZYNQMP_DP_TX_INTR_CUST_TS | \
+ ZYNQMP_DP_TX_INTR_EXT_VSYNC_TS | \
+ ZYNQMP_DP_TX_INTR_VSYNC_TS)
+#define ZYNQMP_DP_TX_REPLY_DATA_CNT 0x148
+#define ZYNQMP_DP_SUB_TX_INTR_STATUS 0x3a0
+#define ZYNQMP_DP_SUB_TX_INTR_MASK 0x3a4
+#define ZYNQMP_DP_SUB_TX_INTR_EN 0x3a8
+#define ZYNQMP_DP_SUB_TX_INTR_DS 0x3ac
+
+/* Main stream attribute registers */
+#define ZYNQMP_DP_TX_MAIN_STREAM_HTOTAL 0x180
+#define ZYNQMP_DP_TX_MAIN_STREAM_VTOTAL 0x184
+#define ZYNQMP_DP_TX_MAIN_STREAM_POLARITY 0x188
+#define ZYNQMP_DP_TX_MAIN_STREAM_POLARITY_HSYNC_SHIFT 0
+#define ZYNQMP_DP_TX_MAIN_STREAM_POLARITY_VSYNC_SHIFT 1
+#define ZYNQMP_DP_TX_MAIN_STREAM_HSWIDTH 0x18c
+#define ZYNQMP_DP_TX_MAIN_STREAM_VSWIDTH 0x190
+#define ZYNQMP_DP_TX_MAIN_STREAM_HRES 0x194
+#define ZYNQMP_DP_TX_MAIN_STREAM_VRES 0x198
+#define ZYNQMP_DP_TX_MAIN_STREAM_HSTART 0x19c
+#define ZYNQMP_DP_TX_MAIN_STREAM_VSTART 0x1a0
+#define ZYNQMP_DP_TX_MAIN_STREAM_MISC0 0x1a4
+#define ZYNQMP_DP_TX_MAIN_STREAM_MISC0_SYNC BIT(0)
+#define ZYNQMP_DP_TX_MAIN_STREAM_MISC0_FORMAT_SHIFT 1
+#define ZYNQMP_DP_TX_MAIN_STREAM_MISC0_DYNAMIC_RANGE BIT(3)
+#define ZYNQMP_DP_TX_MAIN_STREAM_MISC0_YCBCR_COLRIMETRY BIT(4)
+#define ZYNQMP_DP_TX_MAIN_STREAM_MISC0_BPC_SHIFT 5
+#define ZYNQMP_DP_TX_MAIN_STREAM_MISC1 0x1a8
+#define ZYNQMP_DP_TX_MAIN_STREAM_MISC0_INTERLACED_VERT BIT(0)
+#define ZYNQMP_DP_TX_MAIN_STREAM_MISC0_STEREO_VID_SHIFT 1
+#define ZYNQMP_DP_TX_M_VID 0x1ac
+#define ZYNQMP_DP_TX_TRANSFER_UNIT_SIZE 0x1b0
+#define ZYNQMP_DP_TX_DEF_TRANSFER_UNIT_SIZE 64
+#define ZYNQMP_DP_TX_N_VID 0x1b4
+#define ZYNQMP_DP_TX_USER_PIXEL_WIDTH 0x1b8
+#define ZYNQMP_DP_TX_USER_DATA_CNT_PER_LANE 0x1bc
+#define ZYNQMP_DP_TX_MIN_BYTES_PER_TU 0x1c4
+#define ZYNQMP_DP_TX_FRAC_BYTES_PER_TU 0x1c8
+#define ZYNQMP_DP_TX_INIT_WAIT 0x1cc
+
+/* PHY configuration and status registers */
+#define ZYNQMP_DP_TX_PHY_CONFIG 0x200
+#define ZYNQMP_DP_TX_PHY_CONFIG_PHY_RESET BIT(0)
+#define ZYNQMP_DP_TX_PHY_CONFIG_GTTX_RESET BIT(1)
+#define ZYNQMP_DP_TX_PHY_CONFIG_PHY_PMA_RESET BIT(8)
+#define ZYNQMP_DP_TX_PHY_CONFIG_PHY_PCS_RESET BIT(9)
+#define ZYNQMP_DP_TX_PHY_CONFIG_ALL_RESET (ZYNQMP_DP_TX_PHY_CONFIG_PHY_RESET | \
+ ZYNQMP_DP_TX_PHY_CONFIG_GTTX_RESET | \
+ ZYNQMP_DP_TX_PHY_CONFIG_PHY_PMA_RESET | \
+ ZYNQMP_DP_TX_PHY_CONFIG_PHY_PCS_RESET)
+#define ZYNQMP_DP_TX_PHY_PREEMPHASIS_LANE_0 0x210
+#define ZYNQMP_DP_TX_PHY_PREEMPHASIS_LANE_1 0x214
+#define ZYNQMP_DP_TX_PHY_PREEMPHASIS_LANE_2 0x218
+#define ZYNQMP_DP_TX_PHY_PREEMPHASIS_LANE_3 0x21c
+#define ZYNQMP_DP_TX_PHY_VOLTAGE_DIFF_LANE_0 0x220
+#define ZYNQMP_DP_TX_PHY_VOLTAGE_DIFF_LANE_1 0x224
+#define ZYNQMP_DP_TX_PHY_VOLTAGE_DIFF_LANE_2 0x228
+#define ZYNQMP_DP_TX_PHY_VOLTAGE_DIFF_LANE_3 0x22c
+#define ZYNQMP_DP_TX_PHY_CLOCK_FEEDBACK_SETTING 0x234
+#define ZYNQMP_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_162 0x1
+#define ZYNQMP_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_270 0x3
+#define ZYNQMP_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_540 0x5
+#define ZYNQMP_DP_TX_PHY_POWER_DOWN 0x238
+#define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_0 BIT(0)
+#define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_1 BIT(1)
+#define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_2 BIT(2)
+#define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_3 BIT(3)
+#define ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL 0xf
+#define ZYNQMP_DP_TX_PHY_PRECURSOR_LANE_0 0x23c
+#define ZYNQMP_DP_TX_PHY_PRECURSOR_LANE_1 0x240
+#define ZYNQMP_DP_TX_PHY_PRECURSOR_LANE_2 0x244
+#define ZYNQMP_DP_TX_PHY_PRECURSOR_LANE_3 0x248
+#define ZYNQMP_DP_TX_PHY_POSTCURSOR_LANE_0 0x24c
+#define ZYNQMP_DP_TX_PHY_POSTCURSOR_LANE_1 0x250
+#define ZYNQMP_DP_TX_PHY_POSTCURSOR_LANE_2 0x254
+#define ZYNQMP_DP_TX_PHY_POSTCURSOR_LANE_3 0x258
+#define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 0x24c
+#define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_1 0x250
+#define ZYNQMP_DP_TX_PHY_STATUS 0x280
+#define ZYNQMP_DP_TX_PHY_STATUS_PLL_LOCKED_SHIFT 4
+#define ZYNQMP_DP_TX_PHY_STATUS_FPGA_PLL_LOCKED BIT(6)
+
+/* Audio registers */
+#define ZYNQMP_DP_TX_AUDIO_CONTROL 0x300
+#define ZYNQMP_DP_TX_AUDIO_CHANNELS 0x304
+#define ZYNQMP_DP_TX_AUDIO_INFO_DATA 0x308
+#define ZYNQMP_DP_TX_AUDIO_M_AUD 0x328
+#define ZYNQMP_DP_TX_AUDIO_N_AUD 0x32c
+#define ZYNQMP_DP_TX_AUDIO_EXT_DATA 0x330
+
+#define ZYNQMP_DP_MISC0_RGB (0)
+#define ZYNQMP_DP_MISC0_YCRCB_422 (5 << 1)
+#define ZYNQMP_DP_MISC0_YCRCB_444 (6 << 1)
+#define ZYNQMP_DP_MISC0_FORMAT_MASK 0xe
+#define ZYNQMP_DP_MISC0_BPC_6 (0 << 5)
+#define ZYNQMP_DP_MISC0_BPC_8 (1 << 5)
+#define ZYNQMP_DP_MISC0_BPC_10 (2 << 5)
+#define ZYNQMP_DP_MISC0_BPC_12 (3 << 5)
+#define ZYNQMP_DP_MISC0_BPC_16 (4 << 5)
+#define ZYNQMP_DP_MISC0_BPC_MASK 0xe0
+#define ZYNQMP_DP_MISC1_Y_ONLY (1 << 7)
+
+#define ZYNQMP_DP_MAX_LANES 2
+#define ZYNQMP_MAX_FREQ 3000000
+
+#define DP_REDUCED_BIT_RATE 162000
+#define DP_HIGH_BIT_RATE 270000
+#define DP_HIGH_BIT_RATE2 540000
+#define DP_MAX_TRAINING_TRIES 5
+#define DP_V1_2 0x12
+
+/**
+ * struct zynqmp_dp_link_config - Common link config between source and sink
+ * @max_rate: maximum link rate
+ * @max_lanes: maximum number of lanes
+ */
+struct zynqmp_dp_link_config {
+ int max_rate;
+ u8 max_lanes;
+};
+
+/**
+ * struct zynqmp_dp_mode - Configured mode of DisplayPort
+ * @bw_code: code for bandwidth(link rate)
+ * @lane_cnt: number of lanes
+ * @pclock: pixel clock frequency of current mode
+ * @fmt: format identifier string
+ */
+struct zynqmp_dp_mode {
+ u8 bw_code;
+ u8 lane_cnt;
+ int pclock;
+ const char *fmt;
+};
+
+/**
+ * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
+ * @misc0: misc0 configuration (per DP v1.2 spec)
+ * @misc1: misc1 configuration (per DP v1.2 spec)
+ * @bpp: bits per pixel
+ * @bpc: bits per component
+ * @num_colors: number of color components
+ */
+struct zynqmp_dp_config {
+ u8 misc0;
+ u8 misc1;
+ u8 bpp;
+ u8 bpc;
+ u8 num_colors;
+};
+
+/**
+ * struct zynqmp_dp - Xilinx DisplayPort core
+ * @encoder: the drm encoder structure
+ * @connector: the drm connector structure
+ * @dev: device structure
+ * @dpsub: Display subsystem
+ * @drm: DRM core
+ * @iomem: device I/O memory for register access
+ * @irq: irq
+ * @config: IP core configuration from DTS
+ * @aux: aux channel
+ * @phy: PHY handles for DP lanes
+ * @num_lanes: number of enabled phy lanes
+ * @hpd_work: hot plug detection worker
+ * @status: connection status
+ * @enabled: flag to indicate if the device is enabled
+ * @dpms: current dpms state
+ * @dpcd: DP configuration data from currently connected sink device
+ * @link_config: common link configuration between IP core and sink device
+ * @mode: current mode between IP core and sink device
+ * @train_set: set of training data
+ */
+struct zynqmp_dp {
+ struct drm_encoder encoder;
+ struct drm_connector connector;
+ struct device *dev;
+ struct zynqmp_dpsub *dpsub;
+ struct drm_device *drm;
+ void __iomem *iomem;
+ int irq;
+
+ struct zynqmp_dp_config config;
+ struct drm_dp_aux aux;
+ struct phy *phy[ZYNQMP_DP_MAX_LANES];
+ u8 num_lanes;
+ struct delayed_work hpd_work;
+ enum drm_connector_status status;
+ bool enabled;
+
+ int dpms;
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+ struct zynqmp_dp_link_config link_config;
+ struct zynqmp_dp_mode mode;
+ u8 train_set[ZYNQMP_DP_MAX_LANES];
+};
+
+static inline struct zynqmp_dp *encoder_to_dp(struct drm_encoder *encoder)
+{
+ return container_of(encoder, struct zynqmp_dp, encoder);
+}
+
+static inline struct zynqmp_dp *connector_to_dp(struct drm_connector *connector)
+{
+ return container_of(connector, struct zynqmp_dp, connector);
+}
+
+static void zynqmp_dp_write(void __iomem *base, int offset, u32 val)
+{
+ writel(val, base + offset);
+}
+
+static u32 zynqmp_dp_read(void __iomem *base, int offset)
+{
+ return readl(base + offset);
+}
+
+static void zynqmp_dp_clr(void __iomem *base, int offset, u32 clr)
+{
+ zynqmp_dp_write(base, offset, zynqmp_dp_read(base, offset) & ~clr);
+}
+
+static void zynqmp_dp_set(void __iomem *base, int offset, u32 set)
+{
+ zynqmp_dp_write(base, offset, zynqmp_dp_read(base, offset) | set);
+}
+
+/*
+ * Internal functions: used by zynqmp_disp.c
+ */
+
+/**
+ * zynqmp_dp_update_bpp - Update the current bpp config
+ * @dp: DisplayPort IP core structure
+ *
+ * Update the current bpp based on the color format: bpc & num_colors.
+ * Any function that changes bpc or num_colors should call this
+ * to keep the bpp value in sync.
+ */
+static void zynqmp_dp_update_bpp(struct zynqmp_dp *dp)
+{
+ struct zynqmp_dp_config *config = &dp->config;
+
+ config->bpp = dp->config.bpc * dp->config.num_colors;
+}
+
+/**
+ * zynqmp_dp_set_color - Set the color
+ * @dp: DisplayPort IP core structure
+ * @color: color string, from zynqmp_disp_color_enum
+ *
+ * Update misc register values based on @color string.
+ *
+ * Return: 0 on success, or -EINVAL.
+ */
+int zynqmp_dp_set_color(struct zynqmp_dp *dp, const char *color)
+{
+ struct zynqmp_dp_config *config = &dp->config;
+
+ config->misc0 &= ~ZYNQMP_DP_MISC0_FORMAT_MASK;
+ config->misc1 &= ~ZYNQMP_DP_MISC1_Y_ONLY;
+ if (strcmp(color, "rgb") == 0) {
+ config->misc0 |= ZYNQMP_DP_MISC0_RGB;
+ config->num_colors = 3;
+ } else if (strcmp(color, "ycrcb422") == 0) {
+ config->misc0 |= ZYNQMP_DP_MISC0_YCRCB_422;
+ config->num_colors = 2;
+ } else if (strcmp(color, "ycrcb444") == 0) {
+ config->misc0 |= ZYNQMP_DP_MISC0_YCRCB_444;
+ config->num_colors = 3;
+ } else if (strcmp(color, "yonly") == 0) {
+ config->misc1 |= ZYNQMP_DP_MISC1_Y_ONLY;
+ config->num_colors = 1;
+ } else {
+ dev_err(dp->dev, "Invalid colormetry in DT\n");
+ return -EINVAL;
+ }
+ zynqmp_dp_update_bpp(dp);
+
+ return 0;
+}
+
+/**
+ * zynqmp_dp_enable_vblank - Enable vblank
+ * @dp: DisplayPort IP core structure
+ *
+ * Enable vblank interrupt
+ */
+void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp)
+{
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_SUB_TX_INTR_EN,
+ ZYNQMP_DP_TX_INTR_VBLANK_START);
+}
+
+/**
+ * zynqmp_dp_disable_vblank - Disable vblank
+ * @dp: DisplayPort IP core structure
+ *
+ * Disable vblank interrupt
+ */
+void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp)
+{
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_SUB_TX_INTR_DS,
+ ZYNQMP_DP_TX_INTR_VBLANK_START);
+}
+
+/*
+ * DP PHY functions
+ */
+
+/**
+ * zynqmp_dp_init_phy - Initialize the phy
+ * @dp: DisplayPort IP core structure
+ *
+ * Initialize the phy.
+ *
+ * Return: 0 if the phy instances are initialized correctly, or the error code
+ * returned from the callee functions.
+ */
+static int zynqmp_dp_init_phy(struct zynqmp_dp *dp)
+{
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < ZYNQMP_DP_MAX_LANES; i++) {
+ ret = phy_init(dp->phy[i]);
+ if (ret) {
+ dev_err(dp->dev, "failed to init phy lane %d\n", i);
+ return ret;
+ }
+ }
+
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_SUB_TX_INTR_DS,
+ ZYNQMP_DP_TX_INTR_ALL);
+ zynqmp_dp_clr(dp->iomem, ZYNQMP_DP_TX_PHY_CONFIG,
+ ZYNQMP_DP_TX_PHY_CONFIG_ALL_RESET);
+
+ return 0;
+}
+
+/**
+ * zynqmp_dp_exit_phy - Exit the phy
+ * @dp: DisplayPort IP core structure
+ *
+ * Exit the phy.
+ */
+static void zynqmp_dp_exit_phy(struct zynqmp_dp *dp)
+{
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < ZYNQMP_DP_MAX_LANES; i++) {
+ ret = phy_exit(dp->phy[i]);
+ if (ret)
+ dev_err(dp->dev, "failed to exit phy(%d) %d\n", i, ret);
+ }
+}
+
+/**
+ * zynqmp_dp_phy_ready - Check if PHY is ready
+ * @dp: DisplayPort IP core structure
+ *
+ * Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times.
+ * This amount of delay was suggested by IP designer.
+ *
+ * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready.
+ */
+static int zynqmp_dp_phy_ready(struct zynqmp_dp *dp)
+{
+ u32 i, reg, ready;
+
+ ready = (1 << ZYNQMP_DP_MAX_LANES) - 1;
+
+ /* Wait for 100 * 1ms. This should be enough time for PHY to be ready */
+ for (i = 0; ; i++) {
+ reg = zynqmp_dp_read(dp->iomem, ZYNQMP_DP_TX_PHY_STATUS);
+ if ((reg & ready) == ready)
+ return 0;
+
+ if (i == 100) {
+ dev_err(dp->dev, "PHY isn't ready\n");
+ return -ENODEV;
+ }
+
+ usleep_range(1000, 1100);
+ }
+
+ return 0;
+}
+
+/*
+ * DP functions
+ */
+
+/**
+ * zynqmp_dp_max_rate - Calculate and return available max pixel clock
+ * @link_rate: link rate (Kilo-bytes / sec)
+ * @lane_num: number of lanes
+ * @bpp: bits per pixel
+ *
+ * Return: max pixel clock (KHz) supported by current link config.
+ */
+static inline int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp)
+{
+ return link_rate * lane_num * 8 / bpp;
+}
+
+/**
+ * zynqmp_dp_mode_configure - Configure the link values
+ * @dp: DisplayPort IP core structure
+ * @pclock: pixel clock for requested display mode
+ * @current_bw: current link rate
+ *
+ * Find the link configuration values, rate and lane count for requested pixel
+ * clock @pclock. The @pclock is stored in the mode to be used in other
+ * functions later. The returned rate is downshifted from the current rate
+ * @current_bw.
+ *
+ * Return: Current link rate code, or -EINVAL.
+ */
+static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock,
+ u8 current_bw)
+{
+ int max_rate = dp->link_config.max_rate;
+ u8 bws[3] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
+ u8 max_lanes = dp->link_config.max_lanes;
+ u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
+ u8 bpp = dp->config.bpp;
+ u8 lane_cnt;
+ s8 i;
+
+ if (current_bw == DP_LINK_BW_1_62) {
+ dev_err(dp->dev, "can't downshift. already lowest link rate\n");
+ return -EINVAL;
+ }
+
+ for (i = ARRAY_SIZE(bws) - 1; i >= 0; i--) {
+ if (current_bw && bws[i] >= current_bw)
+ continue;
+
+ if (bws[i] <= max_link_rate_code)
+ break;
+ }
+
+ for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
+ int bw;
+ u32 rate;
+
+ bw = drm_dp_bw_code_to_link_rate(bws[i]);
+ rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);
+ if (pclock <= rate) {
+ dp->mode.bw_code = bws[i];
+ dp->mode.lane_cnt = lane_cnt;
+ dp->mode.pclock = pclock;
+ return dp->mode.bw_code;
+ }
+ }
+
+ dev_err(dp->dev, "failed to configure link values\n");
+
+ return -EINVAL;
+}
+
+/**
+ * zynqmp_dp_adjust_train - Adjust train values
+ * @dp: DisplayPort IP core structure
+ * @link_status: link status from sink which contains requested training values
+ */
+static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp,
+ u8 link_status[DP_LINK_STATUS_SIZE])
+{
+ u8 *train_set = dp->train_set;
+ u8 voltage = 0, preemphasis = 0;
+ u8 i;
+
+ for (i = 0; i < dp->mode.lane_cnt; i++) {
+ u8 v = drm_dp_get_adjust_request_voltage(link_status, i);
+ u8 p = drm_dp_get_adjust_request_pre_emphasis(link_status, i);
+
+ if (v > voltage)
+ voltage = v;
+
+ if (p > preemphasis)
+ preemphasis = p;
+ }
+
+ if (voltage >= DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
+ voltage |= DP_TRAIN_MAX_SWING_REACHED;
+
+ if (preemphasis >= DP_TRAIN_PRE_EMPH_LEVEL_2)
+ preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+ for (i = 0; i < dp->mode.lane_cnt; i++)
+ train_set[i] = voltage | preemphasis;
+}
+
+/**
+ * zynqmp_dp_update_vs_emph - Update the training values
+ * @dp: DisplayPort IP core structure
+ *
+ * Update the training values based on the request from sink. The mapped values
+ * are predefined, and values(vs, pe, pc) are from the device manual.
+ *
+ * Return: 0 if vs and emph are updated successfully, or the error code returned
+ * by drm_dp_dpcd_write().
+ */
+static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp)
+{
+ u8 *train_set = dp->train_set;
+ u8 i, v_level, p_level;
+ int ret;
+
+ ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set,
+ dp->mode.lane_cnt);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < dp->mode.lane_cnt; i++) {
+ u32 reg = ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4;
+
+ v_level = (train_set[i] & DP_TRAIN_VOLTAGE_SWING_MASK) >>
+ DP_TRAIN_VOLTAGE_SWING_SHIFT;
+ p_level = (train_set[i] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
+ DP_TRAIN_PRE_EMPHASIS_SHIFT;
+
+ zynqmp_dp_write(dp->iomem, reg, 0x2);
+ }
+
+ return 0;
+}
+
+/**
+ * zynqmp_dp_link_train_cr - Train clock recovery
+ * @dp: DisplayPort IP core structure
+ *
+ * Return: 0 if clock recovery train is done successfully, or corresponding
+ * error code.
+ */
+static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp)
+{
+ u8 link_status[DP_LINK_STATUS_SIZE];
+ u8 lane_cnt = dp->mode.lane_cnt;
+ u8 vs = 0, tries = 0;
+ u16 max_tries, i;
+ bool cr_done;
+ int ret;
+
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_1);
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_1 |
+ DP_LINK_SCRAMBLING_DISABLE);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * 256 loops should be maximum iterations for 4 lanes and 4 values.
+ * So, This loop should exit before 512 iterations
+ */
+ for (max_tries = 0; max_tries < 512; max_tries++) {
+ ret = zynqmp_dp_update_vs_emph(dp);
+ if (ret)
+ return ret;
+
+ drm_dp_link_train_clock_recovery_delay(dp->dpcd);
+ ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
+ if (ret < 0)
+ return ret;
+
+ cr_done = drm_dp_clock_recovery_ok(link_status, lane_cnt);
+ if (cr_done)
+ break;
+
+ for (i = 0; i < lane_cnt; i++)
+ if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED))
+ break;
+ if (i == lane_cnt)
+ break;
+
+ if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs)
+ tries++;
+ else
+ tries = 0;
+
+ if (tries == DP_MAX_TRAINING_TRIES)
+ break;
+
+ vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
+ zynqmp_dp_adjust_train(dp, link_status);
+ }
+
+ if (!cr_done)
+ return -EIO;
+
+ return 0;
+}
+
+/**
+ * zynqmp_dp_link_train_ce - Train channel equalization
+ * @dp: DisplayPort IP core structure
+ *
+ * Return: 0 if channel equalization train is done successfully, or
+ * corresponding error code.
+ */
+static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp)
+{
+ u8 link_status[DP_LINK_STATUS_SIZE];
+ u8 lane_cnt = dp->mode.lane_cnt;
+ u32 pat, tries;
+ int ret;
+ bool ce_done;
+
+ if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 &&
+ dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED)
+ pat = DP_TRAINING_PATTERN_3;
+ else
+ pat = DP_TRAINING_PATTERN_2;
+
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_TRAINING_PATTERN_SET, pat);
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
+ pat | DP_LINK_SCRAMBLING_DISABLE);
+ if (ret < 0)
+ return ret;
+
+ for (tries = 0; tries < DP_MAX_TRAINING_TRIES; tries++) {
+ ret = zynqmp_dp_update_vs_emph(dp);
+ if (ret)
+ return ret;
+
+ drm_dp_link_train_channel_eq_delay(dp->dpcd);
+ ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
+ if (ret < 0)
+ return ret;
+
+ ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt);
+ if (ce_done)
+ break;
+
+ zynqmp_dp_adjust_train(dp, link_status);
+ }
+
+ if (!ce_done)
+ return -EIO;
+
+ return 0;
+}
+
+/**
+ * zynqmp_dp_link_train - Train the link
+ * @dp: DisplayPort IP core structure
+ *
+ * Return: 0 if all trains are done successfully, or corresponding error code.
+ */
+static int zynqmp_dp_train(struct zynqmp_dp *dp)
+{
+ u32 reg;
+ u8 bw_code = dp->mode.bw_code;
+ u8 lane_cnt = dp->mode.lane_cnt;
+ u8 aux_lane_cnt = lane_cnt;
+ bool enhanced;
+ int ret;
+
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_LANE_CNT_SET, lane_cnt);
+ enhanced = drm_dp_enhanced_frame_cap(dp->dpcd);
+ if (enhanced) {
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_ENHANCED_FRAME_EN, 1);
+ aux_lane_cnt |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ }
+
+ if (dp->dpcd[3] & 0x1) {
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_DOWNSPREAD_CTL, 1);
+ drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL,
+ DP_SPREAD_AMP_0_5);
+ } else {
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_DOWNSPREAD_CTL, 0);
+ drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0);
+ }
+
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to set lane count\n");
+ return ret;
+ }
+
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
+ DP_SET_ANSI_8B10B);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to set ANSI 8B/10B encoding\n");
+ return ret;
+ }
+
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to set DP bandwidth\n");
+ return ret;
+ }
+
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_LINK_BW_SET, bw_code);
+ switch (bw_code) {
+ case DP_LINK_BW_1_62:
+ reg = ZYNQMP_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_162;
+ break;
+ case DP_LINK_BW_2_7:
+ reg = ZYNQMP_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_270;
+ break;
+ case DP_LINK_BW_5_4:
+ default:
+ reg = ZYNQMP_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_540;
+ break;
+ }
+
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_PHY_CLOCK_FEEDBACK_SETTING,
+ reg);
+ ret = zynqmp_dp_phy_ready(dp);
+ if (ret < 0)
+ return ret;
+
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_SCRAMBLING_DISABLE, 1);
+ memset(dp->train_set, 0, 4);
+ ret = zynqmp_dp_link_train_cr(dp);
+ if (ret)
+ return ret;
+
+ ret = zynqmp_dp_link_train_ce(dp);
+ if (ret)
+ return ret;
+
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_DISABLE);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to disable training pattern\n");
+ return ret;
+ }
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_DISABLE);
+
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_SCRAMBLING_DISABLE, 0);
+
+ return 0;
+}
+
+/**
+ * zynqmp_dp_train_loop - Downshift the link rate during training
+ * @dp: DisplayPort IP core structure
+ *
+ * Train the link by downshifting the link rate if training is not successful.
+ */
+static void zynqmp_dp_train_loop(struct zynqmp_dp *dp)
+{
+ struct zynqmp_dp_mode *mode = &dp->mode;
+ u8 bw = mode->bw_code;
+ int ret;
+
+ do {
+ if (dp->status == connector_status_disconnected ||
+ !dp->enabled)
+ return;
+
+ ret = zynqmp_dp_train(dp);
+ if (!ret)
+ return;
+
+ ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw);
+ if (ret < 0)
+ goto err_out;
+
+ bw = ret;
+ } while (bw >= DP_LINK_BW_1_62);
+
+err_out:
+ dev_err(dp->dev, "failed to train the DP link\n");
+}
+
+/*
+ * DP Aux functions
+ */
+
+#define AUX_READ_BIT 0x1
+
+/**
+ * zynqmp_dp_aux_cmd_submit - Submit aux command
+ * @dp: DisplayPort IP core structure
+ * @cmd: aux command
+ * @addr: aux address
+ * @buf: buffer for command data
+ * @bytes: number of bytes for @buf
+ * @reply: reply code to be returned
+ *
+ * Submit an aux command. All aux related commands, native or i2c aux
+ * read/write, are submitted through this function. The function is mapped to
+ * the transfer function of struct drm_dp_aux. This function involves in
+ * multiple register reads/writes, thus synchronization is needed, and it is
+ * done by drm_dp_helper using @hw_mutex. The calling thread goes into sleep
+ * if there's no immediate reply to the command submission. The reply code is
+ * returned at @reply if @reply != NULL.
+ *
+ * Return: 0 if the command is submitted properly, or corresponding error code:
+ * -EBUSY when there is any request already being processed
+ * -ETIMEDOUT when receiving reply is timed out
+ * -EIO when received bytes are less than requested
+ */
+static int zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr,
+ u8 *buf, u8 bytes, u8 *reply)
+{
+ bool is_read = (cmd & AUX_READ_BIT) ? true : false;
+ void __iomem *iomem = dp->iomem;
+ u32 reg, i;
+
+ reg = zynqmp_dp_read(iomem, ZYNQMP_DP_TX_INTR_SIGNAL_STATE);
+ if (reg & ZYNQMP_DP_TX_INTR_SIGNAL_STATE_REQUEST)
+ return -EBUSY;
+
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_AUX_ADDRESS, addr);
+ if (!is_read)
+ for (i = 0; i < bytes; i++)
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_AUX_WRITE_FIFO,
+ buf[i]);
+
+ reg = cmd << ZYNQMP_DP_TX_AUX_COMMAND_CMD_SHIFT;
+ if (!buf || !bytes)
+ reg |= ZYNQMP_DP_TX_AUX_COMMAND_ADDRESS_ONLY;
+ else
+ reg |= (bytes - 1) << ZYNQMP_DP_TX_AUX_COMMAND_BYTES_SHIFT;
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_AUX_COMMAND, reg);
+
+ /* Wait for reply to be delivered upto 2ms */
+ for (i = 0; ; i++) {
+ reg = zynqmp_dp_read(iomem, ZYNQMP_DP_TX_INTR_SIGNAL_STATE);
+ if (reg & ZYNQMP_DP_TX_INTR_SIGNAL_STATE_REPLY)
+ break;
+
+ if (reg & ZYNQMP_DP_TX_INTR_SIGNAL_STATE_REPLY_TIMEOUT ||
+ i == 2)
+ return -ETIMEDOUT;
+
+ usleep_range(1000, 1100);
+ }
+
+ reg = zynqmp_dp_read(iomem, ZYNQMP_DP_TX_AUX_REPLY_CODE);
+ if (reply)
+ *reply = reg;
+
+ if (is_read &&
+ (reg == ZYNQMP_DP_TX_AUX_REPLY_CODE_AUX_ACK ||
+ reg == ZYNQMP_DP_TX_AUX_REPLY_CODE_I2C_ACK)) {
+ reg = zynqmp_dp_read(iomem, ZYNQMP_DP_TX_REPLY_DATA_CNT);
+ if ((reg & ZYNQMP_DP_TX_AUX_REPLY_CNT_MASK) != bytes)
+ return -EIO;
+
+ for (i = 0; i < bytes; i++) {
+ buf[i] = zynqmp_dp_read(iomem,
+ ZYNQMP_DP_TX_AUX_REPLY_DATA);
+ }
+ }
+
+ return 0;
+}
+
+static ssize_t
+zynqmp_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
+{
+ struct zynqmp_dp *dp = container_of(aux, struct zynqmp_dp, aux);
+ int ret;
+ unsigned int i, iter;
+
+ /* Number of loops = timeout in msec / aux delay (400 usec) */
+ iter = zynqmp_dp_aux_timeout_ms * 1000 / 400;
+ iter = iter ? iter : 1;
+
+ for (i = 0; i < iter; i++) {
+ ret = zynqmp_dp_aux_cmd_submit(dp, msg->request, msg->address,
+ msg->buffer, msg->size,
+ &msg->reply);
+ if (!ret) {
+ dev_dbg(dp->dev, "aux %d retries\n", i);
+ return msg->size;
+ }
+
+ if (dp->status == connector_status_disconnected) {
+ dev_dbg(dp->dev, "no connected aux device\n");
+ return -ENODEV;
+ }
+
+ usleep_range(400, 500);
+ }
+
+ dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret);
+
+ return ret;
+}
+
+/**
+ * zynqmp_dp_init_aux - Initialize the DP aux
+ * @dp: DisplayPort IP core structure
+ *
+ * Initialize the DP aux. The aux clock is derived from the axi clock, so
+ * this function gets the axi clock frequency and calculates the filter
+ * value. Additionally, the interrupts and transmitter are enabled.
+ *
+ * Return: 0 on success, error value otherwise
+ */
+static int zynqmp_dp_init_aux(struct zynqmp_dp *dp)
+{
+ unsigned int rate;
+ u32 reg, w;
+
+ rate = zynqmp_disp_get_apb_clk_rate(dp->dpsub->disp);
+ if (rate < ZYNQMP_DP_TX_CLK_DIVIDER_MHZ) {
+ dev_err(dp->dev, "aclk should be higher than 1MHz\n");
+ return -EINVAL;
+ }
+
+ /* Allowable values for this register are: 8, 16, 24, 32, 40, 48 */
+ for (w = 8; w <= 48; w += 8) {
+ /* AUX pulse width should be between 0.4 to 0.6 usec */
+ if (w >= (4 * rate / 10000000) &&
+ w <= (6 * rate / 10000000))
+ break;
+ }
+
+ if (w > 48) {
+ dev_err(dp->dev, "aclk frequency too high\n");
+ return -EINVAL;
+ }
+ reg = w << ZYNQMP_DP_TX_CLK_DIVIDER_AUX_FILTER_SHIFT;
+ reg |= rate / ZYNQMP_DP_TX_CLK_DIVIDER_MHZ;
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_CLK_DIVIDER, reg);
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_SUB_TX_INTR_EN,
+ ZYNQMP_DP_TX_INTR_ALL);
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_SUB_TX_INTR_DS,
+ ZYNQMP_DP_TX_NO_INTR_ALL);
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_ENABLE, 1);
+
+ return 0;
+}
+
+/**
+ * zynqmp_dp_exit_aux - De-initialize the DP aux
+ * @dp: DisplayPort IP core structure
+ *
+ * De-initialize the DP aux. Disable all interrupts which are enabled
+ * through aux initialization, as well as the transmitter.
+ */
+static void zynqmp_dp_exit_aux(struct zynqmp_dp *dp)
+{
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_ENABLE, 0);
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_SUB_TX_INTR_DS, 0xffffffff);
+}
+
+/*
+ * Generic DP functions
+ */
+
+/**
+ * zynqmp_dp_update_misc - Write the misc registers
+ * @dp: DisplayPort IP core structure
+ *
+ * The misc register values are stored in the structure, and this
+ * function applies the values into the registers.
+ */
+static void zynqmp_dp_update_misc(struct zynqmp_dp *dp)
+{
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_MAIN_STREAM_MISC0,
+ dp->config.misc0);
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_MAIN_STREAM_MISC1,
+ dp->config.misc1);
+}
+
+/**
+ * zynqmp_dp_set_bpc - Set bpc value in software misc state
+ * @dp: DisplayPort IP core structure
+ * @bpc: bits per component
+ *
+ * Return: 0 on success, or the fallback bpc value
+ */
+static u8 zynqmp_dp_set_bpc(struct zynqmp_dp *dp, u8 bpc)
+{
+ struct zynqmp_dp_config *config = &dp->config;
+ u8 ret = 0;
+
+ if (dp->connector.display_info.bpc &&
+ dp->connector.display_info.bpc != bpc) {
+ dev_err(dp->dev, "requested bpc (%u) != display info (%u)\n",
+ bpc, dp->connector.display_info.bpc);
+ bpc = dp->connector.display_info.bpc;
+ }
+
+ config->misc0 &= ~ZYNQMP_DP_MISC0_BPC_MASK;
+ switch (bpc) {
+ case 6:
+ config->misc0 |= ZYNQMP_DP_MISC0_BPC_6;
+ break;
+ case 8:
+ config->misc0 |= ZYNQMP_DP_MISC0_BPC_8;
+ break;
+ case 10:
+ config->misc0 |= ZYNQMP_DP_MISC0_BPC_10;
+ break;
+ case 12:
+ config->misc0 |= ZYNQMP_DP_MISC0_BPC_12;
+ break;
+ case 16:
+ config->misc0 |= ZYNQMP_DP_MISC0_BPC_16;
+ break;
+ default:
+ dev_err(dp->dev, "Not supported bpc (%u). fall back to 8bpc\n",
+ bpc);
+ config->misc0 |= ZYNQMP_DP_MISC0_BPC_8;
+ ret = 8;
+ break;
+ }
+ config->bpc = bpc;
+ zynqmp_dp_update_bpp(dp);
+
+ return ret;
+}
+
+/**
+ * zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values
+ * @dp: DisplayPort IP core structure
+ * @mode: requested display mode
+ *
+ * Set the transfer unit, and caculate all transfer unit size related values.
+ * Calculation is based on DP and IP core specification.
+ */
+static void
+zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp,
+ struct drm_display_mode *mode)
+{
+ u32 tu = ZYNQMP_DP_TX_DEF_TRANSFER_UNIT_SIZE;
+ u32 bw, vid_kbytes, avg_bytes_per_tu, init_wait;
+
+ /* Use the max transfer unit size (default) */
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_TRANSFER_UNIT_SIZE, tu);
+
+ vid_kbytes = mode->clock * (dp->config.bpp / 8);
+ bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
+ avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000);
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_MIN_BYTES_PER_TU,
+ avg_bytes_per_tu / 1000);
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_FRAC_BYTES_PER_TU,
+ avg_bytes_per_tu % 1000);
+
+ /* Configure the initial wait cycle based on transfer unit size */
+ if (tu < (avg_bytes_per_tu / 1000))
+ init_wait = 0;
+ else if ((avg_bytes_per_tu / 1000) <= 4)
+ init_wait = tu;
+ else
+ init_wait = tu - avg_bytes_per_tu / 1000;
+
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_INIT_WAIT, init_wait);
+}
+
+/**
+ * zynqmp_dp_encoder_mode_set_stream - Configure the main stream
+ * @dp: DisplayPort IP core structure
+ * @mode: requested display mode
+ *
+ * Configure the main stream based on the requested mode @mode. Calculation is
+ * based on IP core specification.
+ */
+void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp,
+ struct drm_display_mode *mode)
+{
+ void __iomem *iomem = dp->iomem;
+ u8 lane_cnt = dp->mode.lane_cnt;
+ u32 reg, wpl;
+ unsigned int rate;
+
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_MAIN_STREAM_HTOTAL, mode->htotal);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_MAIN_STREAM_VTOTAL, mode->vtotal);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_MAIN_STREAM_POLARITY,
+ (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) <<
+ ZYNQMP_DP_TX_MAIN_STREAM_POLARITY_VSYNC_SHIFT) |
+ (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) <<
+ ZYNQMP_DP_TX_MAIN_STREAM_POLARITY_HSYNC_SHIFT));
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_MAIN_STREAM_HSWIDTH,
+ mode->hsync_end - mode->hsync_start);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_MAIN_STREAM_VSWIDTH,
+ mode->vsync_end - mode->vsync_start);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_MAIN_STREAM_HRES, mode->hdisplay);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_MAIN_STREAM_VRES, mode->vdisplay);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_MAIN_STREAM_HSTART,
+ mode->htotal - mode->hsync_start);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_MAIN_STREAM_VSTART,
+ mode->vtotal - mode->vsync_start);
+
+ /* In synchronous mode, set the diviers */
+ if (dp->config.misc0 & ZYNQMP_DP_TX_MAIN_STREAM_MISC0_SYNC) {
+ reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_N_VID, reg);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_M_VID, mode->clock);
+ rate = zynqmp_disp_get_aud_clk_rate(dp->dpsub->disp);
+ if (rate) {
+ dev_dbg(dp->dev, "Audio rate: %d\n", rate / 512);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_AUDIO_N_AUD, reg);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_AUDIO_M_AUD,
+ rate / 1000);
+ }
+ }
+
+ /* Only 2 channel audio is supported now */
+ if (zynqmp_disp_aud_enabled(dp->dpsub->disp))
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_AUDIO_CHANNELS, 1);
+
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_USER_PIXEL_WIDTH, 1);
+
+ /* Translate to the native 16 bit datapath based on IP core spec */
+ wpl = (mode->hdisplay * dp->config.bpp + 15) / 16;
+ reg = wpl + wpl % lane_cnt - lane_cnt;
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_USER_DATA_CNT_PER_LANE, reg);
+}
+
+/*
+ * DRM connector functions
+ */
+
+static enum drm_connector_status
+zynqmp_dp_connector_detect(struct drm_connector *connector, bool force)
+{
+ struct zynqmp_dp *dp = connector_to_dp(connector);
+ struct zynqmp_dp_link_config *link_config = &dp->link_config;
+ u32 state, i;
+ int ret;
+
+ /*
+ * This is from heuristic. It takes some delay (ex, 100 ~ 500 msec) to
+ * get the HPD signal with some monitors.
+ */
+ for (i = 0; i < 10; i++) {
+ state = zynqmp_dp_read(dp->iomem,
+ ZYNQMP_DP_TX_INTR_SIGNAL_STATE);
+ if (state & ZYNQMP_DP_TX_INTR_SIGNAL_STATE_HPD)
+ break;
+ msleep(100);
+ }
+
+ if (state & ZYNQMP_DP_TX_INTR_SIGNAL_STATE_HPD) {
+ ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd,
+ sizeof(dp->dpcd));
+ if (ret < 0) {
+ dev_dbg(dp->dev, "DPCD read failes");
+ goto disconnected;
+ }
+
+ link_config->max_rate = min_t(int,
+ drm_dp_max_link_rate(dp->dpcd),
+ DP_HIGH_BIT_RATE2);
+ link_config->max_lanes = min_t(u8,
+ drm_dp_max_lane_count(dp->dpcd),
+ dp->num_lanes);
+
+ dp->status = connector_status_connected;
+ return connector_status_connected;
+ }
+
+disconnected:
+ dp->status = connector_status_disconnected;
+ return connector_status_disconnected;
+}
+
+static int zynqmp_dp_connector_get_modes(struct drm_connector *connector)
+{
+ struct zynqmp_dp *dp = connector_to_dp(connector);
+ struct edid *edid;
+ int ret;
+
+ edid = drm_get_edid(connector, &dp->aux.ddc);
+ if (!edid)
+ return 0;
+
+ drm_mode_connector_update_edid_property(connector, edid);
+ ret = drm_add_edid_modes(connector, edid);
+ kfree(edid);
+
+ return ret;
+}
+
+static struct drm_encoder *
+zynqmp_dp_connector_best_encoder(struct drm_connector *connector)
+{
+ struct zynqmp_dp *dp = connector_to_dp(connector);
+
+ return &dp->encoder;
+}
+
+static int zynqmp_dp_connector_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ struct zynqmp_dp *dp = connector_to_dp(connector);
+ u8 max_lanes = dp->link_config.max_lanes;
+ u8 bpp = dp->config.bpp;
+ int max_rate = dp->link_config.max_rate;
+ int rate;
+
+ if (mode->clock > ZYNQMP_MAX_FREQ) {
+ dev_dbg(dp->dev, "filtered the mode, %s,for high pixel rate\n",
+ mode->name);
+ drm_mode_debug_printmodeline(mode);
+ return MODE_CLOCK_HIGH;
+ }
+
+ /* Check with link rate and lane count */
+ rate = zynqmp_dp_max_rate(max_rate, max_lanes, bpp);
+ if (mode->clock > rate) {
+ dev_dbg(dp->dev, "filtered the mode, %s,for high pixel rate\n",
+ mode->name);
+ drm_mode_debug_printmodeline(mode);
+ return MODE_CLOCK_HIGH;
+ }
+
+ return MODE_OK;
+}
+
+static void zynqmp_dp_connector_destroy(struct drm_connector *connector)
+{
+ drm_connector_unregister(connector);
+ drm_connector_cleanup(connector);
+}
+
+static const struct drm_connector_funcs zynqmp_dp_connector_funcs = {
+ .detect = zynqmp_dp_connector_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = zynqmp_dp_connector_destroy,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .reset = drm_atomic_helper_connector_reset,
+};
+
+static struct drm_connector_helper_funcs zynqmp_dp_connector_helper_funcs = {
+ .get_modes = zynqmp_dp_connector_get_modes,
+ .best_encoder = zynqmp_dp_connector_best_encoder,
+ .mode_valid = zynqmp_dp_connector_mode_valid,
+};
+
+/*
+ * DRM encoder functions
+ */
+
+static void zynqmp_dp_encoder_enable(struct drm_encoder *encoder)
+{
+ struct zynqmp_dp *dp = encoder_to_dp(encoder);
+ void __iomem *iomem = dp->iomem;
+ unsigned int i;
+ int ret = 0;
+
+ pm_runtime_get_sync(dp->dev);
+ dp->enabled = true;
+ zynqmp_dp_init_aux(dp);
+ zynqmp_dp_update_misc(dp);
+ if (zynqmp_disp_aud_enabled(dp->dpsub->disp))
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_AUDIO_CONTROL, 1);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_PHY_POWER_DOWN, 0);
+ if (dp->status == connector_status_connected) {
+ for (i = 0; i < 3; i++) {
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER,
+ DP_SET_POWER_D0);
+ if (ret == 1)
+ break;
+ usleep_range(300, 500);
+ }
+ /* Some monitors take time to wake up properly */
+ msleep(zynqmp_dp_power_on_delay_ms);
+ }
+ if (ret != 1)
+ dev_dbg(dp->dev, "DP aux failed\n");
+ else
+ zynqmp_dp_train_loop(dp);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_SW_RESET,
+ ZYNQMP_DP_TX_SW_RESET_ALL);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_ENABLE_MAIN_STREAM, 1);
+}
+
+static void zynqmp_dp_encoder_disable(struct drm_encoder *encoder)
+{
+ struct zynqmp_dp *dp = encoder_to_dp(encoder);
+ void __iomem *iomem = dp->iomem;
+
+ dp->enabled = false;
+ cancel_delayed_work(&dp->hpd_work);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_ENABLE_MAIN_STREAM, 0);
+ drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_PHY_POWER_DOWN,
+ ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
+ if (zynqmp_disp_aud_enabled(dp->dpsub->disp))
+ zynqmp_dp_write(iomem, ZYNQMP_DP_TX_AUDIO_CONTROL, 0);
+ pm_runtime_put_sync(dp->dev);
+}
+
+static void
+zynqmp_dp_encoder_atomic_mode_set(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *connector_state)
+{
+ struct zynqmp_dp *dp = encoder_to_dp(encoder);
+ struct drm_display_mode *mode = &crtc_state->mode;
+ struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
+ u8 max_lanes = dp->link_config.max_lanes;
+ u8 bpp = dp->config.bpp;
+ int rate, max_rate = dp->link_config.max_rate;
+ int ret;
+
+ /* Check again as bpp or format might have been chagned */
+ rate = zynqmp_dp_max_rate(max_rate, max_lanes, bpp);
+ if (mode->clock > rate) {
+ dev_err(dp->dev, "the mode, %s,has too high pixel rate\n",
+ mode->name);
+ drm_mode_debug_printmodeline(mode);
+ }
+
+ ret = zynqmp_dp_mode_configure(dp, adjusted_mode->clock, 0);
+ if (ret < 0)
+ return;
+
+ zynqmp_dp_encoder_mode_set_transfer_unit(dp, adjusted_mode);
+}
+
+#define ZYNQMP_DP_MIN_H_BACKPORCH 20
+
+static int
+zynqmp_dp_encoder_atomic_check(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct drm_display_mode *mode = &crtc_state->mode;
+ struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
+ int diff = mode->htotal - mode->hsync_end;
+
+ /*
+ * ZynqMP DP requires horizontal backporch to be greater than 12.
+ * This limitation may not be compatible with the sink device.
+ */
+ if (diff < ZYNQMP_DP_MIN_H_BACKPORCH) {
+ int vrefresh = (adjusted_mode->clock * 1000) /
+ (adjusted_mode->vtotal * adjusted_mode->htotal);
+
+ dev_dbg(encoder->dev->dev, "hbackporch adjusted: %d to %d",
+ diff, ZYNQMP_DP_MIN_H_BACKPORCH - diff);
+ diff = ZYNQMP_DP_MIN_H_BACKPORCH - diff;
+ adjusted_mode->htotal += diff;
+ adjusted_mode->clock = adjusted_mode->vtotal *
+ adjusted_mode->htotal * vrefresh / 1000;
+ }
+
+ return 0;
+}
+
+static const struct drm_encoder_funcs zynqmp_dp_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static const struct drm_encoder_helper_funcs zynqmp_dp_encoder_helper_funcs = {
+ .enable = zynqmp_dp_encoder_enable,
+ .disable = zynqmp_dp_encoder_disable,
+ .atomic_mode_set = zynqmp_dp_encoder_atomic_mode_set,
+ .atomic_check = zynqmp_dp_encoder_atomic_check,
+};
+
+/*
+ * Component functions
+ */
+
+static void zynqmp_dp_hpd_work_func(struct work_struct *work)
+{
+ struct zynqmp_dp *dp;
+
+ dp = container_of(work, struct zynqmp_dp, hpd_work.work);
+
+ if (dp->drm)
+ drm_helper_hpd_irq_event(dp->drm);
+}
+
+int zynqmp_dp_bind(struct device *dev, struct device *master, void *data)
+{
+ struct zynqmp_dpsub *dpsub = dev_get_drvdata(dev);
+ struct zynqmp_dp *dp = dpsub->dp;
+ struct drm_encoder *encoder = &dp->encoder;
+ struct drm_connector *connector = &dp->connector;
+ struct drm_device *drm = data;
+ struct device_node *port;
+ int ret;
+
+ encoder->possible_crtcs |= zynqmp_disp_get_crtc_mask(dpsub->disp);
+ for_each_child_of_node(dev->of_node, port) {
+ if (!port->name || of_node_cmp(port->name, "port"))
+ continue;
+ encoder->possible_crtcs |= drm_of_find_possible_crtcs(drm,
+ port);
+ }
+ drm_encoder_init(drm, encoder, &zynqmp_dp_encoder_funcs,
+ DRM_MODE_ENCODER_TMDS, NULL);
+ drm_encoder_helper_add(encoder, &zynqmp_dp_encoder_helper_funcs);
+
+ connector->polled = DRM_CONNECTOR_POLL_HPD;
+ ret = drm_connector_init(encoder->dev, connector,
+ &zynqmp_dp_connector_funcs,
+ DRM_MODE_CONNECTOR_DisplayPort);
+ if (ret) {
+ dev_err(dp->dev, "failed to initialize the drm connector");
+ goto error_encoder;
+ }
+
+ drm_connector_helper_add(connector, &zynqmp_dp_connector_helper_funcs);
+ drm_connector_register(connector);
+ drm_mode_connector_attach_encoder(connector, encoder);
+ connector->dpms = DRM_MODE_DPMS_OFF;
+
+ dp->drm = drm;
+ dp->config.misc0 &= ~ZYNQMP_DP_TX_MAIN_STREAM_MISC0_SYNC;
+ ret = zynqmp_dp_set_bpc(dp, 8);
+ zynqmp_dp_update_bpp(dp);
+
+ /* This enables interrupts, so should be called after DRM init */
+ ret = zynqmp_dp_init_aux(dp);
+ if (ret) {
+ dev_err(dp->dev, "failed to initialize DP aux");
+ goto error_connector;
+ }
+ INIT_DELAYED_WORK(&dp->hpd_work, zynqmp_dp_hpd_work_func);
+
+ return 0;
+
+error_connector:
+ zynqmp_dp_connector_destroy(&dp->connector);
+error_encoder:
+ drm_encoder_cleanup(&dp->encoder);
+ return ret;
+}
+
+void zynqmp_dp_unbind(struct device *dev, struct device *master, void *data)
+{
+ struct zynqmp_dpsub *dpsub = dev_get_drvdata(dev);
+ struct zynqmp_dp *dp = dpsub->dp;
+
+ cancel_delayed_work_sync(&dp->hpd_work);
+ disable_irq(dp->irq);
+ zynqmp_dp_exit_aux(dp);
+ zynqmp_dp_connector_destroy(&dp->connector);
+ drm_encoder_cleanup(&dp->encoder);
+}
+
+/*
+ * Platform functions
+ */
+
+static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data)
+{
+ struct zynqmp_dp *dp = (struct zynqmp_dp *)data;
+ u32 status, mask;
+
+ status = zynqmp_dp_read(dp->iomem, ZYNQMP_DP_SUB_TX_INTR_STATUS);
+ mask = zynqmp_dp_read(dp->iomem, ZYNQMP_DP_SUB_TX_INTR_MASK);
+ if (!(status & ~mask))
+ return IRQ_NONE;
+
+ /* dbg for diagnostic, but not much that the driver can do */
+ if (status & ZYNQMP_DP_TX_INTR_CHBUF_UNDERFLW_MASK)
+ dev_dbg_ratelimited(dp->dev, "underflow interrupt\n");
+ if (status & ZYNQMP_DP_TX_INTR_CHBUF_OVERFLW_MASK)
+ dev_dbg_ratelimited(dp->dev, "overflow interrupt\n");
+
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_SUB_TX_INTR_STATUS, status);
+
+ /* The DP vblank will not be enabled with remote crtc device */
+ if (status & ZYNQMP_DP_TX_INTR_VBLANK_START)
+ zynqmp_disp_handle_vblank(dp->dpsub->disp);
+
+ if (status & ZYNQMP_DP_TX_INTR_HPD_EVENT)
+ schedule_delayed_work(&dp->hpd_work, 0);
+
+ if (status & ZYNQMP_DP_TX_INTR_HPD_IRQ) {
+ int ret;
+ u8 status[DP_LINK_STATUS_SIZE + 2];
+
+ ret = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status,
+ DP_LINK_STATUS_SIZE + 2);
+ if (ret < 0)
+ goto handled;
+
+ if (status[4] & DP_LINK_STATUS_UPDATED ||
+ !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) ||
+ !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) {
+ zynqmp_dp_train_loop(dp);
+ }
+ }
+
+handled:
+ return IRQ_HANDLED;
+}
+
+int zynqmp_dp_probe(struct platform_device *pdev)
+{
+ struct zynqmp_dpsub *dpsub;
+ struct zynqmp_dp *dp;
+ struct resource *res;
+ unsigned int i;
+ int irq, ret;
+
+ dp = devm_kzalloc(&pdev->dev, sizeof(*dp), GFP_KERNEL);
+ if (!dp)
+ return -ENOMEM;
+
+ dp->dpms = DRM_MODE_DPMS_OFF;
+ dp->status = connector_status_disconnected;
+ dp->dev = &pdev->dev;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dp");
+ dp->iomem = devm_ioremap_resource(dp->dev, res);
+ if (IS_ERR(dp->iomem))
+ return PTR_ERR(dp->iomem);
+
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_PHY_POWER_DOWN,
+ ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
+ zynqmp_dp_set(dp->iomem, ZYNQMP_DP_TX_PHY_CONFIG,
+ ZYNQMP_DP_TX_PHY_CONFIG_ALL_RESET);
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_FORCE_SCRAMBLER_RESET, 1);
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_ENABLE, 0);
+
+ dp->num_lanes = 2;
+ for (i = 0; i < ZYNQMP_DP_MAX_LANES; i++) {
+ char phy_name[16];
+
+ snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i);
+ dp->phy[i] = devm_phy_get(dp->dev, phy_name);
+ if (IS_ERR(dp->phy[i])) {
+ /* 2nd lane is optional */
+ if (i == 0 || PTR_ERR(dp->phy[i]) != -ENODEV) {
+ dev_err(dp->dev, "failed to get phy lane\n");
+ ret = PTR_ERR(dp->phy[i]);
+ dp->phy[i] = NULL;
+ return ret;
+ }
+ dp->phy[i] = NULL;
+ dp->num_lanes = 1;
+ }
+ }
+
+ ret = zynqmp_dp_init_phy(dp);
+ if (ret)
+ goto error_phy;
+
+ dp->aux.name = "ZynqMP DP AUX";
+ dp->aux.dev = dp->dev;
+ dp->aux.transfer = zynqmp_dp_aux_transfer;
+ ret = drm_dp_aux_register(&dp->aux);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to initialize DP aux\n");
+ goto error;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ ret = irq;
+ goto error;
+ }
+
+ ret = devm_request_threaded_irq(dp->dev, irq, NULL,
+ zynqmp_dp_irq_handler, IRQF_ONESHOT,
+ dev_name(dp->dev), dp);
+ if (ret < 0)
+ goto error;
+ dp->irq = irq;
+
+ dpsub = platform_get_drvdata(pdev);
+ dpsub->dp = dp;
+ dp->dpsub = dpsub;
+
+ return 0;
+
+error:
+ drm_dp_aux_unregister(&dp->aux);
+error_phy:
+ zynqmp_dp_exit_phy(dp);
+ return ret;
+}
+
+int zynqmp_dp_remove(struct platform_device *pdev)
+{
+ struct zynqmp_dpsub *dpsub = platform_get_drvdata(pdev);
+ struct zynqmp_dp *dp = dpsub->dp;
+
+ zynqmp_dp_write(dp->iomem, ZYNQMP_DP_TX_ENABLE, 0);
+ drm_dp_aux_unregister(&dp->aux);
+ zynqmp_dp_exit_phy(dp);
+ dpsub->dp = NULL;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.h b/drivers/gpu/drm/xlnx/zynqmp_dp.h
new file mode 100644
index 0000000..2d7cb8a
--- /dev/null
+++ b/drivers/gpu/drm/xlnx/zynqmp_dp.h
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP DisplayPort Driver
+ *
+ * Copyright (C) 2017 - 2018 Xilinx, Inc.
+ *
+ * Author: Hyun Woo Kwon <hyun.kwon-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ZYNQMP_DP_H_
+#define _ZYNQMP_DP_H_
+
+struct zynqmp_dp;
+struct drm_display_mode;
+
+const int zynqmp_dp_set_color(struct zynqmp_dp *dp, const char *color);
+void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp);
+void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp);
+void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp,
+ struct drm_display_mode *mode);
+
+int zynqmp_dp_bind(struct device *dev, struct device *master, void *data);
+void zynqmp_dp_unbind(struct device *dev, struct device *master, void *data);
+
+int zynqmp_dp_probe(struct platform_device *pdev);
+int zynqmp_dp_remove(struct platform_device *pdev);
+
+#endif /* _ZYNQMP_DP_H_ */
--
2.7.4
--
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