From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bjorn Andersson Subject: [PATCH v7 3/4] arm64: dts: qcom: Add AOSS QMP node Date: Tue, 30 Apr 2019 21:37:33 -0700 Message-ID: <20190501043734.26706-4-bjorn.andersson@linaro.org> References: <20190501043734.26706-1-bjorn.andersson@linaro.org> Return-path: In-Reply-To: <20190501043734.26706-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org The AOSS QMP provides a number of power domains, used for QDSS and PIL, add the node for this. Tested-by: Sibi Sankar Reviewed-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- Changes since v6: - Added #clock-cells arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index fcb93300ca62..666bc88d3e81 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -2142,6 +2143,15 @@ #reset-cells = <1>; }; + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, -- 2.18.0