From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
Cc: "Z.q. Hou" <zhiqiang.hou@nxp.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
Leo Li <leoyang.li@nxp.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"will.deacon@arm.com" <will.deacon@arm.com>,
Mingkai Hu <mingkai.hu@nxp.com>,
"M.h. Lian" <minghuan.lian@nxp.com>,
Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: Re: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors
Date: Fri, 14 Jun 2019 11:43:59 +0100 [thread overview]
Message-ID: <20190614104351.GA29955@e121166-lin.cambridge.arm.com> (raw)
In-Reply-To: <CAKnKUHFMH6=ox=qdaUR1kNEhETDCVyu3jQZEj+taEbbMRBRuYA@mail.gmail.com>
On Fri, Jun 14, 2019 at 12:38:51PM +0530, Karthikeyan Mitran wrote:
> Hi Lorenzo and Hou Zhiqiang
> PAB_INTP_AMBA_MISC_STAT does have other status in the higher bits, it
> should have been masked before checking for the status
You are the maintainer for this driver, so if there is something to be
changed you must post a patch to that extent, I do not understand what
the above means, write the code to fix it, I won't do it.
I am getting a bit annoyed with this Mobiveil driver so either you guys
sort this out or I will have to remove it from the kernel.
> Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
Ok I assume this means you tested it but according to what you
say above, are there still issues with this code path ? Should
we update the patch ?
Moreover:
https://kernelnewbies.org/PatchCulture
Please read it and never top-post.
Thanks,
Lorenzo
> On Wed, Jun 12, 2019 at 8:38 PM Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
> >
> > On Fri, Apr 12, 2019 at 08:36:12AM +0000, Z.q. Hou wrote:
> > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > >
> > > In the loop block, there is not code to update the loop key,
> > > this patch updates the loop key by re-read the INTx status
> > > register.
> > >
> > > This patch also add the clearing of the handled INTx status.
> > >
> > > Note: Need MV to test this fix.
> >
> > This means INTX were never tested and current code handling them is,
> > AFAICS, an infinite loop which is very very bad.
> >
> > This is a gross bug and must be fixed as soon as possible.
> >
> > I want Karthikeyan ACK and Tested-by on this patch.
> >
> > Lorenzo
> >
> > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > > ---
> > > V5:
> > > - Corrected and retouched the subject and changelog.
> > >
> > > drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++----
> > > 1 file changed, 9 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> > > index 4ba458474e42..78e575e71f4d 100644
> > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> > > /* Handle INTx */
> > > if (intr_status & PAB_INTP_INTX_MASK) {
> > > shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> > > + shifted_status &= PAB_INTP_INTX_MASK;
> > > shifted_status >>= PAB_INTX_START;
> > > do {
> > > for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
> > > @@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> > > dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
> > > bit);
> > >
> > > - /* clear interrupt */
> > > - csr_writel(pcie,
> > > - shifted_status << PAB_INTX_START,
> > > + /* clear interrupt handled */
> > > + csr_writel(pcie, 1 << (PAB_INTX_START + bit),
> > > PAB_INTP_AMBA_MISC_STAT);
> > > }
> > > - } while ((shifted_status >> PAB_INTX_START) != 0);
> > > +
> > > + shifted_status = csr_readl(pcie,
> > > + PAB_INTP_AMBA_MISC_STAT);
> > > + shifted_status &= PAB_INTP_INTX_MASK;
> > > + shifted_status >>= PAB_INTX_START;
> > > + } while (shifted_status != 0);
> > > }
> > >
> > > /* read extra MSI status register */
> > > --
> > > 2.17.1
> > >
>
>
>
> --
> Thanks,
> Regards,
> Karthikeyan Mitran
>
> --
> Mobiveil INC., CONFIDENTIALITY NOTICE: This e-mail message, including any
> attachments, is for the sole use of the intended recipient(s) and may
> contain proprietary confidential or privileged information or otherwise be
> protected by law. Any unauthorized review, use, disclosure or distribution
> is prohibited. If you are not the intended recipient, please notify the
> sender and destroy all copies and the original message.
next prev parent reply other threads:[~2019-06-14 10:43 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-12 8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 01/20] PCI: mobiveil: Unify register accessors Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change Z.q. Hou
2019-07-03 15:10 ` Lorenzo Pieralisi
2019-07-04 2:41 ` Z.q. Hou
2019-07-03 15:19 ` Lorenzo Pieralisi
2019-07-03 15:24 ` Lorenzo Pieralisi
2019-07-04 3:00 ` Z.q. Hou
2019-07-04 10:56 ` Lorenzo Pieralisi
2019-07-05 2:24 ` Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 03/20] PCI: mobiveil: Correct the returned error number Z.q. Hou
2019-07-03 14:17 ` Lorenzo Pieralisi
2019-07-04 2:38 ` Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
2019-06-11 16:59 ` Lorenzo Pieralisi
2019-06-11 17:29 ` Marc Zyngier
2019-06-12 10:54 ` Lorenzo Pieralisi
2019-06-12 11:22 ` Marc Zyngier
2019-06-12 11:34 ` Z.q. Hou
2019-06-12 13:08 ` Lorenzo Pieralisi
2019-06-15 1:30 ` Z.q. Hou
2019-06-17 9:33 ` Lorenzo Pieralisi
2019-06-17 10:34 ` Z.q. Hou
2019-06-28 11:35 ` Lorenzo Pieralisi
2019-07-01 10:07 ` Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 05/20] PCI: mobiveil: Correct PCI base address in MEM/IO outbound windows Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 06/20] PCI: mobiveil: Replace the resource list iteration function Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 07/20] PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
2019-06-12 15:13 ` Lorenzo Pieralisi
2019-04-12 8:36 ` [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions Z.q. Hou
2019-06-28 16:02 ` Lorenzo Pieralisi
2019-07-01 10:18 ` Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 09/20] PCI: mobiveil: Correct inbound/outbound window setup routines Z.q. Hou
2019-06-28 16:41 ` Lorenzo Pieralisi
2019-07-01 10:24 ` Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors Z.q. Hou
2019-06-12 15:08 ` Lorenzo Pieralisi
2019-06-14 7:08 ` Karthikeyan Mitran
2019-06-14 10:43 ` Lorenzo Pieralisi [this message]
2019-06-19 5:28 ` Karthikeyan Mitran
2019-06-19 7:24 ` Z.q. Hou
2019-06-28 17:05 ` Lorenzo Pieralisi
2019-07-01 10:27 ` Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 11/20] PCI: mobiveil: Correct the fixup of Class Code field Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 12/20] PCI: mobiveil: Move the link up waiting out of mobiveil_host_init() Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 13/20] PCI: mobiveil: Move IRQ chained handler setup out of DT parse Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 14/20] PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 15/20] PCI: mobiveil: Fix the checking of valid device Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 16/20] PCI: mobiveil: Add link up condition check Z.q. Hou
2019-06-11 17:17 ` Lorenzo Pieralisi
2019-06-12 11:36 ` Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 17/20] PCI: mobiveil: Complete initialization of host even if no PCIe link Z.q. Hou
2019-06-12 14:34 ` Lorenzo Pieralisi
2019-06-15 2:34 ` Z.q. Hou
2019-04-12 8:37 ` [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader Z.q. Hou
2019-06-12 16:23 ` Lorenzo Pieralisi
2019-06-15 5:03 ` Z.q. Hou
2019-06-17 9:30 ` Lorenzo Pieralisi
2019-06-17 10:42 ` Z.q. Hou
2019-04-12 8:37 ` [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors Z.q. Hou
2019-06-12 13:54 ` Lorenzo Pieralisi
2019-06-15 1:13 ` Z.q. Hou
2019-06-17 9:29 ` Lorenzo Pieralisi
2019-06-17 10:16 ` Z.q. Hou
2019-04-12 8:37 ` [PATCHv5 20/20] dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional Z.q. Hou
2019-07-03 10:33 ` [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Lorenzo Pieralisi
2019-07-04 2:36 ` Z.q. Hou
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190614104351.GA29955@e121166-lin.cambridge.arm.com \
--to=lorenzo.pieralisi@arm.com \
--cc=bhelgaas@google.com \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=l.subrahmanya@mobiveil.co.in \
--cc=leoyang.li@nxp.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=m.karthikeyan@mobiveil.co.in \
--cc=mark.rutland@arm.com \
--cc=minghuan.lian@nxp.com \
--cc=mingkai.hu@nxp.com \
--cc=robh+dt@kernel.org \
--cc=shawnguo@kernel.org \
--cc=will.deacon@arm.com \
--cc=xiaowei.bao@nxp.com \
--cc=zhiqiang.hou@nxp.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).