From: Jitao Shi <jitao.shi@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
linux-pwm@vger.kernel.org, David Airlie <airlied@linux.ie>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: Jitao Shi <jitao.shi@mediatek.com>,
Thierry Reding <treding@nvidia.com>,
Ajay Kumar <ajaykumar.rs@samsung.com>,
Inki Dae <inki.dae@samsung.com>,
Rahul Sharma <rahul.sharma@samsung.com>,
Sean Paul <seanpaul@chromium.org>,
Vincent Palatin <vpalatin@chromium.org>,
Andy Yan <andy.yan@rock-chips.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Russell King <rmk+kernel@arm.linux.org.uk>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com,
Sascha Hauer <kernel@pengutronix.de>,
yingjoe.chen@mediatek.com, eddie.huang@mediatek.com,
cawa.cheng@mediatek.com, bibby.hsieh@mediatek.com, ck.hu
Subject: [v5 4/7] drm/mediatek: add frame size control
Date: Thu, 27 Jun 2019 16:01:12 +0800 [thread overview]
Message-ID: <20190627080116.40264-5-jitao.shi@mediatek.com> (raw)
In-Reply-To: <20190627080116.40264-1-jitao.shi@mediatek.com>
Our new DSI chip has frame size control.
So add the driver data to control for different chips.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 6b6550926db6..45e331055842 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -78,6 +78,7 @@
#define DSI_VBP_NL 0x24
#define DSI_VFP_NL 0x28
#define DSI_VACT_NL 0x2C
+#define DSI_SIZE_CON 0x38
#define DSI_HSA_WC 0x50
#define DSI_HBP_WC 0x54
#define DSI_HFP_WC 0x58
@@ -162,6 +163,7 @@ struct phy;
struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
bool has_shadow_ctl;
+ bool has_size_ctl;
};
struct mtk_dsi {
@@ -430,6 +432,10 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
+ if (dsi->driver_data->has_size_ctl)
+ writel(vm->vactive << 16 | vm->hactive,
+ dsi->regs + DSI_SIZE_CON);
+
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
--
2.21.0
next prev parent reply other threads:[~2019-06-27 8:01 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-27 8:01 [v5 0/7] Support dsi for mt8183 Jitao Shi
2019-06-27 8:01 ` [v5 1/7] drm/mediatek: move mipi_dsi_host_register to probe Jitao Shi
2019-06-28 6:10 ` CK Hu
2019-07-17 21:48 ` Ryan Case
2019-06-27 8:01 ` [v5 2/7] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701 Jitao Shi
2019-06-28 5:57 ` CK Hu
2019-06-27 8:01 ` [v5 3/7] drm/mediatek: add dsi reg commit disable control Jitao Shi
2019-06-27 8:01 ` Jitao Shi [this message]
2019-07-01 1:29 ` [v5 4/7] drm/mediatek: add frame size control CK Hu
2019-06-27 8:01 ` [v5 5/7] drm/mediatek: add mt8183 dsi driver support Jitao Shi
2019-06-27 8:01 ` [v5 6/7] drm/mediatek: change the dsi phytiming calculate method Jitao Shi
2019-07-01 1:43 ` CK Hu
2019-07-17 22:03 ` Ryan Case
2019-06-27 8:01 ` [v5 7/7] drm: mediatek: adjust dsi and mipi_tx probe sequence Jitao Shi
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