From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lorenzo Pieralisi Subject: Re: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors Date: Fri, 28 Jun 2019 18:05:52 +0100 Message-ID: <20190628170552.GD21829@e121166-lin.cambridge.arm.com> References: <20190412083635.33626-1-Zhiqiang.Hou@nxp.com> <20190412083635.33626-11-Zhiqiang.Hou@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20190412083635.33626-11-Zhiqiang.Hou@nxp.com> Sender: linux-kernel-owner@vger.kernel.org To: "Z.q. Hou" Cc: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "catalin.marinas@arm.com" , "will.deacon@arm.com" , Mingkai Hu , "M.h. Lian" , Xiaowei Bao List-Id: devicetree@vger.kernel.org On Fri, Apr 12, 2019 at 08:36:12AM +0000, Z.q. Hou wrote: > From: Hou Zhiqiang > > In the loop block, there is not code to update the loop key, > this patch updates the loop key by re-read the INTx status > register. > > This patch also add the clearing of the handled INTx status. This is two bugs and that requires two patches, each of them fixing a specific issue. So split the patch into two and repost it. Lorenzo > Note: Need MV to test this fix. > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > Reviewed-by: Subrahmanya Lingappa > --- > V5: > - Corrected and retouched the subject and changelog. > > drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c > index 4ba458474e42..78e575e71f4d 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) > /* Handle INTx */ > if (intr_status & PAB_INTP_INTX_MASK) { > shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); > + shifted_status &= PAB_INTP_INTX_MASK; > shifted_status >>= PAB_INTX_START; > do { > for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) { > @@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) > dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", > bit); > > - /* clear interrupt */ > - csr_writel(pcie, > - shifted_status << PAB_INTX_START, > + /* clear interrupt handled */ > + csr_writel(pcie, 1 << (PAB_INTX_START + bit), > PAB_INTP_AMBA_MISC_STAT); > } > - } while ((shifted_status >> PAB_INTX_START) != 0); > + > + shifted_status = csr_readl(pcie, > + PAB_INTP_AMBA_MISC_STAT); > + shifted_status &= PAB_INTP_INTX_MASK; > + shifted_status >>= PAB_INTX_START; > + } while (shifted_status != 0); > } > > /* read extra MSI status register */ > -- > 2.17.1 >