From mboxrd@z Thu Jan 1 00:00:00 1970 From: Helen Koike Subject: [PATCH v8 12/14] arm64: dts: rockchip: add isp0 node for rk3399 Date: Tue, 30 Jul 2019 15:42:54 -0300 Message-ID: <20190730184256.30338-13-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-rockchip@lists.infradead.org Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, mchehab@kernel.org, heiko@sntech.de, jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, kernel@collabora.com, ezequiel@collabora.com, linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, zhengsq@rock-chips.com, Helen Koike List-Id: devicetree@vger.kernel.org From: Shunqian Zheng rk3399 have two ISP, but we havn't test isp1, so just add isp0 at present. Signed-off-by: Shunqian Zheng Signed-off-by: Jacob Chen [update for upstream] Signed-off-by: Helen Koike --- Changes in v8: None Changes in v7: - add phy properties - add ports arch/arm64/boot/dts/rockchip/rk3399.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index cede1ad81be2..776d2bd48c06 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1698,6 +1698,31 @@ status = "disabled"; }; + isp0: isp0@ff910000 { + compatible = "rockchip,rk3399-cif-isp"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_ISP0>, + <&cru ACLK_ISP0>, <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0>, <&cru HCLK_ISP0_WRAPPER>; + clock-names = "clk_isp", + "aclk_isp", "aclk_isp_wrap", + "hclk_isp", "hclk_isp_wrap"; + power-domains = <&power RK3399_PD_ISP0>; + iommus = <&isp0_mmu>; + phys = <&mipi_dphy_rx0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + }; + }; + isp0_mmu: iommu@ff914000 { compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; -- 2.22.0