From mboxrd@z Thu Jan 1 00:00:00 1970 From: Atish Patra Subject: [PATCH v2 5/5] dt-bindings: Update the isa string description Date: Tue, 30 Jul 2019 18:24:18 -0700 Message-ID: <20190731012418.24565-6-atish.patra@wdc.com> References: <20190731012418.24565-1-atish.patra@wdc.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20190731012418.24565-1-atish.patra@wdc.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Alexios Zavras , Allison Randal , Anup Patel , Daniel Lezcano , devicetree@vger.kernel.org, Enrico Weigelt , Greg Kroah-Hartman , Johan Hovold , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Rob Herring , Thomas Gleixner List-Id: devicetree@vger.kernel.org The yaml documentation description of isa strings section doesn't specify anything about the case sensitiveness of the isa strings. The RISC-V specification clearly specifies it to be case insensitive. However, Linux kernel supports only lower case isa strings. Update the yaml documentation accordingly to avoid any confusion. Signed-off-by: Atish Patra --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c899111aa5e3..e22a2b7ebafa 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -46,10 +46,14 @@ properties: - rv64imafdc description: Identifies the specific RISC-V instruction set architecture - supported by the hart. These are documented in the RISC-V + supported by the hart. These are documented in the RISC-V User-Level ISA document, available from https://riscv.org/specifications/ + Linux kernel only supports lower case isa strings. Thus, + isa strings must be specified in lower case in device tree + as well. + timebase-frequency: type: integer minimum: 1 -- 2.21.0