From: Andy Shevchenko <andriy.shevchenko@intel.com>
To: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Cc: linus.walleij@linaro.org, robh+dt@kernel.org,
mark.rutland@arm.com, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
robh@kernel.org, qi-ming.wu@intel.com, yixin.zhu@linux.intel.com,
cheol.yong.kim@intel.com
Subject: Re: [PATCH v6 1/2] pinctrl: Add pinmux & GPIO controller driver for a new SoC
Date: Mon, 11 Nov 2019 13:18:08 +0200 [thread overview]
Message-ID: <20191111111808.GO32742@smile.fi.intel.com> (raw)
In-Reply-To: <d15b8cf13882902444e33c616d78c06c6b5fdc7b.1573455324.git.rahul.tanwar@linux.intel.com>
On Mon, Nov 11, 2019 at 06:11:29PM +0800, Rahul Tanwar wrote:
> Intel Lightning Mountain SoC has a pinmux controller & GPIO controller IP which
> controls pin multiplexing & configuration including GPIO functions selection &
> GPIO attributes configuration.
>
> This IP is not based on & does not have anything in common with Chassis
> specification. The pinctrl drivers under pinctrl/intel/* are all based upon
> Chassis spec compliant pinctrl IPs. So this driver doesn't fit & can not use
> pinctrl framework under pinctrl/intel/* and it requires a separate new driver.
>
> Add a new GPIO & pin control framework based driver for this IP.
Looking again into this DT parsing and at other drivers, can't you utilize pin
control framework better?
I see some drivers are using
pinctrl_utils_add_map_mux()
among other calls.
Some comments below as well.
> + writel(pmx, mem + (offset << 2));
offset * 4
looks more naturally here. Applies to other similar cases if any.
> + val = readl(mem + REG_DRCC(idx));
> + val = PARSE_DRV_CURRENT(val, pin_offset);
> +
> + return val;
Can be
return PARSE_DRV_CURRENT(readl(mem + REG_DRCC(idx)), pin_offset);
but it's up to you.
> +static int eqbr_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
> + unsigned long *configs, unsigned int num_configs)
> +{
> + struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
> + struct eqbr_gpio_ctrl *gctrl;
> + enum pin_config_param param;
> + struct eqbr_pin_bank *bank;
> + unsigned int val, offset;
> + struct gpio_chip *gc;
> + unsigned long flags;
> + void __iomem *mem;
> + u32 regval, mask;
> + int i;
> +
> + for (i = 0; i < num_configs; i++) {
> + param = pinconf_to_config_param(configs[i]);
> + val = pinconf_to_config_argument(configs[i]);
> +
> + bank = find_pinbank_via_pin(pctl, pin);
> + if (!bank) {
> + dev_err(pctl->dev,
> + "Couldn't find pin bank for pin %u\n", pin);
> + return -ENODEV;
> + }
> + mem = bank->membase;
> + offset = pin - bank->pin_base;
> +
> + switch (param) {
> + case PIN_CONFIG_BIAS_PULL_UP:
> + mem += REG_PUEN;
> + val &= 0x1;
Unneeded if use standard pattern (see below).
> + mask = BIT(offset);
> + break;
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + mem += REG_PDEN;
> + val &= 0x1;
Ditto.
> + mask = BIT(offset);
> + break;
> + case PIN_CONFIG_DRIVE_OPEN_DRAIN:
> + mem += REG_OD;
> + val &= 0x1;
Ditto.
> + mask = BIT(offset);
> + break;
> + case PIN_CONFIG_DRIVE_STRENGTH:
> + mem += REG_DRCC(offset / DRV_CUR_PINS);
> + offset = (offset % DRV_CUR_PINS) << 1;
> + val &= 0x3;
Ditto.
> + mask = GENMASK(offset + 1, offset);
GENMASK() badly works with non-constants. Better
mask = GENMASK(1, 0) << offset;
> + break;
> + case PIN_CONFIG_SLEW_RATE:
> + mem += REG_SRC;
> + val &= 0x1;
Ditto.
> + mask = BIT(offset);
> + break;
> + case PIN_CONFIG_OUTPUT_ENABLE:
> + gctrl = get_gpio_ctrls_via_bank(pctl, bank);
> + if (!gctrl) {
> + dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
> + bank->pin_base, pin);
> + return -ENODEV;
> + }
> + gc = &gctrl->chip;
> + gc->direction_output(gc, offset, 0);
> + continue;
> + default:
> + return -ENOTSUPP;
> + }
> +
> + raw_spin_lock_irqsave(&pctl->lock, flags);
> + regval = readl(mem);
> + regval = (regval & ~mask) | (val << offset);
Standard pattern is to apply mask here:
regval = (regval & ~mask) | ((val << offset) & mask);
> + writel(regval, mem);
> + raw_spin_unlock_irqrestore(&pctl->lock, flags);
> + }
> +
> + return 0;
> +}
> + dev_dbg(dev, "Group %s: not function binded!\n",
> + (char *)prop->value);
Do you need casting here?
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2019-11-11 11:18 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-11 10:11 [PATCH v6 0/2] pinctrl: Add new pinctrl/GPIO driver Rahul Tanwar
2019-11-11 10:11 ` [PATCH v6 1/2] pinctrl: Add pinmux & GPIO controller driver for a new SoC Rahul Tanwar
2019-11-11 11:18 ` Andy Shevchenko [this message]
2019-11-13 3:55 ` Tanwar, Rahul
2019-11-11 10:11 ` [PATCH v6 2/2] dt-bindings: pinctrl: intel: Add for " Rahul Tanwar
2019-11-12 19:14 ` Rob Herring
2019-11-13 6:05 ` Tanwar, Rahul
2019-11-13 14:46 ` Linus Walleij
2019-11-14 3:27 ` Tanwar, Rahul
2019-11-14 17:39 ` Rob Herring
2019-11-15 6:01 ` Tanwar, Rahul
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