From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D580AC33CA8 for ; Tue, 19 Nov 2019 23:19:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9DF412246B for ; Tue, 19 Nov 2019 23:19:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="whICS7lb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727519AbfKSXTc (ORCPT ); Tue, 19 Nov 2019 18:19:32 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:41688 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727495AbfKSXTb (ORCPT ); Tue, 19 Nov 2019 18:19:31 -0500 Received: by mail-wr1-f66.google.com with SMTP id b18so24498979wrj.8 for ; Tue, 19 Nov 2019 15:19:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CY9BzC4lO/psiiWDvfyoZ5PZxvDdzpF24ejbtK1oew8=; b=whICS7lbVl4iQygx4TtWkKmLoxTN22cvmLgeTEL6i0Wk5kEJR5srSsIvGyO8Vffh7f zWfGkuDM43I1mSSB4W7r9MEvitCrB6Lis5kGdwfTTvt586EjueWoTnMVLZ9g/gbiKnee rlXbwBXefr0T3UkywMVmoZaThvQoKy7h5IT5anGG4CgND6KuX5dGIhzM3WUIhqpJWvpH /8d5GAxJX7EHczVlCT3bBL0gRgpRS4wTL2c6jhFAT8IWTibax6CoVHUw0AtbumAKtxXj E6t2CUzztNbrgzVg0FK9XrXcHrP5ROYhgELsCROYzp/OzXJJkiCLuMwNR+ejiaNMG7Fg MGDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CY9BzC4lO/psiiWDvfyoZ5PZxvDdzpF24ejbtK1oew8=; b=mNxiZs2aI448n2AR84AyCwO/eq17r/r7+xk1AgZiaeBTXj9+mIJdpaiwiyPB9SypeP vnrjZkGYVPRIkiRNz+TbtPlR3QpsQmxW1ytG/bR19W+jmSGD+zfCbzjWy1FB4c2r1v0K gm7U2wGJhSNjsqJf/orDfFuaXBMYzLBrR13U6QPuqqMYBaPGqrFGISHz1I8vGczg0mXV gN3EO2xsuNuT/p1jgIfo1oNcaO0RTDkxdlwPKaPL2tFzoJeKNgmpKwaq9oWKhFbueWDG EtKwkIoMB5y5TRJluZc82dP1JzI5P6vlLAm/1VJRsB3UbQczWCbBID5fWg2rY38jSEOc gxjQ== X-Gm-Message-State: APjAAAU/DK5ZtvbmQmKDBxA9ZQt7GKq/yk3foz+5Igt+5/pW4WXmMIUB f5J4X/U8fz70E88xr+Hr1L5BhA== X-Google-Smtp-Source: APXvYqyNzLbvJ4OlsG32U7Lnk0xF5OdDAXiURRrNOmbEyBLWk7UCA6MQ2hD34Esh6BlQUv2sLWKTWg== X-Received: by 2002:adf:9d87:: with SMTP id p7mr39530588wre.11.1574205569880; Tue, 19 Nov 2019 15:19:29 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:a19d:4139:292b:19a0]) by smtp.gmail.com with ESMTPSA id m15sm15746717wrj.52.2019.11.19.15.19.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 15:19:29 -0800 (PST) From: Mike Leach To: mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com Subject: [PATCH v5 10/14] dt-bindings: qcom: Add CTI options for qcom msm8916 Date: Tue, 19 Nov 2019 23:19:08 +0000 Message-Id: <20191119231912.12768-11-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191119231912.12768-1-mike.leach@linaro.org> References: <20191119231912.12768-1-mike.leach@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adds system and CPU bound CTI definitions for Qualcom msm8916 platform (Dragonboard DB410C). System CTIs 2-11 are omitted as no information available at present. Signed-off-by: Mike Leach --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 85 +++++++++++++++++++++++++-- 1 file changed, 81 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 5ea9fb8f2f87..9589fc2cba22 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -1357,7 +1358,7 @@ cpu = <&CPU3>; }; - etm@85c000 { + etm0: etm@85c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85c000 0x1000>; @@ -1375,7 +1376,7 @@ }; }; - etm@85d000 { + etm1: etm@85d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85d000 0x1000>; @@ -1393,7 +1394,7 @@ }; }; - etm@85e000 { + etm2: etm@85e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85e000 0x1000>; @@ -1411,7 +1412,7 @@ }; }; - etm@85f000 { + etm3: etm@85f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85f000 0x1000>; @@ -1429,6 +1430,82 @@ }; }; + /* System CTIs */ + /* CTI 0 - TMC connections */ + cti@810000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTI 1 - TPIU connections */ + cti@811000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x811000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTIs 2-11 - no information - not instantiated */ + + /* Core CTIs; CTIs 12-15 */ + /* CTI - CPU-0 */ + cti@858000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + arm,cti-v8-arch; + cpu = <&CPU0>; + arm,cs-dev-assoc = <&etm0>; + + }; + + /* CTI - CPU-1 */ + cti@859000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + arm,cti-v8-arch; + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + }; + + /* CTI - CPU-2 */ + cti@85a000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x85a000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + arm,cti-v8-arch; + cpu = <&CPU2>; + arm,cs-dev-assoc = <&etm2>; + }; + + /* CTI - CPU-3 */ + cti@85b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x85b000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + arm,cti-v8-arch; + cpu = <&CPU3>; + arm,cs-dev-assoc = <&etm3>; + }; + + venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>; -- 2.17.1