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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id a10sm1354822otf.72.2019.11.21.12.43.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 12:43:51 -0800 (PST) Date: Thu, 21 Nov 2019 14:43:50 -0600 From: Rob Herring To: Shiping Ji Cc: bp@alien8.de, james.morse@arm.com, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mchehab@kernel.org, linux-edac@vger.kernel.org, sashal@kernel.org, hangl@microsoft.com, lewan@microsoft.com, ruizhao@microsoft.com, scott.branden@broadcom.com, yuqing.shen@broadcom.com, ray.jui@broadcom.com, shji@microsoft.com, wangglei@gmail.com Subject: Re: [PATCH v7 1/2] dt-bindings: edac: arm-dmc520.txt Message-ID: <20191121204350.GA26174@bogus> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sun, Nov 17, 2019 at 06:10:43PM -0800, Shiping Ji wrote: > This is the device tree bindings for new EDAC driver dmc520_edac.c. > > Signed-off-by: Lei Wang > Reviewed-by: James Morse > > --- > Changes in v7: > - Added arm prefix to the interrupt-config property > > --- > .../devicetree/bindings/edac/arm-dmc520.txt | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > create mode 100644 Documentation/devicetree/bindings/edac/arm-dmc520.txt > > diff --git a/Documentation/devicetree/bindings/edac/arm-dmc520.txt b/Documentation/devicetree/bindings/edac/arm-dmc520.txt > new file mode 100644 > index 000000000000..476cf8b76f2a > --- /dev/null > +++ b/Documentation/devicetree/bindings/edac/arm-dmc520.txt > @@ -0,0 +1,26 @@ > +* ARM DMC-520 EDAC node > + > +Required properties: > +- compatible : "brcm,dmc-520", "arm,dmc-520". > +- reg : Address range of the DMC-520 registers. > +- interrupts : DMC-520 interrupt numbers. The example below specifies > + two interrupt lines for dram_ecc_errc_int and > + dram_ecc_errd_int. > +- arm,interrupt-config : This is an array of interrupt masks. For each of the > + above interrupt line, add one interrupt mask element to > + it. That is, there is a 1:1 mapping from each interrupt > + line to an interrupt mask. An interrupt mask can represent > + multiple interrupts being enabled. Refer to interrupt_control > + register in DMC-520 TRM for interrupt mapping. In the example > + below, the interrupt configuration enables dram_ecc_errc_int > + and dram_ecc_errd_int. And each interrupt is connected to > + a separate interrupt line. Looking at this again, I think I now understand what you are trying to do. Your mask is just what interrupt line each one is. We have a standard way of doing this either by using indices of 'interrupts' or with interrupt-names. The latter probably works best in this case. You need to define *all* the interrupt-names: combined ram_ecc_errc ram_ecc_errd dram_ecc_errc dram_ecc_errd failed_access failed_prog link_err temperature_event arch_fsm phy_request I'm not sure if all the '*_oflow' interrupts should be listed too. It doesn't seem all that useful to get a 2nd interrupt. Your node should list all that are hooked up in the h/w, not just the ones you need for EDAC. Rob