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From: Ard Biesheuvel <ardb@kernel.org>
To: devicetree@vger.kernel.org
Cc: Ard Biesheuvel <ardb@kernel.org>,
	Brijesh Singh <brijeshkumar.singh@amd.com>,
	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
	Tom Lendacky <thomas.lendacky@amd.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>
Subject: [PATCH v2 6/8] dt: amd-seattle: add description of the SATA/CCP SMMUs
Date: Tue, 26 Nov 2019 12:43:17 +0100	[thread overview]
Message-ID: <20191126114319.2755-7-ardb@kernel.org> (raw)
In-Reply-To: <20191126114319.2755-1-ardb@kernel.org>

Add descriptions of the SMMUs that cover the SATA controller(s)
on the AMD Seattle SOC. The CCP crypto accelerator shares its
SMMU with the second SATA controller, which is only enabled on
B1 silicon.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
 arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts |  4 ++++
 arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts |  5 +++++
 arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi     | 22 ++++++++++++++++++++
 3 files changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
index 8e341be9a399..be8db5758c94 100644
--- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
+++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
@@ -60,6 +60,10 @@
 	status = "ok";
 };
 
+&sata0 {
+	iommus = <&sata0_smmu 0x0a>, <&sata0_smmu 0x0b>, <&sata0_smmu 0x1a>;
+};
+
 &spi0 {
 	status = "ok";
 };
diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
index 92cef05c6b74..1661544eb0af 100644
--- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
+++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
@@ -60,7 +60,12 @@
 	status = "ok";
 };
 
+&sata0 {
+	iommus = <&sata0_smmu 0x0e>, <&sata0_smmu 0x0f>, <&sata0_smmu 0x1e>;
+};
+
 &sata1 {
+	iommus = <&sata1_smmu 0x0e>, <&sata1_smmu 0x0f>, <&sata1_smmu 0x1e>;
 	status = "ok";
 };
 
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
index 7484ea695262..eac241c98ff0 100644
--- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
+++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
@@ -83,6 +83,24 @@
 			dma-coherent;
 		};
 
+		sata0_smmu: smmu@e0200000 {
+			compatible = "arm,mmu-401";
+			reg = <0 0xe0200000 0 0x10000>;
+			#global-interrupts = <1>;
+			interrupts = <0 332 4>, <0 332 4>;
+			#iommu-cells = <1>;
+			dma-coherent;
+		};
+
+		sata1_smmu: smmu@e0c00000 {
+			compatible = "arm,mmu-401";
+			reg = <0 0xe0c00000 0 0x10000>;
+			#global-interrupts = <1>;
+			interrupts = <0 331 4>, <0 331 4>;
+			#iommu-cells = <1>;
+			dma-coherent;
+		};
+
 		i2c0: i2c@e1000000 {
 			status = "disabled";
 			compatible = "snps,designware-i2c";
@@ -201,6 +219,10 @@
 			reg = <0 0xe0100000 0 0x10000>;
 			interrupts = <0 3 4>;
 			dma-coherent;
+			iommus = <&sata1_smmu 0x00>,
+				 <&sata1_smmu 0x02>,
+				 <&sata1_smmu 0x40>,
+				 <&sata1_smmu 0x42>;
 		};
 
 		pcie0: pcie@f0000000 {
-- 
2.17.1


  parent reply	other threads:[~2019-11-26 11:43 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-26 11:43 [PATCH v2 0/8] dt: amd-seattle: update SMMU, PCIe and cache descriptions Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 1/8] dt: amd-seattle: remove Husky platform Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 2/8] dt: amd-seattle: remove Overdrive revision A0 support Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 3/8] dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 4/8] dt: amd-seattle: fix PCIe legacy interrupt routing Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 5/8] dt: amd-seattle: add a description of the PCIe SMMU Ard Biesheuvel
2019-11-26 11:43 ` Ard Biesheuvel [this message]
2019-12-03 14:10   ` [PATCH v2 6/8] dt: amd-seattle: add description of the SATA/CCP SMMUs Ard Biesheuvel
2019-12-03 14:33   ` Rob Herring
2019-11-26 11:43 ` [PATCH v2 7/8] dt: amd-seattle: disable IPMI controller and some GPIO blocks on B0 Ard Biesheuvel
2019-11-26 11:43 ` [PATCH v2 8/8] dt: amd-seattle: add a description of the CPUs and caches Ard Biesheuvel
2019-11-26 11:59   ` Mark Rutland

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